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MIPS: DEC: Convert to new irq_chip functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2178/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -17,80 +17,48 @@
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#include <asm/dec/ioasic_addrs.h>
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#include <asm/dec/ioasic_addrs.h>
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#include <asm/dec/ioasic_ints.h>
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#include <asm/dec/ioasic_ints.h>
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static int ioasic_irq_base;
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static int ioasic_irq_base;
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static void unmask_ioasic_irq(struct irq_data *d)
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static inline void unmask_ioasic_irq(unsigned int irq)
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{
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{
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u32 simr;
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u32 simr;
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simr = ioasic_read(IO_REG_SIMR);
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simr = ioasic_read(IO_REG_SIMR);
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simr |= (1 << (irq - ioasic_irq_base));
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simr |= (1 << (d->irq - ioasic_irq_base));
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ioasic_write(IO_REG_SIMR, simr);
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ioasic_write(IO_REG_SIMR, simr);
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}
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}
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static inline void mask_ioasic_irq(unsigned int irq)
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static void mask_ioasic_irq(struct irq_data *d)
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{
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{
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u32 simr;
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u32 simr;
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simr = ioasic_read(IO_REG_SIMR);
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simr = ioasic_read(IO_REG_SIMR);
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simr &= ~(1 << (irq - ioasic_irq_base));
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simr &= ~(1 << (d->irq - ioasic_irq_base));
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ioasic_write(IO_REG_SIMR, simr);
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ioasic_write(IO_REG_SIMR, simr);
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}
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}
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static inline void clear_ioasic_irq(unsigned int irq)
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static void ack_ioasic_irq(struct irq_data *d)
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{
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{
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u32 sir;
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mask_ioasic_irq(d);
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sir = ~(1 << (irq - ioasic_irq_base));
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ioasic_write(IO_REG_SIR, sir);
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}
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static inline void ack_ioasic_irq(unsigned int irq)
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{
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mask_ioasic_irq(irq);
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fast_iob();
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fast_iob();
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}
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}
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static inline void end_ioasic_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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unmask_ioasic_irq(irq);
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}
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static struct irq_chip ioasic_irq_type = {
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static struct irq_chip ioasic_irq_type = {
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.name = "IO-ASIC",
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.name = "IO-ASIC",
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.ack = ack_ioasic_irq,
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.irq_ack = ack_ioasic_irq,
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.mask = mask_ioasic_irq,
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.irq_mask = mask_ioasic_irq,
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.mask_ack = ack_ioasic_irq,
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.irq_mask_ack = ack_ioasic_irq,
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.unmask = unmask_ioasic_irq,
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.irq_unmask = unmask_ioasic_irq,
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};
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};
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#define unmask_ioasic_dma_irq unmask_ioasic_irq
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#define mask_ioasic_dma_irq mask_ioasic_irq
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#define ack_ioasic_dma_irq ack_ioasic_irq
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static inline void end_ioasic_dma_irq(unsigned int irq)
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{
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clear_ioasic_irq(irq);
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fast_iob();
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end_ioasic_irq(irq);
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}
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static struct irq_chip ioasic_dma_irq_type = {
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static struct irq_chip ioasic_dma_irq_type = {
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.name = "IO-ASIC-DMA",
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.name = "IO-ASIC-DMA",
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.ack = ack_ioasic_dma_irq,
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.irq_ack = ack_ioasic_irq,
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.mask = mask_ioasic_dma_irq,
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.irq_mask = mask_ioasic_irq,
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.mask_ack = ack_ioasic_dma_irq,
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.irq_mask_ack = ack_ioasic_irq,
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.unmask = unmask_ioasic_dma_irq,
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.irq_unmask = unmask_ioasic_irq,
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.end = end_ioasic_dma_irq,
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};
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};
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void __init init_ioasic_irqs(int base)
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void __init init_ioasic_irqs(int base)
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{
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{
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int i;
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int i;
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@ -27,43 +27,40 @@
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*/
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*/
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u32 cached_kn02_csr;
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u32 cached_kn02_csr;
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static int kn02_irq_base;
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static int kn02_irq_base;
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static void unmask_kn02_irq(struct irq_data *d)
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static inline void unmask_kn02_irq(unsigned int irq)
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{
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{
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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KN02_CSR);
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KN02_CSR);
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cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
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cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16));
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*csr = cached_kn02_csr;
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*csr = cached_kn02_csr;
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}
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}
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static inline void mask_kn02_irq(unsigned int irq)
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static void mask_kn02_irq(struct irq_data *d)
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{
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{
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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KN02_CSR);
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KN02_CSR);
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cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
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cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16));
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*csr = cached_kn02_csr;
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*csr = cached_kn02_csr;
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}
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}
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static void ack_kn02_irq(unsigned int irq)
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static void ack_kn02_irq(struct irq_data *d)
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{
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{
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mask_kn02_irq(irq);
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mask_kn02_irq(d);
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iob();
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iob();
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}
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}
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static struct irq_chip kn02_irq_type = {
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static struct irq_chip kn02_irq_type = {
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.name = "KN02-CSR",
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.name = "KN02-CSR",
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.ack = ack_kn02_irq,
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.irq_ack = ack_kn02_irq,
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.mask = mask_kn02_irq,
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.irq_mask = mask_kn02_irq,
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.mask_ack = ack_kn02_irq,
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.irq_mask_ack = ack_kn02_irq,
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.unmask = unmask_kn02_irq,
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.irq_unmask = unmask_kn02_irq,
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};
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};
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void __init init_kn02_irqs(int base)
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void __init init_kn02_irqs(int base)
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{
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{
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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