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powerpc/85xx: fix timebase sync issue when CONFIG_HOTPLUG_CPU=n
commitc45361abb9
upstream. When CONFIG_SMP=y, timebase synchronization is required when the second kernel is started. arch/powerpc/kernel/smp.c: int __cpu_up(unsigned int cpu, struct task_struct *tidle) { ... if (smp_ops->give_timebase) smp_ops->give_timebase(); ... } void start_secondary(void *unused) { ... if (smp_ops->take_timebase) smp_ops->take_timebase(); ... } When CONFIG_HOTPLUG_CPU=n and CONFIG_KEXEC_CORE=n, smp_85xx_ops.give_timebase is NULL, smp_85xx_ops.take_timebase is NULL, As a result, the timebase is not synchronized. Timebase synchronization does not depend on CONFIG_HOTPLUG_CPU. Fixes:56f1ba2807
("powerpc/mpc85xx: refactor the PM operations") Cc: stable@vger.kernel.org # v4.6+ Signed-off-by: Xiaoming Ni <nixiaoming@huawei.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210929033646.39630-3-nixiaoming@huawei.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -3,7 +3,9 @@
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# Makefile for the PowerPC 85xx linux kernel.
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# Makefile for the PowerPC 85xx linux kernel.
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#
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#
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_FSL_PMC) += mpc85xx_pm_ops.o
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ifneq ($(CONFIG_FSL_CORENET_RCPM),y)
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obj-$(CONFIG_SMP) += mpc85xx_pm_ops.o
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endif
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obj-y += common.o
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obj-y += common.o
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@ -17,6 +17,7 @@
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static struct ccsr_guts __iomem *guts;
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static struct ccsr_guts __iomem *guts;
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#ifdef CONFIG_FSL_PMC
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static void mpc85xx_irq_mask(int cpu)
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static void mpc85xx_irq_mask(int cpu)
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{
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{
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@ -49,6 +50,7 @@ static void mpc85xx_cpu_up_prepare(int cpu)
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{
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{
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}
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}
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#endif
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static void mpc85xx_freeze_time_base(bool freeze)
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static void mpc85xx_freeze_time_base(bool freeze)
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{
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{
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@ -76,10 +78,12 @@ static const struct of_device_id mpc85xx_smp_guts_ids[] = {
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static const struct fsl_pm_ops mpc85xx_pm_ops = {
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static const struct fsl_pm_ops mpc85xx_pm_ops = {
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.freeze_time_base = mpc85xx_freeze_time_base,
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.freeze_time_base = mpc85xx_freeze_time_base,
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#ifdef CONFIG_FSL_PMC
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.irq_mask = mpc85xx_irq_mask,
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.irq_mask = mpc85xx_irq_mask,
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.irq_unmask = mpc85xx_irq_unmask,
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.irq_unmask = mpc85xx_irq_unmask,
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.cpu_die = mpc85xx_cpu_die,
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.cpu_die = mpc85xx_cpu_die,
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.cpu_up_prepare = mpc85xx_cpu_up_prepare,
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.cpu_up_prepare = mpc85xx_cpu_up_prepare,
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#endif
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};
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};
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int __init mpc85xx_setup_pmc(void)
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int __init mpc85xx_setup_pmc(void)
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@ -40,7 +40,6 @@ struct epapr_spin_table {
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u32 pir;
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u32 pir;
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};
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};
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#ifdef CONFIG_HOTPLUG_CPU
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static u64 timebase;
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static u64 timebase;
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static int tb_req;
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static int tb_req;
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static int tb_valid;
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static int tb_valid;
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@ -112,6 +111,7 @@ static void mpc85xx_take_timebase(void)
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local_irq_restore(flags);
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local_irq_restore(flags);
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}
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static void smp_85xx_cpu_offline_self(void)
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static void smp_85xx_cpu_offline_self(void)
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{
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{
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unsigned int cpu = smp_processor_id();
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unsigned int cpu = smp_processor_id();
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@ -495,21 +495,21 @@ void __init mpc85xx_smp_init(void)
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smp_85xx_ops.probe = NULL;
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smp_85xx_ops.probe = NULL;
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}
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}
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#ifdef CONFIG_HOTPLUG_CPU
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#ifdef CONFIG_FSL_CORENET_RCPM
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#ifdef CONFIG_FSL_CORENET_RCPM
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/* Assign a value to qoriq_pm_ops on PPC_E500MC */
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fsl_rcpm_init();
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fsl_rcpm_init();
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#endif
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#else
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/* Assign a value to qoriq_pm_ops on !PPC_E500MC */
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#ifdef CONFIG_FSL_PMC
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mpc85xx_setup_pmc();
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mpc85xx_setup_pmc();
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#endif
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#endif
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if (qoriq_pm_ops) {
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if (qoriq_pm_ops) {
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smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
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smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
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smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
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smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
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#ifdef CONFIG_HOTPLUG_CPU
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smp_85xx_ops.cpu_offline_self = smp_85xx_cpu_offline_self;
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smp_85xx_ops.cpu_offline_self = smp_85xx_cpu_offline_self;
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smp_85xx_ops.cpu_die = qoriq_cpu_kill;
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smp_85xx_ops.cpu_die = qoriq_cpu_kill;
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}
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#endif
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#endif
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}
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smp_ops = &smp_85xx_ops;
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smp_ops = &smp_85xx_ops;
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#ifdef CONFIG_KEXEC_CORE
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#ifdef CONFIG_KEXEC_CORE
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