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Merge nommu tree
Fix merge conflict in arch/arm/mm/proc-xscale.S Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
Russell King
commit
0003cedfc5
@ -358,7 +358,7 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
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str r1, [r0]
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mov pc, lr
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__armv4_cache_on:
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__armv4_mmu_cache_on:
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mov r12, lr
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bl __setup_mmu
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mov r0, #0
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@ -367,24 +367,24 @@ __armv4_cache_on:
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
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orr r0, r0, #0x0030
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bl __common_cache_on
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bl __common_mmu_cache_on
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
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mov pc, r12
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__arm6_cache_on:
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__arm6_mmu_cache_on:
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mov r12, lr
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bl __setup_mmu
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
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mov r0, #0x30
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bl __common_cache_on
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bl __common_mmu_cache_on
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mov r0, #0
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mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
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mov pc, r12
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__common_cache_on:
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__common_mmu_cache_on:
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#ifndef DEBUG
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orr r0, r0, #0x000d @ Write buffer, mmu
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#endif
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@ -471,12 +471,12 @@ call_cache_fn: adr r12, proc_types
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proc_types:
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.word 0x41560600 @ ARM6/610
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.word 0xffffffe0
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b __arm6_cache_off @ works, but slow
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b __arm6_cache_off
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b __arm6_mmu_cache_off @ works, but slow
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b __arm6_mmu_cache_off
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mov pc, lr
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@ b __arm6_cache_on @ untested
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@ b __arm6_cache_off
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@ b __armv3_cache_flush
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@ b __arm6_mmu_cache_on @ untested
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@ b __arm6_mmu_cache_off
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@ b __armv3_mmu_cache_flush
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.word 0x00000000 @ old ARM ID
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.word 0x0000f000
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@ -486,14 +486,14 @@ proc_types:
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.word 0x41007000 @ ARM7/710
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.word 0xfff8fe00
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b __arm7_cache_off
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b __arm7_cache_off
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b __arm7_mmu_cache_off
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b __arm7_mmu_cache_off
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mov pc, lr
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.word 0x41807200 @ ARM720T (writethrough)
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.word 0xffffff00
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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mov pc, lr
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.word 0x00007000 @ ARM7 IDs
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@ -506,41 +506,41 @@ proc_types:
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.word 0x4401a100 @ sa110 / sa1100
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.word 0xffffffe0
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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.word 0x6901b110 @ sa1110
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.word 0xfffffff0
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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@ These match on the architecture ID
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.word 0x00020000 @ ARMv4T
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.word 0x000f0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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.word 0x00050000 @ ARMv5TE
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.word 0x000f0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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.word 0x00060000 @ ARMv5TEJ
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.word 0x000f0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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.word 0x00070000 @ ARMv6
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.word 0x000f0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv6_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv6_mmu_cache_flush
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.word 0 @ unrecognised type
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.word 0
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@ -562,7 +562,7 @@ proc_types:
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cache_off: mov r3, #12 @ cache_off function
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b call_cache_fn
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__armv4_cache_off:
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__armv4_mmu_cache_off:
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mrc p15, 0, r0, c1, c0
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bic r0, r0, #0x000d
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mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
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@ -571,15 +571,15 @@ __armv4_cache_off:
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mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
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mov pc, lr
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__arm6_cache_off:
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__arm6_mmu_cache_off:
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mov r0, #0x00000030 @ ARM6 control reg.
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b __armv3_cache_off
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b __armv3_mmu_cache_off
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__arm7_cache_off:
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__arm7_mmu_cache_off:
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mov r0, #0x00000070 @ ARM7 control reg.
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b __armv3_cache_off
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b __armv3_mmu_cache_off
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__armv3_cache_off:
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__armv3_mmu_cache_off:
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mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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@ -601,7 +601,7 @@ cache_clean_flush:
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mov r3, #16
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b call_cache_fn
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__armv6_cache_flush:
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__armv6_mmu_cache_flush:
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mov r1, #0
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mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
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mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
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@ -609,7 +609,7 @@ __armv6_cache_flush:
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mov pc, lr
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__armv4_cache_flush:
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__armv4_mmu_cache_flush:
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mov r2, #64*1024 @ default: 32K dcache size (*2)
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mov r11, #32 @ default: 32 byte line size
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mrc p15, 0, r3, c0, c0, 1 @ read cache type
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@ -637,7 +637,7 @@ no_cache_id:
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mov pc, lr
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__armv3_cache_flush:
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__armv3_mmu_cache_flush:
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mov r1, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mov pc, lr
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@ -81,6 +81,7 @@
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ENTRY(stext)
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msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
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@ and irqs disabled
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mrc p15, 0, r9, c0, c0 @ get processor id
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bl __lookup_processor_type @ r5=procinfo r9=cpuid
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movs r10, r5 @ invalid processor (r5=0)?
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beq __error_p @ yes, error 'p'
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@ -155,6 +156,7 @@ ENTRY(secondary_startup)
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* as it has already been validated by the primary processor.
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*/
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msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
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mrc p15, 0, r9, c0, c0 @ get processor id
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bl __lookup_processor_type
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movs r10, r5 @ invalid processor?
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moveq r0, #'p' @ yes, error 'p'
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@ -449,19 +451,19 @@ __error:
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* (and therefore, we are not in the correct address space). We have to
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* calculate the offset.
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*
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* r9 = cpuid
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* Returns:
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* r3, r4, r6 corrupted
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* r5 = proc_info pointer in physical address space
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* r9 = cpuid
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* r9 = cpuid (preserved)
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*/
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.type __lookup_processor_type, %function
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__lookup_processor_type:
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adr r3, 3f
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ldmda r3, {r5, r6, r9}
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sub r3, r3, r9 @ get offset between virt&phys
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ldmda r3, {r5 - r7}
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sub r3, r3, r7 @ get offset between virt&phys
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add r5, r5, r3 @ convert virt addresses to
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add r6, r6, r3 @ physical address space
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mrc p15, 0, r9, c0, c0 @ get processor id
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1: ldmia r5, {r3, r4} @ value, mask
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and r4, r4, r9 @ mask wanted bits
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teq r3, r4
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@ -476,10 +478,11 @@ __lookup_processor_type:
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* This provides a C-API version of the above function.
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*/
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ENTRY(lookup_processor_type)
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stmfd sp!, {r4 - r6, r9, lr}
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stmfd sp!, {r4 - r7, r9, lr}
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mov r9, r0
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bl __lookup_processor_type
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mov r0, r5
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ldmfd sp!, {r4 - r6, r9, pc}
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ldmfd sp!, {r4 - r7, r9, pc}
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/*
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* Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for
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@ -278,7 +278,7 @@ int cpu_architecture(void)
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* These functions re-use the assembly code in head.S, which
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* already provide the required functionality.
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*/
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extern struct proc_info_list *lookup_processor_type(void);
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extern struct proc_info_list *lookup_processor_type(unsigned int);
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extern struct machine_desc *lookup_machine_type(unsigned int);
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static void __init setup_processor(void)
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@ -290,7 +290,7 @@ static void __init setup_processor(void)
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* types. The linker builds this table for us from the
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* entries in arch/arm/mm/proc-*.S
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*/
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list = lookup_processor_type();
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list = lookup_processor_type(processor_id);
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if (!list) {
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printk("CPU configuration botched (ID %08x), unable "
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"to continue.\n", processor_id);
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@ -234,7 +234,12 @@ asmlinkage int sys_ipc(uint call, int first, int second, int third,
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*/
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asmlinkage int sys_fork(struct pt_regs *regs)
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{
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#ifdef CONFIG_MMU
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return do_fork(SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL);
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#else
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/* can not support in nommu mode */
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return(-EINVAL);
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#endif
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}
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/* Clone a task - this clones the calling program thread.
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@ -26,6 +26,7 @@
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/page.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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@ -266,12 +266,18 @@ config CPU_32v6K
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# This defines the compiler instruction set which depends on the machine type.
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config CPU_32v3
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bool
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select TLS_REG_EMUL if SMP
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select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
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config CPU_32v4
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bool
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select TLS_REG_EMUL if SMP
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select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
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config CPU_32v5
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bool
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select TLS_REG_EMUL if SMP
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select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
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config CPU_32v6
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bool
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@ -417,7 +423,6 @@ config CPU_BPREDICT_DISABLE
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config TLS_REG_EMUL
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bool
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default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
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help
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An SMP system using a pre-ARMv6 processor (there are apparently
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a few prototypes like that in existence) and therefore access to
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@ -436,7 +441,6 @@ config HAS_TLS_REG
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config NEEDS_SYSCALL_FOR_CMPXCHG
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bool
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default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
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help
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SMP on a pre-ARMv6 processor? Well OK then.
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Forget about fast user space cmpxchg support.
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@ -29,6 +29,7 @@
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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@ -29,6 +29,7 @@
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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@ -18,6 +18,7 @@
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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@ -18,6 +18,7 @@
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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@ -14,6 +14,7 @@
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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@ -34,6 +34,7 @@
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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@ -28,6 +28,7 @@
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#include <linux/config.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/page.h>
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@ -29,6 +29,7 @@
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#include <linux/config.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/page.h>
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@ -51,6 +51,7 @@
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#include <linux/config.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/page.h>
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@ -28,6 +28,7 @@
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#include <linux/config.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/page.h>
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@ -18,6 +18,7 @@
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#include <asm/asm-offsets.h>
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#include <asm/procinfo.h>
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#include <asm/hardware.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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@ -23,6 +23,7 @@
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#include <asm/asm-offsets.h>
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#include <asm/procinfo.h>
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#include <asm/hardware.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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/*
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@ -14,6 +14,7 @@
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#include <asm/asm-offsets.h>
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||||
#include <asm/hardware/arm_scu.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
#include "proc-macros.S"
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include "proc-macros.S"
|
||||
|
||||
@ -10,10 +10,15 @@
|
||||
#ifndef _ASMARM_PGALLOC_H
|
||||
#define _ASMARM_PGALLOC_H
|
||||
|
||||
#include <asm/domain.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
|
||||
#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
|
||||
|
||||
/*
|
||||
* Since we have only two-level page tables, these are trivial
|
||||
*/
|
||||
|
||||
88
include/asm-arm/pgtable-hwdef.h
Normal file
88
include/asm-arm/pgtable-hwdef.h
Normal file
@ -0,0 +1,88 @@
|
||||
/*
|
||||
* linux/include/asm-arm/pgtable-hwdef.h
|
||||
*
|
||||
* Copyright (C) 1995-2002 Russell King
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef _ASMARM_PGTABLE_HWDEF_H
|
||||
#define _ASMARM_PGTABLE_HWDEF_H
|
||||
|
||||
/*
|
||||
* Hardware page table definitions.
|
||||
*
|
||||
* + Level 1 descriptor (PMD)
|
||||
* - common
|
||||
*/
|
||||
#define PMD_TYPE_MASK (3 << 0)
|
||||
#define PMD_TYPE_FAULT (0 << 0)
|
||||
#define PMD_TYPE_TABLE (1 << 0)
|
||||
#define PMD_TYPE_SECT (2 << 0)
|
||||
#define PMD_BIT4 (1 << 4)
|
||||
#define PMD_DOMAIN(x) ((x) << 5)
|
||||
#define PMD_PROTECTION (1 << 9) /* v5 */
|
||||
/*
|
||||
* - section
|
||||
*/
|
||||
#define PMD_SECT_BUFFERABLE (1 << 2)
|
||||
#define PMD_SECT_CACHEABLE (1 << 3)
|
||||
#define PMD_SECT_AP_WRITE (1 << 10)
|
||||
#define PMD_SECT_AP_READ (1 << 11)
|
||||
#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
|
||||
#define PMD_SECT_APX (1 << 15) /* v6 */
|
||||
#define PMD_SECT_S (1 << 16) /* v6 */
|
||||
#define PMD_SECT_nG (1 << 17) /* v6 */
|
||||
#define PMD_SECT_SUPER (1 << 18) /* v6 */
|
||||
|
||||
#define PMD_SECT_UNCACHED (0)
|
||||
#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
|
||||
#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
|
||||
#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
|
||||
#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
|
||||
#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
|
||||
#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
|
||||
|
||||
/*
|
||||
* - coarse table (not used)
|
||||
*/
|
||||
|
||||
/*
|
||||
* + Level 2 descriptor (PTE)
|
||||
* - common
|
||||
*/
|
||||
#define PTE_TYPE_MASK (3 << 0)
|
||||
#define PTE_TYPE_FAULT (0 << 0)
|
||||
#define PTE_TYPE_LARGE (1 << 0)
|
||||
#define PTE_TYPE_SMALL (2 << 0)
|
||||
#define PTE_TYPE_EXT (3 << 0) /* v5 */
|
||||
#define PTE_BUFFERABLE (1 << 2)
|
||||
#define PTE_CACHEABLE (1 << 3)
|
||||
|
||||
/*
|
||||
* - extended small page/tiny page
|
||||
*/
|
||||
#define PTE_EXT_XN (1 << 0) /* v6 */
|
||||
#define PTE_EXT_AP_MASK (3 << 4)
|
||||
#define PTE_EXT_AP0 (1 << 4)
|
||||
#define PTE_EXT_AP1 (2 << 4)
|
||||
#define PTE_EXT_AP_UNO_SRO (0 << 4)
|
||||
#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
|
||||
#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
|
||||
#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
|
||||
#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
|
||||
#define PTE_EXT_APX (1 << 9) /* v6 */
|
||||
#define PTE_EXT_SHARED (1 << 10) /* v6 */
|
||||
#define PTE_EXT_NG (1 << 11) /* v6 */
|
||||
|
||||
/*
|
||||
* - small page
|
||||
*/
|
||||
#define PTE_SMALL_AP_MASK (0xff << 4)
|
||||
#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
|
||||
#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
|
||||
#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
|
||||
#define PTE_SMALL_AP_URW_SRW (0xff << 4)
|
||||
|
||||
#endif
|
||||
@ -136,81 +136,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
|
||||
#define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT)
|
||||
#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
|
||||
|
||||
/*
|
||||
* Hardware page table definitions.
|
||||
*
|
||||
* + Level 1 descriptor (PMD)
|
||||
* - common
|
||||
*/
|
||||
#define PMD_TYPE_MASK (3 << 0)
|
||||
#define PMD_TYPE_FAULT (0 << 0)
|
||||
#define PMD_TYPE_TABLE (1 << 0)
|
||||
#define PMD_TYPE_SECT (2 << 0)
|
||||
#define PMD_BIT4 (1 << 4)
|
||||
#define PMD_DOMAIN(x) ((x) << 5)
|
||||
#define PMD_PROTECTION (1 << 9) /* v5 */
|
||||
/*
|
||||
* - section
|
||||
*/
|
||||
#define PMD_SECT_BUFFERABLE (1 << 2)
|
||||
#define PMD_SECT_CACHEABLE (1 << 3)
|
||||
#define PMD_SECT_AP_WRITE (1 << 10)
|
||||
#define PMD_SECT_AP_READ (1 << 11)
|
||||
#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
|
||||
#define PMD_SECT_APX (1 << 15) /* v6 */
|
||||
#define PMD_SECT_S (1 << 16) /* v6 */
|
||||
#define PMD_SECT_nG (1 << 17) /* v6 */
|
||||
#define PMD_SECT_SUPER (1 << 18) /* v6 */
|
||||
|
||||
#define PMD_SECT_UNCACHED (0)
|
||||
#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
|
||||
#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
|
||||
#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
|
||||
#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
|
||||
#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
|
||||
#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
|
||||
|
||||
/*
|
||||
* - coarse table (not used)
|
||||
*/
|
||||
|
||||
/*
|
||||
* + Level 2 descriptor (PTE)
|
||||
* - common
|
||||
*/
|
||||
#define PTE_TYPE_MASK (3 << 0)
|
||||
#define PTE_TYPE_FAULT (0 << 0)
|
||||
#define PTE_TYPE_LARGE (1 << 0)
|
||||
#define PTE_TYPE_SMALL (2 << 0)
|
||||
#define PTE_TYPE_EXT (3 << 0) /* v5 */
|
||||
#define PTE_BUFFERABLE (1 << 2)
|
||||
#define PTE_CACHEABLE (1 << 3)
|
||||
|
||||
/*
|
||||
* - extended small page/tiny page
|
||||
*/
|
||||
#define PTE_EXT_XN (1 << 0) /* v6 */
|
||||
#define PTE_EXT_AP_MASK (3 << 4)
|
||||
#define PTE_EXT_AP0 (1 << 4)
|
||||
#define PTE_EXT_AP1 (2 << 4)
|
||||
#define PTE_EXT_AP_UNO_SRO (0 << 4)
|
||||
#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
|
||||
#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
|
||||
#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
|
||||
#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
|
||||
#define PTE_EXT_APX (1 << 9) /* v6 */
|
||||
#define PTE_EXT_SHARED (1 << 10) /* v6 */
|
||||
#define PTE_EXT_NG (1 << 11) /* v6 */
|
||||
|
||||
/*
|
||||
* - small page
|
||||
*/
|
||||
#define PTE_SMALL_AP_MASK (0xff << 4)
|
||||
#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
|
||||
#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
|
||||
#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
|
||||
#define PTE_SMALL_AP_URW_SRW (0xff << 4)
|
||||
|
||||
/*
|
||||
* "Linux" PTE definitions.
|
||||
*
|
||||
@ -236,11 +161,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/domain.h>
|
||||
|
||||
#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
|
||||
#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
|
||||
|
||||
/*
|
||||
* The following macros handle the cache and bufferable bits...
|
||||
*/
|
||||
|
||||
@ -19,6 +19,14 @@
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
#ifndef CONFIG_MMU
|
||||
|
||||
#include <linux/pagemap.h>
|
||||
#include <asm-generic/tlb.h>
|
||||
|
||||
#else /* !CONFIG_MMU */
|
||||
|
||||
#include <asm/pgalloc.h>
|
||||
|
||||
/*
|
||||
@ -82,4 +90,5 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
|
||||
|
||||
#define tlb_migrate_finish(mm) do { } while (0)
|
||||
|
||||
#endif /* CONFIG_MMU */
|
||||
#endif
|
||||
|
||||
@ -11,6 +11,13 @@
|
||||
#define _ASMARM_TLBFLUSH_H
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
#ifndef CONFIG_MMU
|
||||
|
||||
#define tlb_flush(tlb) ((void) tlb)
|
||||
|
||||
#else /* CONFIG_MMU */
|
||||
|
||||
#include <asm/glue.h>
|
||||
|
||||
#define TLB_V3_PAGE (1 << 0)
|
||||
@ -423,4 +430,6 @@ extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_MMU */
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user