2016-12-10 02:53:05 +08:00
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Buffer Sharing and Synchronization
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==================================
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The dma-buf subsystem provides the framework for sharing buffers for
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hardware (DMA) access across multiple device drivers and subsystems, and
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for synchronizing asynchronous hardware access.
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This is used, for example, by drm "prime" multi-GPU support, but is of
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course not limited to GPU use cases.
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The three main components of this are: (1) dma-buf, representing a
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sg_table and exposed to userspace as a file descriptor to allow passing
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between devices, (2) fence, which provides a mechanism to signal when
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2020-04-20 15:41:15 +08:00
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one device has finished access, and (3) reservation, which manages the
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shared or exclusive fence(s) associated with the buffer.
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Shared DMA Buffers
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------------------
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2016-12-10 02:53:07 +08:00
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This document serves as a guide to device-driver writers on what is the dma-buf
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buffer sharing API, how to use it for exporting and using shared buffers.
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Any device driver which wishes to be a part of DMA buffer sharing, can do so as
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either the 'exporter' of buffers, or the 'user' or 'importer' of buffers.
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Say a driver A wants to use buffers created by driver B, then we call B as the
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exporter, and A as buffer-user/importer.
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The exporter
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- implements and manages operations in :c:type:`struct dma_buf_ops
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<dma_buf_ops>` for the buffer,
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- allows other users to share the buffer by using dma_buf sharing APIs,
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- manages the details of buffer allocation, wrapped in a :c:type:`struct
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dma_buf <dma_buf>`,
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- decides about the actual backing storage where this allocation happens,
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- and takes care of any migration of scatterlist - for all (shared) users of
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this buffer.
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The buffer-user
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- is one of (many) sharing users of the buffer.
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- doesn't need to worry about how the buffer is allocated, or where.
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- and needs a mechanism to get access to the scatterlist that makes up this
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buffer in memory, mapped into its own address space, so it can access the
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same area of memory. This interface is provided by :c:type:`struct
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dma_buf_attachment <dma_buf_attachment>`.
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2016-12-10 05:50:55 +08:00
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Any exporters or users of the dma-buf buffer sharing framework must have a
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'select DMA_SHARED_BUFFER' in their respective Kconfigs.
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Userspace Interface Notes
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~~~~~~~~~~~~~~~~~~~~~~~~~
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Mostly a DMA buffer file descriptor is simply an opaque object for userspace,
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and hence the generic interface exposed is very minimal. There's a few things to
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consider though:
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- Since kernel 3.12 the dma-buf FD supports the llseek system call, but only
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with offset=0 and whence=SEEK_END|SEEK_SET. SEEK_SET is supported to allow
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the usual size discover pattern size = SEEK_END(0); SEEK_SET(0). Every other
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llseek operation will report -EINVAL.
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If llseek on dma-buf FDs isn't support the kernel will report -ESPIPE for all
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cases. Userspace can use this to detect support for discovering the dma-buf
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size using llseek.
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- In order to avoid fd leaks on exec, the FD_CLOEXEC flag must be set
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on the file descriptor. This is not just a resource leak, but a
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potential security hole. It could give the newly exec'd application
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access to buffers, via the leaked fd, to which it should otherwise
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not be permitted access.
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The problem with doing this via a separate fcntl() call, versus doing it
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atomically when the fd is created, is that this is inherently racy in a
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multi-threaded app[3]. The issue is made worse when it is library code
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opening/creating the file descriptor, as the application may not even be
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aware of the fd's.
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To avoid this problem, userspace must have a way to request O_CLOEXEC
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flag be set when the dma-buf fd is created. So any API provided by
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the exporting driver to create a dmabuf fd must provide a way to let
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userspace control setting of O_CLOEXEC flag passed in to dma_buf_fd().
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- Memory mapping the contents of the DMA buffer is also supported. See the
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discussion below on `CPU Access to DMA Buffer Objects`_ for the full details.
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2020-09-09 22:10:51 +08:00
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- The DMA buffer FD is also pollable, see `Implicit Fence Poll Support`_ below for
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details.
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2021-06-18 03:42:58 +08:00
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- The DMA buffer FD also supports a few dma-buf-specific ioctls, see
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`DMA Buffer ioctls`_ below for details.
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2016-12-10 02:53:07 +08:00
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Basic Operation and Device DMA Access
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. kernel-doc:: drivers/dma-buf/dma-buf.c
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:doc: dma buf device access
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2016-12-10 02:53:08 +08:00
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CPU Access to DMA Buffer Objects
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. kernel-doc:: drivers/dma-buf/dma-buf.c
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:doc: cpu access
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2020-06-12 15:05:35 +08:00
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Implicit Fence Poll Support
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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2016-12-10 05:50:55 +08:00
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.. kernel-doc:: drivers/dma-buf/dma-buf.c
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2020-06-12 15:05:35 +08:00
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:doc: implicit fence polling
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2021-06-04 05:47:51 +08:00
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DMA-BUF statistics
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~~~~~~~~~~~~~~~~~~
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.. kernel-doc:: drivers/dma-buf/dma-buf-sysfs-stats.c
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:doc: overview
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2021-06-18 03:42:58 +08:00
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DMA Buffer ioctls
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~~~~~~~~~~~~~~~~~
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.. kernel-doc:: include/uapi/linux/dma-buf.h
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2016-12-10 02:53:07 +08:00
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Kernel Functions and Structures Reference
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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2016-12-10 02:53:05 +08:00
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.. kernel-doc:: drivers/dma-buf/dma-buf.c
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:export:
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.. kernel-doc:: include/linux/dma-buf.h
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:internal:
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Reservation Objects
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-------------------
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2019-09-27 19:15:04 +08:00
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.. kernel-doc:: drivers/dma-buf/dma-resv.c
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:doc: Reservation Object Overview
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2019-09-27 19:15:04 +08:00
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.. kernel-doc:: drivers/dma-buf/dma-resv.c
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:export:
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2019-09-27 19:15:04 +08:00
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.. kernel-doc:: include/linux/dma-resv.h
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:internal:
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DMA Fences
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----------
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2018-07-04 17:29:09 +08:00
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.. kernel-doc:: drivers/dma-buf/dma-fence.c
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:doc: DMA fences overview
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dma-fence: prime lockdep annotations
Two in one go:
- it is allowed to call dma_fence_wait() while holding a
dma_resv_lock(). This is fundamental to how eviction works with ttm,
so required.
- it is allowed to call dma_fence_wait() from memory reclaim contexts,
specifically from shrinker callbacks (which i915 does), and from mmu
notifier callbacks (which amdgpu does, and which i915 sometimes also
does, and probably always should, but that's kinda a debate). Also
for stuff like HMM we really need to be able to do this, or things
get real dicey.
Consequence is that any critical path necessary to get to a
dma_fence_signal for a fence must never a) call dma_resv_lock nor b)
allocate memory with GFP_KERNEL. Also by implication of
dma_resv_lock(), no userspace faulting allowed. That's some supremely
obnoxious limitations, which is why we need to sprinkle the right
annotations to all relevant paths.
The one big locking context we're leaving out here is mmu notifiers,
added in
commit 23b68395c7c78a764e8963fc15a7cfd318bf187f
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Mon Aug 26 22:14:21 2019 +0200
mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end
that one covers a lot of other callsites, and it's also allowed to
wait on dma-fences from mmu notifiers. But there's no ready-made
functions exposed to prime this, so I've left it out for now.
v2: Also track against mmu notifier context.
v3: kerneldoc to spec the cross-driver contract. Note that currently
i915 throws in a hard-coded 10s timeout on foreign fences (not sure
why that was done, but it's there), which is why that rule is worded
with SHOULD instead of MUST.
Also some of the mmu_notifier/shrinker rules might surprise SoC
drivers, I haven't fully audited them all. Which is infeasible anyway,
we'll need to run them with lockdep and dma-fence annotations and see
what goes boom.
v4: A spelling fix from Mika
v5: #ifdef for CONFIG_MMU_NOTIFIER. Reported by 0day. Unfortunately
this means lockdep enforcement is slightly inconsistent, it won't spot
GFP_NOIO and GFP_NOFS allocations in the wrong spot if
CONFIG_MMU_NOTIFIER is disabled in the kernel config. Oh well.
v5: Note that only drivers/gpu has a reasonable (or at least
historical) excuse to use dma_fence_wait() from shrinker and mmu
notifier callbacks. Everyone else should either have a better memory
manager model, or better hardware. This reflects discussions with
Jason Gunthorpe.
Cc: Jason Gunthorpe <jgg@mellanox.com>
Cc: Felix Kuehling <Felix.Kuehling@amd.com>
Cc: kernel test robot <lkp@intel.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@intel.com> (v4)
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Thomas Hellstrom <thomas.hellstrom@intel.com>
Cc: linux-media@vger.kernel.org
Cc: linaro-mm-sig@lists.linaro.org
Cc: linux-rdma@vger.kernel.org
Cc: amd-gfx@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200707201229.472834-3-daniel.vetter@ffwll.ch
2020-07-08 04:12:06 +08:00
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DMA Fence Cross-Driver Contract
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. kernel-doc:: drivers/dma-buf/dma-fence.c
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:doc: fence cross-driver contract
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dma-fence: basic lockdep annotations
Design is similar to the lockdep annotations for workers, but with
some twists:
- We use a read-lock for the execution/worker/completion side, so that
this explicit annotation can be more liberally sprinkled around.
With read locks lockdep isn't going to complain if the read-side
isn't nested the same way under all circumstances, so ABBA deadlocks
are ok. Which they are, since this is an annotation only.
- We're using non-recursive lockdep read lock mode, since in recursive
read lock mode lockdep does not catch read side hazards. And we
_very_ much want read side hazards to be caught. For full details of
this limitation see
commit e91498589746065e3ae95d9a00b068e525eec34f
Author: Peter Zijlstra <peterz@infradead.org>
Date: Wed Aug 23 13:13:11 2017 +0200
locking/lockdep/selftests: Add mixed read-write ABBA tests
- To allow nesting of the read-side explicit annotations we explicitly
keep track of the nesting. lock_is_held() allows us to do that.
- The wait-side annotation is a write lock, and entirely done within
dma_fence_wait() for everyone by default.
- To be able to freely annotate helper functions I want to make it ok
to call dma_fence_begin/end_signalling from soft/hardirq context.
First attempt was using the hardirq locking context for the write
side in lockdep, but this forces all normal spinlocks nested within
dma_fence_begin/end_signalling to be spinlocks. That bollocks.
The approach now is to simple check in_atomic(), and for these cases
entirely rely on the might_sleep() check in dma_fence_wait(). That
will catch any wrong nesting against spinlocks from soft/hardirq
contexts.
The idea here is that every code path that's critical for eventually
signalling a dma_fence should be annotated with
dma_fence_begin/end_signalling. The annotation ideally starts right
after a dma_fence is published (added to a dma_resv, exposed as a
sync_file fd, attached to a drm_syncobj fd, or anything else that
makes the dma_fence visible to other kernel threads), up to and
including the dma_fence_wait(). Examples are irq handlers, the
scheduler rt threads, the tail of execbuf (after the corresponding
fences are visible), any workers that end up signalling dma_fences and
really anything else. Not annotated should be code paths that only
complete fences opportunistically as the gpu progresses, like e.g.
shrinker/eviction code.
The main class of deadlocks this is supposed to catch are:
Thread A:
mutex_lock(A);
mutex_unlock(A);
dma_fence_signal();
Thread B:
mutex_lock(A);
dma_fence_wait();
mutex_unlock(A);
Thread B is blocked on A signalling the fence, but A never gets around
to that because it cannot acquire the lock A.
Note that dma_fence_wait() is allowed to be nested within
dma_fence_begin/end_signalling sections. To allow this to happen the
read lock needs to be upgraded to a write lock, which means that any
other lock is acquired between the dma_fence_begin_signalling() call and
the call to dma_fence_wait(), and still held, this will result in an
immediate lockdep complaint. The only other option would be to not
annotate such calls, defeating the point. Therefore these annotations
cannot be sprinkled over the code entirely mindless to avoid false
positives.
Originally I hope that the cross-release lockdep extensions would
alleviate the need for explicit annotations:
https://lwn.net/Articles/709849/
But there's a few reasons why that's not an option:
- It's not happening in upstream, since it got reverted due to too
many false positives:
commit e966eaeeb623f09975ef362c2866fae6f86844f9
Author: Ingo Molnar <mingo@kernel.org>
Date: Tue Dec 12 12:31:16 2017 +0100
locking/lockdep: Remove the cross-release locking checks
This code (CONFIG_LOCKDEP_CROSSRELEASE=y and CONFIG_LOCKDEP_COMPLETIONS=y),
while it found a number of old bugs initially, was also causing too many
false positives that caused people to disable lockdep - which is arguably
a worse overall outcome.
- cross-release uses the complete() call to annotate the end of
critical sections, for dma_fence that would be dma_fence_signal().
But we do not want all dma_fence_signal() calls to be treated as
critical, since many are opportunistic cleanup of gpu requests. If
these get stuck there's still the main completion interrupt and
workers who can unblock everyone. Automatically annotating all
dma_fence_signal() calls would hence cause false positives.
- cross-release had some educated guesses for when a critical section
starts, like fresh syscall or fresh work callback. This would again
cause false positives without explicit annotations, since for
dma_fence the critical sections only starts when we publish a fence.
- Furthermore there can be cases where a thread never does a
dma_fence_signal, but is still critical for reaching completion of
fences. One example would be a scheduler kthread which picks up jobs
and pushes them into hardware, where the interrupt handler or
another completion thread calls dma_fence_signal(). But if the
scheduler thread hangs, then all the fences hang, hence we need to
manually annotate it. cross-release aimed to solve this by chaining
cross-release dependencies, but the dependency from scheduler thread
to the completion interrupt handler goes through hw where
cross-release code can't observe it.
In short, without manual annotations and careful review of the start
and end of critical sections, cross-relese dependency tracking doesn't
work. We need explicit annotations.
v2: handle soft/hardirq ctx better against write side and dont forget
EXPORT_SYMBOL, drivers can't use this otherwise.
v3: Kerneldoc.
v4: Some spelling fixes from Mika
v5: Amend commit message to explain in detail why cross-release isn't
the solution.
v6: Pull out misplaced .rst hunk.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Cc: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Thomas Hellstrom <thomas.hellstrom@intel.com>
Cc: linux-media@vger.kernel.org
Cc: linaro-mm-sig@lists.linaro.org
Cc: linux-rdma@vger.kernel.org
Cc: amd-gfx@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200707201229.472834-2-daniel.vetter@ffwll.ch
2020-07-08 04:12:05 +08:00
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DMA Fence Signalling Annotations
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. kernel-doc:: drivers/dma-buf/dma-fence.c
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:doc: fence signalling annotation
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2018-07-04 17:29:09 +08:00
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DMA Fences Functions Reference
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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2016-12-10 02:53:05 +08:00
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.. kernel-doc:: drivers/dma-buf/dma-fence.c
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:export:
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.. kernel-doc:: include/linux/dma-fence.h
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:internal:
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DMA Fence Array
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~~~~~~~~~~~~~~~
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.. kernel-doc:: drivers/dma-buf/dma-fence-array.c
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:export:
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.. kernel-doc:: include/linux/dma-fence-array.h
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:internal:
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2021-05-21 16:24:57 +08:00
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DMA Fence Chain
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~~~~~~~~~~~~~~~
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.. kernel-doc:: drivers/dma-buf/dma-fence-chain.c
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:export:
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.. kernel-doc:: include/linux/dma-fence-chain.h
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:internal:
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2022-03-11 17:27:53 +08:00
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DMA Fence unwrap
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~~~~~~~~~~~~~~~~
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.. kernel-doc:: include/linux/dma-fence-unwrap.h
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:internal:
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2016-12-10 02:53:05 +08:00
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DMA Fence uABI/Sync File
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~~~~~~~~~~~~~~~~~~~~~~~~
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.. kernel-doc:: drivers/dma-buf/sync_file.c
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:export:
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.. kernel-doc:: include/linux/sync_file.h
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:internal:
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2020-07-09 20:33:38 +08:00
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Indefinite DMA Fences
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2020-08-24 07:41:59 +08:00
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~~~~~~~~~~~~~~~~~~~~~
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2020-07-09 20:33:38 +08:00
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2020-12-05 04:02:42 +08:00
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At various times struct dma_fence with an indefinite time until dma_fence_wait()
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2020-07-09 20:33:38 +08:00
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finishes have been proposed. Examples include:
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* Future fences, used in HWC1 to signal when a buffer isn't used by the display
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any longer, and created with the screen update that makes the buffer visible.
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The time this fence completes is entirely under userspace's control.
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* Proxy fences, proposed to handle &drm_syncobj for which the fence has not yet
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been set. Used to asynchronously delay command submission.
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* Userspace fences or gpu futexes, fine-grained locking within a command buffer
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that userspace uses for synchronization across engines or with the CPU, which
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are then imported as a DMA fence for integration into existing winsys
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protocols.
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* Long-running compute command buffers, while still using traditional end of
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batch DMA fences for memory management instead of context preemption DMA
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fences which get reattached when the compute job is rescheduled.
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Common to all these schemes is that userspace controls the dependencies of these
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fences and controls when they fire. Mixing indefinite fences with normal
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in-kernel DMA fences does not work, even when a fallback timeout is included to
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protect against malicious userspace:
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* Only the kernel knows about all DMA fence dependencies, userspace is not aware
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of dependencies injected due to memory management or scheduler decisions.
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* Only userspace knows about all dependencies in indefinite fences and when
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exactly they will complete, the kernel has no visibility.
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Furthermore the kernel has to be able to hold up userspace command submission
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for memory management needs, which means we must support indefinite fences being
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dependent upon DMA fences. If the kernel also support indefinite fences in the
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kernel like a DMA fence, like any of the above proposal would, there is the
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potential for deadlocks.
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.. kernel-render:: DOT
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:alt: Indefinite Fencing Dependency Cycle
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:caption: Indefinite Fencing Dependency Cycle
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digraph "Fencing Cycle" {
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node [shape=box bgcolor=grey style=filled]
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kernel [label="Kernel DMA Fences"]
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userspace [label="userspace controlled fences"]
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kernel -> userspace [label="memory management"]
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userspace -> kernel [label="Future fence, fence proxy, ..."]
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{ rank=same; kernel userspace }
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}
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This means that the kernel might accidentally create deadlocks
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through memory management dependencies which userspace is unaware of, which
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randomly hangs workloads until the timeout kicks in. Workloads, which from
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userspace's perspective, do not contain a deadlock. In such a mixed fencing
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architecture there is no single entity with knowledge of all dependencies.
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Thefore preventing such deadlocks from within the kernel is not possible.
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The only solution to avoid dependencies loops is by not allowing indefinite
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fences in the kernel. This means:
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* No future fences, proxy fences or userspace fences imported as DMA fences,
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with or without a timeout.
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* No DMA fences that signal end of batchbuffer for command submission where
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userspace is allowed to use userspace fencing or long running compute
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workloads. This also means no implicit fencing for shared buffers in these
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cases.
|
2021-02-03 23:29:21 +08:00
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|
Recoverable Hardware Page Faults Implications
|
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|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Modern hardware supports recoverable page faults, which has a lot of
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implications for DMA fences.
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First, a pending page fault obviously holds up the work that's running on the
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accelerator and a memory allocation is usually required to resolve the fault.
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But memory allocations are not allowed to gate completion of DMA fences, which
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means any workload using recoverable page faults cannot use DMA fences for
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synchronization. Synchronization fences controlled by userspace must be used
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instead.
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On GPUs this poses a problem, because current desktop compositor protocols on
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Linux rely on DMA fences, which means without an entirely new userspace stack
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built on top of userspace fences, they cannot benefit from recoverable page
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faults. Specifically this means implicit synchronization will not be possible.
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The exception is when page faults are only used as migration hints and never to
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on-demand fill a memory request. For now this means recoverable page
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faults on GPUs are limited to pure compute workloads.
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Furthermore GPUs usually have shared resources between the 3D rendering and
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compute side, like compute units or command submission engines. If both a 3D
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job with a DMA fence and a compute workload using recoverable page faults are
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pending they could deadlock:
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- The 3D workload might need to wait for the compute job to finish and release
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hardware resources first.
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- The compute workload might be stuck in a page fault, because the memory
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|
allocation is waiting for the DMA fence of the 3D workload to complete.
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There are a few options to prevent this problem, one of which drivers need to
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|
ensure:
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|
- Compute workloads can always be preempted, even when a page fault is pending
|
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|
and not yet repaired. Not all hardware supports this.
|
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|
- DMA fence workloads and workloads which need page fault handling have
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|
independent hardware resources to guarantee forward progress. This could be
|
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|
achieved through e.g. through dedicated engines and minimal compute unit
|
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|
reservations for DMA fence workloads.
|
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|
- The reservation approach could be further refined by only reserving the
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|
hardware resources for DMA fence workloads when they are in-flight. This must
|
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|
cover the time from when the DMA fence is visible to other threads up to
|
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|
|
moment when fence is completed through dma_fence_signal().
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|
- As a last resort, if the hardware provides no useful reservation mechanics,
|
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|
all workloads must be flushed from the GPU when switching between jobs
|
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|
|
requiring DMA fences or jobs requiring page fault handling: This means all DMA
|
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|
|
fences must complete before a compute job with page fault handling can be
|
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|
|
inserted into the scheduler queue. And vice versa, before a DMA fence can be
|
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|
|
made visible anywhere in the system, all compute workloads must be preempted
|
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|
|
to guarantee all pending GPU page faults are flushed.
|
|
|
|
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|
|
- Only a fairly theoretical option would be to untangle these dependencies when
|
|
|
|
allocating memory to repair hardware page faults, either through separate
|
|
|
|
memory blocks or runtime tracking of the full dependency graph of all DMA
|
|
|
|
fences. This results very wide impact on the kernel, since resolving the page
|
|
|
|
on the CPU side can itself involve a page fault. It is much more feasible and
|
|
|
|
robust to limit the impact of handling hardware page faults to the specific
|
|
|
|
driver.
|
|
|
|
|
|
|
|
Note that workloads that run on independent hardware like copy engines or other
|
|
|
|
GPUs do not have any impact. This allows us to keep using DMA fences internally
|
|
|
|
in the kernel even for resolving hardware page faults, e.g. by using copy
|
|
|
|
engines to clear or copy memory needed to resolve the page fault.
|
|
|
|
|
|
|
|
In some ways this page fault problem is a special case of the `Infinite DMA
|
|
|
|
Fences` discussions: Infinite fences from compute workloads are allowed to
|
|
|
|
depend on DMA fences, but not the other way around. And not even the page fault
|
|
|
|
problem is new, because some other CPU thread in userspace might
|
|
|
|
hit a page fault which holds up a userspace fence - supporting page faults on
|
|
|
|
GPUs doesn't anything fundamentally new.
|