2021-01-21 15:16:59 +08:00
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# SPDX-License-Identifier: GPL-2.0
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config XILINX_VCU
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tristate "Xilinx VCU logicoreIP Init"
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2022-10-04 04:31:03 +08:00
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depends on HAS_IOMEM
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2021-01-21 15:16:59 +08:00
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select REGMAP_MMIO
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help
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Provides the driver to enable and disable the isolation between the
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processing system and programmable logic part by using the logicoreIP
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register set. This driver also configures the frequency based on the
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clock information from the logicoreIP register set.
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If you say yes here you get support for the logicoreIP.
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If unsure, say N.
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To compile this driver as a module, choose M here: the
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module will be called xlnx_vcu.
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2022-04-11 18:04:40 +08:00
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config COMMON_CLK_XLNX_CLKWZRD
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tristate "Xilinx Clocking Wizard"
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2022-10-04 04:31:03 +08:00
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depends on OF
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2022-10-04 04:26:08 +08:00
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depends on HAS_IOMEM
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2022-04-11 18:04:40 +08:00
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help
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Support for the Xilinx Clocking Wizard IP core clock generator.
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Adds support for clocking wizard and compatible.
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This driver supports the Xilinx clocking wizard programmable clock
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synthesizer. The number of output is configurable in the design.
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If unsure, say N.
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