2021-08-06 16:49:05 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2019-2021, Intel Corporation. */
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#ifndef _ICE_TC_LIB_H_
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#define _ICE_TC_LIB_H_
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#define ICE_TC_FLWR_FIELD_DST_MAC BIT(0)
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#define ICE_TC_FLWR_FIELD_SRC_MAC BIT(1)
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#define ICE_TC_FLWR_FIELD_VLAN BIT(2)
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#define ICE_TC_FLWR_FIELD_DEST_IPV4 BIT(3)
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#define ICE_TC_FLWR_FIELD_SRC_IPV4 BIT(4)
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#define ICE_TC_FLWR_FIELD_DEST_IPV6 BIT(5)
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#define ICE_TC_FLWR_FIELD_SRC_IPV6 BIT(6)
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#define ICE_TC_FLWR_FIELD_DEST_L4_PORT BIT(7)
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#define ICE_TC_FLWR_FIELD_SRC_L4_PORT BIT(8)
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#define ICE_TC_FLWR_FIELD_TENANT_ID BIT(9)
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#define ICE_TC_FLWR_FIELD_ENC_DEST_IPV4 BIT(10)
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#define ICE_TC_FLWR_FIELD_ENC_SRC_IPV4 BIT(11)
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#define ICE_TC_FLWR_FIELD_ENC_DEST_IPV6 BIT(12)
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#define ICE_TC_FLWR_FIELD_ENC_SRC_IPV6 BIT(13)
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#define ICE_TC_FLWR_FIELD_ENC_DEST_L4_PORT BIT(14)
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#define ICE_TC_FLWR_FIELD_ENC_SRC_L4_PORT BIT(15)
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#define ICE_TC_FLWR_FIELD_ENC_DST_MAC BIT(16)
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#define ICE_TC_FLWR_FIELD_ETH_TYPE_ID BIT(17)
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struct ice_tc_flower_action {
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u32 tc_class;
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enum ice_sw_fwd_act_type fltr_act;
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};
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struct ice_tc_vlan_hdr {
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__be16 vlan_id; /* Only last 12 bits valid */
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u16 vlan_prio; /* Only last 3 bits valid (valid values: 0..7) */
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};
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struct ice_tc_l2_hdr {
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u8 dst_mac[ETH_ALEN];
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u8 src_mac[ETH_ALEN];
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__be16 n_proto; /* Ethernet Protocol */
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};
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struct ice_tc_l3_hdr {
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u8 ip_proto; /* IPPROTO value */
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union {
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struct {
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struct in_addr dst_ip;
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struct in_addr src_ip;
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} v4;
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struct {
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struct in6_addr dst_ip6;
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struct in6_addr src_ip6;
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} v6;
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} ip;
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#define dst_ipv6 ip.v6.dst_ip6.s6_addr32
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#define dst_ipv6_addr ip.v6.dst_ip6.s6_addr
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#define src_ipv6 ip.v6.src_ip6.s6_addr32
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#define src_ipv6_addr ip.v6.src_ip6.s6_addr
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#define dst_ipv4 ip.v4.dst_ip.s_addr
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#define src_ipv4 ip.v4.src_ip.s_addr
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u8 tos;
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u8 ttl;
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};
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struct ice_tc_l4_hdr {
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__be16 dst_port;
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__be16 src_port;
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};
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struct ice_tc_flower_lyr_2_4_hdrs {
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/* L2 layer fields with their mask */
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struct ice_tc_l2_hdr l2_key;
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struct ice_tc_l2_hdr l2_mask;
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struct ice_tc_vlan_hdr vlan_hdr;
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/* L3 (IPv4[6]) layer fields with their mask */
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struct ice_tc_l3_hdr l3_key;
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struct ice_tc_l3_hdr l3_mask;
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/* L4 layer fields with their mask */
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struct ice_tc_l4_hdr l4_key;
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struct ice_tc_l4_hdr l4_mask;
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};
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enum ice_eswitch_fltr_direction {
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ICE_ESWITCH_FLTR_INGRESS,
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ICE_ESWITCH_FLTR_EGRESS,
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};
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struct ice_tc_flower_fltr {
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struct hlist_node tc_flower_node;
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/* cookie becomes filter_rule_id if rule is added successfully */
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unsigned long cookie;
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/* add_adv_rule returns information like recipe ID, rule_id. Store
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* those values since they are needed to remove advanced rule
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*/
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u16 rid;
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u16 rule_id;
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/* this could be queue/vsi_idx (sw handle)/queue_group, depending upon
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* destination type
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*/
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u16 dest_id;
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/* if dest_id is vsi_idx, then need to store destination VSI ptr */
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struct ice_vsi *dest_vsi;
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/* direction of fltr for eswitch use case */
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enum ice_eswitch_fltr_direction direction;
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/* Parsed TC flower configuration params */
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struct ice_tc_flower_lyr_2_4_hdrs outer_headers;
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struct ice_tc_flower_lyr_2_4_hdrs inner_headers;
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struct ice_vsi *src_vsi;
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__be32 tenant_id;
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u32 flags;
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struct ice_tc_flower_action action;
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/* cache ptr which is used wherever needed to communicate netlink
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* messages
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*/
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struct netlink_ext_ack *extack;
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};
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int
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ice_add_cls_flower(struct net_device *netdev, struct ice_vsi *vsi,
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struct flow_cls_offload *cls_flower);
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int
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ice_del_cls_flower(struct ice_vsi *vsi, struct flow_cls_offload *cls_flower);
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2021-08-06 16:49:06 +08:00
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void ice_replay_tc_fltrs(struct ice_pf *pf);
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2021-08-06 16:49:05 +08:00
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#endif /* _ICE_TC_LIB_H_ */
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