arm64: Add sysreg header generation scripting
The arm64 kernel requires some metadata for each system register it may
need to access. Currently we have:
* A SYS_<regname> definition which sorresponds to a sys_reg() macro.
This is used both to look up a sysreg by encoding (e.g. in KVM), and
also to generate code to access a sysreg where the assembler is
unaware of the specific sysreg encoding.
Where assemblers support the S3_<op1>_C<crn>_C<crm>_<op2> syntax for
system registers, we could use this rather than manually assembling
the instructions. However, we don't have consistent definitions for
these and we currently still need to handle toolchains that lack this
feature.
* A set of <regname>_<fieldname>_SHIFT and <regname>_<fieldname>_MASK
definitions, which can be used to extract fields from the register, or
to construct a register from a set of fields.
These do not follow the convention used by <linux/bitfield.h>, and the
masks are not shifted into place, preventing their use in FIELD_PREP()
and FIELD_GET(). We require the SHIFT definitions for inline assembly
(and WIDTH definitions would be helpful for UBFX/SBFX), so we cannot
only define a shifted MASK. Defining a SHIFT, WIDTH, shifted MASK and
unshifted MASK is tedious and error-prone and life is much easier when
they can be relied up to exist when writing code.
* A set of <regname>_<fieldname>_<valname> definitions for each
enumerated value a field may hold. These are used when identifying the
presence of features.
Atop of this, other code has to build up metadata at runtime (e.g. the
sets of RES0/RES1 bits in a register).
This patch adds scripting so that we can have an easier-to-manage
canonical representation of this metadata, from which we can generate
all the definitions necessary for various use-cases, e.g.
| #define REG_ID_AA64ISAR0_EL1 S3_0_C0_C6_0
| #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
| #define SYS_ID_AA64ISAR0_EL1_Op0 3
| #define SYS_ID_AA64ISAR0_EL1_Op1 0
| #define SYS_ID_AA64ISAR0_EL1_CRn 0
| #define SYS_ID_AA64ISAR0_EL1_CRm 6
| #define SYS_ID_AA64ISAR0_EL1_Op2 0
| #define ID_AA64ISAR0_EL1_RNDR GENMASK(63, 60)
| #define ID_AA64ISAR0_EL1_RNDR_MASK GENMASK(63, 60)
| #define ID_AA64ISAR0_EL1_RNDR_SHIFT 60
| #define ID_AA64ISAR0_EL1_RNDR_WIDTH 4
| #define ID_AA64ISAR0_EL1_RNDR_NI UL(0b0000)
| #define ID_AA64ISAR0_EL1_RNDR_IMP UL(0b0001)
The script requires that all bits in the register be specified and that
there be no overlapping fields. This helps the script spot errors in the
input but means that the few registers which change layout at runtime
depending on things like virtualisation settings will need some manual
handling. No actual register conversions are done here but a header for
the register data with some documention of the format is provided.
For cases where multiple registers share a layout (eg, when identical
controls are provided at multiple ELs) the register fields can be
defined once and referenced from the actual registers, currently we do
not generate actual defines for the individual registers.
At the moment this is only intended to express metadata from the
architecture, and does not handle policy imposed by the kernel, such as
values exposed to userspace or VMs. In future this could be extended to
express such information.
This script was mostly written by Mark Rutland but has been extended by
Mark Brown to improve validation of input and better integrate with the
kernel.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Co-Developed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220503170233.507788-9-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-04 01:02:29 +08:00
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# System register metadata
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# Each System register is described by a Sysreg block:
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# Sysreg <name> <op0> <op1> <crn> <crm> <op2>
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# <field>
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# ...
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# EndSysreg
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# Within a Sysreg block, each field can be described as one of:
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# Res0 <msb>[:<lsb>]
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# Res1 <msb>[:<lsb>]
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# Field <msb>[:<lsb>] <name>
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# Enum <msb>[:<lsb>] <name>
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# <enumval> <enumname>
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# ...
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# EndEnum
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# Alternatively if multiple registers share the same layout then
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# a SysregFields block can be used to describe the shared layout
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# SysregFields <fieldsname>
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# <field>
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# ...
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# EndSysregFields
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# and referenced from within the Sysreg:
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# Sysreg <name> <op0> <op1> <crn> <crm> <op2>
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# Fields <fieldsname>
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# EndSysreg
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# For ID registers we adopt a few conventions for translating the
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# language in the ARM into defines:
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#
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# NI - Not implemented
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# IMP - Implemented
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#
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# In general it is recommended that new enumeration items be named for the
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# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
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# item ACCDATA) though it may be more taseful to do something else.
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2022-12-01 01:16:28 +08:00
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Sysreg ID_PFR0_EL1 3 0 0 1 0
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Res0 63:32
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Enum 31:28 RAS
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0b0000 NI
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0b0001 RAS
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0b0010 RASv1p1
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EndEnum
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Enum 27:24 DIT
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 23:20 AMU
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0b0000 NI
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0b0001 AMUv1
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0b0010 AMUv1p1
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EndEnum
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Enum 19:16 CSV2
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0b0000 UNDISCLOSED
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0b0001 IMP
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0b0010 CSV2p1
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EndEnum
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Enum 15:12 State3
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 11:8 State2
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0b0000 NI
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0b0001 NO_CV
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0b0010 CV
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EndEnum
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Enum 7:4 State1
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0b0000 NI
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0b0001 THUMB
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0b0010 THUMB2
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EndEnum
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Enum 3:0 State0
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0b0000 NI
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0b0001 IMP
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EndEnum
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EndSysreg
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2022-12-01 01:16:16 +08:00
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Sysreg ID_MMFR0_EL1 3 0 0 1 4
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Res0 63:32
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Enum 31:28 InnerShr
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0b0000 NC
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0b0001 HW
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0b1111 IGNORED
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EndEnum
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Enum 27:24 FCSE
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 23:20 AuxReg
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0b0000 NI
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0b0001 ACTLR
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0b0010 AIFSR
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EndEnum
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Enum 19:16 TCM
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0b0000 NI
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0b0001 IMPDEF
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0b0010 TCM
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0b0011 TCM_DMA
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EndEnum
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Enum 15:12 ShareLvl
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0b0000 ONE
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0b0001 TWO
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EndEnum
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Enum 11:8 OuterShr
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0b0000 NC
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0b0001 HW
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0b1111 IGNORED
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EndEnum
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Enum 7:4 PMSA
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0b0000 NI
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0b0001 IMPDEF
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0b0010 PMSAv6
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0b0011 PMSAv7
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EndEnum
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Enum 3:0 VMSA
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0b0000 NI
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0b0001 IMPDEF
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0b0010 VMSAv6
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0b0011 VMSAv7
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0b0100 VMSAv7_PXN
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0b0101 VMSAv7_LONG
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EndEnum
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EndSysreg
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2022-12-01 01:16:17 +08:00
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Sysreg ID_MMFR1_EL1 3 0 0 1 5
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Res0 63:32
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Enum 31:28 BPred
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0b0000 NI
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0b0001 BP_SW_MANGED
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0b0010 BP_ASID_AWARE
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0b0011 BP_NOSNOOP
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0b0100 BP_INVISIBLE
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EndEnum
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Enum 27:24 L1TstCln
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0b0000 NI
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0b0001 NOINVALIDATE
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0b0010 INVALIDATE
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EndEnum
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Enum 23:20 L1Uni
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0b0000 NI
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0b0001 INVALIDATE
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0b0010 CLEAN_AND_INVALIDATE
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EndEnum
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Enum 19:16 L1Hvd
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0b0000 NI
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0b0001 INVALIDATE_ISIDE_ONLY
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0b0010 INVALIDATE
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0b0011 CLEAN_AND_INVALIDATE
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EndEnum
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Enum 15:12 L1UniSW
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0b0000 NI
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0b0001 CLEAN
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0b0010 CLEAN_AND_INVALIDATE
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0b0011 INVALIDATE
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EndEnum
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Enum 11:8 L1HvdSW
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0b0000 NI
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0b0001 CLEAN_AND_INVALIDATE
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0b0010 INVALIDATE_DSIDE_ONLY
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0b0011 INVALIDATE
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EndEnum
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Enum 7:4 L1UniVA
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0b0000 NI
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0b0001 CLEAN_AND_INVALIDATE
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0b0010 INVALIDATE_BP
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EndEnum
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Enum 3:0 L1HvdVA
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0b0000 NI
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0b0001 CLEAN_AND_INVALIDATE
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0b0010 INVALIDATE_BP
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EndEnum
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EndSysreg
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2022-12-01 01:16:18 +08:00
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Sysreg ID_MMFR2_EL1 3 0 0 1 6
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Res0 63:32
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Enum 31:28 HWAccFlg
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 27:24 WFIStall
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 23:20 MemBarr
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0b0000 NI
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0b0001 DSB_ONLY
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0b0010 IMP
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EndEnum
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Enum 19:16 UniTLB
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0b0000 NI
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0b0001 BY_VA
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0b0010 BY_MATCH_ASID
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0b0011 BY_ALL_ASID
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0b0100 OTHER_TLBS
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0b0101 BROADCAST
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0b0110 BY_IPA
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EndEnum
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Enum 15:12 HvdTLB
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0b0000 NI
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EndEnum
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Enum 11:8 L1HvdRng
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 7:4 L1HvdBG
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 3:0 L1HvdFG
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0b0000 NI
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0b0001 IMP
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EndEnum
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EndSysreg
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2022-12-01 01:16:19 +08:00
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Sysreg ID_MMFR3_EL1 3 0 0 1 7
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Res0 63:32
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Enum 31:28 Supersec
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0b0000 IMP
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0b1111 NI
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EndEnum
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Enum 27:24 CMemSz
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0b0000 4GB
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0b0001 64GB
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0b0010 1TB
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EndEnum
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Enum 23:20 CohWalk
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 19:16 PAN
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0b0000 NI
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0b0001 PAN
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0b0010 PAN2
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EndEnum
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Enum 15:12 MaintBcst
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0b0000 NI
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0b0001 NO_TLB
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0b0010 ALL
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EndEnum
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Enum 11:8 BPMaint
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0b0000 NI
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0b0001 ALL
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0b0010 BY_VA
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EndEnum
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Enum 7:4 CMaintSW
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 3:0 CMaintVA
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0b0000 NI
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0b0001 IMP
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EndEnum
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EndSysreg
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2022-12-01 01:16:21 +08:00
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Sysreg ID_ISAR0_EL1 3 0 0 2 0
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Res0 63:28
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Enum 27:24 Divide
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0b0000 NI
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0b0001 xDIV_T32
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0b0010 xDIV_A32
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EndEnum
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Enum 23:20 Debug
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 19:16 Coproc
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0b0000 NI
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0b0001 MRC
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0b0010 MRC2
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0b0011 MRRC
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0b0100 MRRC2
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EndEnum
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Enum 15:12 CmpBranch
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 11:8 BitField
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 7:4 BitCount
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 3:0 Swap
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0b0000 NI
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0b0001 IMP
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EndEnum
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EndSysreg
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2022-12-01 01:16:22 +08:00
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Sysreg ID_ISAR1_EL1 3 0 0 2 1
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Res0 63:32
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Enum 31:28 Jazelle
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 27:24 Interwork
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|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 BX
|
|
|
|
|
0b0010 BLX
|
|
|
|
|
0b0011 A32_BX
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 Immediate
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 IfThen
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 Extend
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 SXTB
|
|
|
|
|
0b0010 SXTB16
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 Except_AR
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 Except
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 Endian
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-12-01 01:16:23 +08:00
|
|
|
Sysreg ID_ISAR2_EL1 3 0 0 2 2
|
|
|
|
|
Res0 63:32
|
|
|
|
|
Enum 31:28 Reversal
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 REV
|
|
|
|
|
0b0010 RBIT
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 27:24 PSR_AR
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 MultU
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 UMULL
|
|
|
|
|
0b0010 UMAAL
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 MultS
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 SMULL
|
|
|
|
|
0b0010 SMLABB
|
|
|
|
|
0b0011 SMLAD
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 Mult
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 MLA
|
|
|
|
|
0b0010 MLS
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 MultiAccessInt
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 RESTARTABLE
|
|
|
|
|
0b0010 CONTINUABLE
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 MemHint
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 PLD
|
|
|
|
|
0b0010 PLD2
|
|
|
|
|
0b0011 PLI
|
|
|
|
|
0b0100 PLDW
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 LoadStore
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 DOUBLE
|
|
|
|
|
0b0010 ACQUIRE
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-12-01 01:16:24 +08:00
|
|
|
Sysreg ID_ISAR3_EL1 3 0 0 2 3
|
|
|
|
|
Res0 63:32
|
|
|
|
|
Enum 31:28 T32EE
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 27:24 TrueNOP
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 T32Copy
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 TabBranch
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 SynchPrim
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 EXCLUSIVE
|
|
|
|
|
0b0010 DOUBLE
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 SVC
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 SIMD
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 SSAT
|
|
|
|
|
0b0011 PKHBT
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 Saturate
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-12-01 01:16:25 +08:00
|
|
|
Sysreg ID_ISAR4_EL1 3 0 0 2 4
|
|
|
|
|
Res0 63:32
|
|
|
|
|
Enum 31:28 SWP_frac
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 27:24 PSR_M
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 SynchPrim_frac
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0011 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 Barrier
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 SMC
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 Writeback
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 WithShifts
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 LSL3
|
|
|
|
|
0b0011 LS
|
|
|
|
|
0b0100 REG
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 Unpriv
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 REG_BYTE
|
|
|
|
|
0b0010 SIGNED_HALFWORD
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-12-01 01:16:26 +08:00
|
|
|
Sysreg ID_ISAR5_EL1 3 0 0 2 5
|
|
|
|
|
Res0 63:32
|
|
|
|
|
Enum 31:28 VCMA
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 27:24 RDM
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 23:20
|
|
|
|
|
Enum 19:16 CRC32
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 SHA2
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 SHA1
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 AES
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 VMULL
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 SEVL
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-12-01 01:16:27 +08:00
|
|
|
Sysreg ID_ISAR6_EL1 3 0 0 2 7
|
|
|
|
|
Res0 63:28
|
|
|
|
|
Enum 27:24 I8MM
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 BF16
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 SPECRES
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 SB
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 FHM
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 DP
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 JSCVT
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-12-01 01:16:20 +08:00
|
|
|
Sysreg ID_MMFR4_EL1 3 0 0 2 6
|
|
|
|
|
Res0 63:32
|
|
|
|
|
Enum 31:28 EVT
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 NO_TLBIS
|
|
|
|
|
0b0010 TLBIS
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 27:24 CCIDX
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 LSM
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 HPDS
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 AA32HPD
|
|
|
|
|
0b0010 HPDS2
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 CnP
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 XNX
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 AC2
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 SpecSEI
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-09-06 06:54:21 +08:00
|
|
|
Sysreg ID_AA64PFR0_EL1 3 0 0 4 0
|
|
|
|
|
Enum 63:60 CSV3
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 59:56 CSV2
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 CSV2_2
|
|
|
|
|
0b0011 CSV2_3
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 55:52 RME
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 51:48 DIT
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 47:44 AMU
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 V1P1
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 43:40 MPAM
|
|
|
|
|
0b0000 0
|
|
|
|
|
0b0001 1
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 39:36 SEL2
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 35:32 SVE
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 31:28 RAS
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 V1P1
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 27:24 GIC
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 V4P1
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 AdvSIMD
|
|
|
|
|
0b0000 IMP
|
|
|
|
|
0b0001 FP16
|
|
|
|
|
0b1111 NI
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 FP
|
|
|
|
|
0b0000 IMP
|
|
|
|
|
0b0001 FP16
|
|
|
|
|
0b1111 NI
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 EL3
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 AARCH32
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 EL2
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 AARCH32
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 EL1
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 AARCH32
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 EL0
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 AARCH32
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-09-06 06:54:22 +08:00
|
|
|
Sysreg ID_AA64PFR1_EL1 3 0 0 4 1
|
|
|
|
|
Res0 63:40
|
|
|
|
|
Enum 39:36 NMI
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 35:32 CSV2_frac
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 CSV2_1p1
|
|
|
|
|
0b0010 CSV2_1p2
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 31:28 RNDR_trap
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 27:24 SME
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 23:20
|
|
|
|
|
Enum 19:16 MPAM_frac
|
|
|
|
|
0b0000 MINOR_0
|
|
|
|
|
0b0001 MINOR_1
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 RAS_frac
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 RASv1p1
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 MTE
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 MTE2
|
|
|
|
|
0b0011 MTE3
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 SSBS
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 SSBS2
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 BT
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-07-05 01:03:02 +08:00
|
|
|
Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4
|
|
|
|
|
Res0 63:60
|
|
|
|
|
Enum 59:56 F64MM
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 55:52 F32MM
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 51:48
|
|
|
|
|
Enum 47:44 I8MM
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 43:40 SM4
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 39:36
|
|
|
|
|
Enum 35:32 SHA3
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 31:24
|
|
|
|
|
Enum 23:20 BF16
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 EBF16
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 BitPerm
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 15:8
|
|
|
|
|
Enum 7:4 AES
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 PMULL128
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 SVEver
|
|
|
|
|
0b0000 IMP
|
|
|
|
|
0b0001 SVE2
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-07-05 01:03:01 +08:00
|
|
|
Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5
|
|
|
|
|
Enum 63 FA64
|
|
|
|
|
0b0 NI
|
|
|
|
|
0b1 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 62:60
|
2022-09-06 06:53:59 +08:00
|
|
|
Enum 59:56 SMEver
|
|
|
|
|
0b0000 IMP
|
|
|
|
|
EndEnum
|
2022-07-05 01:03:01 +08:00
|
|
|
Enum 55:52 I16I64
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b1111 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 51:49
|
|
|
|
|
Enum 48 F64F64
|
|
|
|
|
0b0 NI
|
|
|
|
|
0b1 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 47:40
|
|
|
|
|
Enum 39:36 I8I32
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b1111 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 35 F16F32
|
|
|
|
|
0b0 NI
|
|
|
|
|
0b1 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 34 B16F32
|
|
|
|
|
0b0 NI
|
|
|
|
|
0b1 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 33
|
|
|
|
|
Enum 32 F32F32
|
|
|
|
|
0b0 NI
|
|
|
|
|
0b1 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 31:0
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-09-11 00:33:52 +08:00
|
|
|
Sysreg ID_AA64DFR0_EL1 3 0 0 5 0
|
|
|
|
|
Enum 63:60 HPMN0
|
|
|
|
|
0b0000 UNPREDICTABLE
|
|
|
|
|
0b0001 DEF
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 59:56
|
|
|
|
|
Enum 55:52 BRBE
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 BRBE_V1P1
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 51:48 MTPMU
|
|
|
|
|
0b0000 NI_IMPDEF
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b1111 NI
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 47:44 TraceBuffer
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 43:40 TraceFilt
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 39:36 DoubleLock
|
|
|
|
|
0b0000 IMP
|
|
|
|
|
0b1111 NI
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 35:32 PMSVer
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 V1P1
|
|
|
|
|
0b0011 V1P2
|
|
|
|
|
0b0100 V1P3
|
|
|
|
|
EndEnum
|
|
|
|
|
Field 31:28 CTX_CMPs
|
|
|
|
|
Res0 27:24
|
|
|
|
|
Field 23:20 WRPs
|
|
|
|
|
Res0 19:16
|
|
|
|
|
Field 15:12 BRPs
|
|
|
|
|
Enum 11:8 PMUVer
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0100 V3P1
|
|
|
|
|
0b0101 V3P4
|
|
|
|
|
0b0110 V3P5
|
|
|
|
|
0b0111 V3P7
|
|
|
|
|
0b1000 V3P8
|
|
|
|
|
0b1111 IMP_DEF
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 TraceVer
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 DebugVer
|
|
|
|
|
0b0110 IMP
|
|
|
|
|
0b0111 VHE
|
|
|
|
|
0b1000 V8P2
|
|
|
|
|
0b1001 V8P4
|
|
|
|
|
0b1010 V8P8
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-09-11 00:33:53 +08:00
|
|
|
Sysreg ID_AA64DFR1_EL1 3 0 0 5 1
|
|
|
|
|
Res0 63:0
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-09-11 00:33:54 +08:00
|
|
|
Sysreg ID_AA64AFR0_EL1 3 0 0 5 4
|
|
|
|
|
Res0 63:32
|
|
|
|
|
Field 31:28 IMPDEF7
|
|
|
|
|
Field 27:24 IMPDEF6
|
|
|
|
|
Field 23:20 IMPDEF5
|
|
|
|
|
Field 19:16 IMPDEF4
|
|
|
|
|
Field 15:12 IMPDEF3
|
|
|
|
|
Field 11:8 IMPDEF2
|
|
|
|
|
Field 7:4 IMPDEF1
|
|
|
|
|
Field 3:0 IMPDEF0
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
|
|
|
|
Sysreg ID_AA64AFR1_EL1 3 0 0 5 5
|
|
|
|
|
Res0 63:0
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-04 01:02:31 +08:00
|
|
|
Sysreg ID_AA64ISAR0_EL1 3 0 0 6 0
|
|
|
|
|
Enum 63:60 RNDR
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 59:56 TLB
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 OS
|
|
|
|
|
0b0010 RANGE
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 55:52 TS
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 FLAGM
|
|
|
|
|
0b0010 FLAGM2
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 51:48 FHM
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 47:44 DP
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 43:40 SM4
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 39:36 SM3
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 35:32 SHA3
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 31:28 RDM
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 27:24 TME
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 ATOMIC
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0010 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 CRC32
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 SHA2
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 SHA256
|
|
|
|
|
0b0010 SHA512
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 SHA1
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 AES
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 AES
|
|
|
|
|
0b0010 PMULL
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 3:0
|
|
|
|
|
EndSysreg
|
2022-05-04 01:02:32 +08:00
|
|
|
|
2022-07-05 01:02:54 +08:00
|
|
|
Sysreg ID_AA64ISAR1_EL1 3 0 0 6 1
|
|
|
|
|
Enum 63:60 LS64
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 LS64
|
|
|
|
|
0b0010 LS64_V
|
|
|
|
|
0b0011 LS64_ACCDATA
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 59:56 XS
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 55:52 I8MM
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 51:48 DGH
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 47:44 BF16
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 EBF16
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 43:40 SPECRES
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 39:36 SB
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 35:32 FRINTTS
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 31:28 GPI
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 27:24 GPA
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 LRCPC
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 LRCPC2
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 FCMA
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 JSCVT
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 API
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 PAuth
|
|
|
|
|
0b0010 EPAC
|
|
|
|
|
0b0011 PAuth2
|
|
|
|
|
0b0100 FPAC
|
|
|
|
|
0b0101 FPACCOMBINE
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 APA
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 PAuth
|
|
|
|
|
0b0010 EPAC
|
|
|
|
|
0b0011 PAuth2
|
|
|
|
|
0b0100 FPAC
|
|
|
|
|
0b0101 FPACCOMBINE
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 DPB
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 DPB2
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
2022-07-05 01:02:55 +08:00
|
|
|
|
|
|
|
|
Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2
|
|
|
|
|
Res0 63:28
|
|
|
|
|
Enum 27:24 PAC_frac
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 BC
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 MOPS
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 APA3
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 PAuth
|
|
|
|
|
0b0010 EPAC
|
|
|
|
|
0b0011 PAuth2
|
|
|
|
|
0b0100 FPAC
|
|
|
|
|
0b0101 FPACCOMBINE
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 GPA3
|
|
|
|
|
0b0000 NI
|
2022-07-05 01:02:54 +08:00
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
2022-07-05 01:02:55 +08:00
|
|
|
Enum 7:4 RPRES
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 WFxT
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0010 IMP
|
|
|
|
|
EndEnum
|
2022-07-05 01:02:54 +08:00
|
|
|
EndSysreg
|
|
|
|
|
|
2022-09-06 06:54:18 +08:00
|
|
|
Sysreg ID_AA64MMFR0_EL1 3 0 0 7 0
|
|
|
|
|
Enum 63:60 ECV
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 CNTPOFF
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 59:56 FGT
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 55:48
|
|
|
|
|
Enum 47:44 EXS
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 43:40 TGRAN4_2
|
|
|
|
|
0b0000 TGRAN4
|
|
|
|
|
0b0001 NI
|
|
|
|
|
0b0010 IMP
|
|
|
|
|
0b0011 52_BIT
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 39:36 TGRAN64_2
|
|
|
|
|
0b0000 TGRAN64
|
|
|
|
|
0b0001 NI
|
|
|
|
|
0b0010 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 35:32 TGRAN16_2
|
|
|
|
|
0b0000 TGRAN16
|
|
|
|
|
0b0001 NI
|
|
|
|
|
0b0010 IMP
|
|
|
|
|
0b0011 52_BIT
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 31:28 TGRAN4
|
|
|
|
|
0b0000 IMP
|
|
|
|
|
0b0001 52_BIT
|
|
|
|
|
0b1111 NI
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 27:24 TGRAN64
|
|
|
|
|
0b0000 IMP
|
|
|
|
|
0b1111 NI
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 TGRAN16
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 52_BIT
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 BIGENDEL0
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 SNSMEM
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 BIGEND
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 ASIDBITS
|
|
|
|
|
0b0000 8
|
|
|
|
|
0b0010 16
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 PARANGE
|
|
|
|
|
0b0000 32
|
|
|
|
|
0b0001 36
|
|
|
|
|
0b0010 40
|
|
|
|
|
0b0011 42
|
|
|
|
|
0b0100 44
|
|
|
|
|
0b0101 48
|
|
|
|
|
0b0110 52
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-09-06 06:54:19 +08:00
|
|
|
Sysreg ID_AA64MMFR1_EL1 3 0 0 7 1
|
|
|
|
|
Enum 63:60 ECBHB
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 59:56 CMOW
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 55:52 TIDCP1
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 51:48 nTLBPA
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 47:44 AFP
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 43:40 HCX
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 39:36 ETS
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 35:32 TWED
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 31:28 XNX
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 27:24 SpecSEI
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 PAN
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 PAN2
|
|
|
|
|
0b0011 PAN3
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 LO
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 HPDS
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 HPDS2
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 VH
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 VMIDBits
|
|
|
|
|
0b0000 8
|
|
|
|
|
0b0010 16
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 HAFDBS
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 AF
|
|
|
|
|
0b0010 DBM
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-09-06 06:54:20 +08:00
|
|
|
Sysreg ID_AA64MMFR2_EL1 3 0 0 7 2
|
|
|
|
|
Enum 63:60 E0PD
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 59:56 EVT
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 TTLBxS
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 55:52 BBM
|
|
|
|
|
0b0000 0
|
|
|
|
|
0b0001 1
|
|
|
|
|
0b0010 2
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 51:48 TTL
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Res0 47:44
|
|
|
|
|
Enum 43:40 FWB
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 39:36 IDS
|
|
|
|
|
0b0000 0x0
|
|
|
|
|
0b0001 0x18
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 35:32 AT
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 31:28 ST
|
|
|
|
|
0b0000 39
|
|
|
|
|
0b0001 48_47
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 27:24 NV
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
0b0010 NV2
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 23:20 CCIDX
|
|
|
|
|
0b0000 32
|
|
|
|
|
0b0001 64
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 19:16 VARange
|
|
|
|
|
0b0000 48
|
|
|
|
|
0b0001 52
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 15:12 IESB
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 11:8 LSM
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 7:4 UAO
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 3:0 CnP
|
|
|
|
|
0b0000 NI
|
|
|
|
|
0b0001 IMP
|
|
|
|
|
EndEnum
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-04 01:02:33 +08:00
|
|
|
Sysreg SCTLR_EL1 3 0 1 0 0
|
|
|
|
|
Field 63 TIDCP
|
2022-10-06 02:16:42 +08:00
|
|
|
Field 62 SPINTMASK
|
2022-05-04 01:02:33 +08:00
|
|
|
Field 61 NMI
|
|
|
|
|
Field 60 EnTP2
|
|
|
|
|
Res0 59:58
|
|
|
|
|
Field 57 EPAN
|
|
|
|
|
Field 56 EnALS
|
|
|
|
|
Field 55 EnAS0
|
|
|
|
|
Field 54 EnASR
|
|
|
|
|
Field 53 TME
|
|
|
|
|
Field 52 TME0
|
|
|
|
|
Field 51 TMT
|
|
|
|
|
Field 50 TMT0
|
|
|
|
|
Field 49:46 TWEDEL
|
|
|
|
|
Field 45 TWEDEn
|
|
|
|
|
Field 44 DSSBS
|
|
|
|
|
Field 43 ATA
|
|
|
|
|
Field 42 ATA0
|
|
|
|
|
Enum 41:40 TCF
|
|
|
|
|
0b00 NONE
|
|
|
|
|
0b01 SYNC
|
|
|
|
|
0b10 ASYNC
|
|
|
|
|
0b11 ASYMM
|
|
|
|
|
EndEnum
|
|
|
|
|
Enum 39:38 TCF0
|
|
|
|
|
0b00 NONE
|
|
|
|
|
0b01 SYNC
|
|
|
|
|
0b10 ASYNC
|
|
|
|
|
0b11 ASYMM
|
|
|
|
|
EndEnum
|
|
|
|
|
Field 37 ITFSB
|
|
|
|
|
Field 36 BT1
|
|
|
|
|
Field 35 BT0
|
|
|
|
|
Res0 34
|
|
|
|
|
Field 33 MSCEn
|
|
|
|
|
Field 32 CMOW
|
|
|
|
|
Field 31 EnIA
|
|
|
|
|
Field 30 EnIB
|
|
|
|
|
Field 29 LSMAOE
|
|
|
|
|
Field 28 nTLSMD
|
|
|
|
|
Field 27 EnDA
|
|
|
|
|
Field 26 UCI
|
|
|
|
|
Field 25 EE
|
|
|
|
|
Field 24 E0E
|
|
|
|
|
Field 23 SPAN
|
|
|
|
|
Field 22 EIS
|
|
|
|
|
Field 21 IESB
|
|
|
|
|
Field 20 TSCXT
|
|
|
|
|
Field 19 WXN
|
|
|
|
|
Field 18 nTWE
|
|
|
|
|
Res0 17
|
|
|
|
|
Field 16 nTWI
|
|
|
|
|
Field 15 UCT
|
|
|
|
|
Field 14 DZE
|
|
|
|
|
Field 13 EnDB
|
|
|
|
|
Field 12 I
|
|
|
|
|
Field 11 EOS
|
|
|
|
|
Field 10 EnRCTX
|
|
|
|
|
Field 9 UMA
|
|
|
|
|
Field 8 SED
|
|
|
|
|
Field 7 ITD
|
|
|
|
|
Field 6 nAA
|
|
|
|
|
Field 5 CP15BEN
|
|
|
|
|
Field 4 SA0
|
|
|
|
|
Field 3 SA
|
|
|
|
|
Field 2 C
|
|
|
|
|
Field 1 A
|
|
|
|
|
Field 0 M
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-21 00:16:35 +08:00
|
|
|
SysregFields CPACR_ELx
|
|
|
|
|
Res0 63:29
|
|
|
|
|
Field 28 TTA
|
|
|
|
|
Res0 27:26
|
|
|
|
|
Field 25:24 SMEN
|
|
|
|
|
Res0 23:22
|
|
|
|
|
Field 21:20 FPEN
|
|
|
|
|
Res0 19:18
|
|
|
|
|
Field 17:16 ZEN
|
|
|
|
|
Res0 15:0
|
|
|
|
|
EndSysregFields
|
|
|
|
|
|
|
|
|
|
Sysreg CPACR_EL1 3 0 1 0 2
|
|
|
|
|
Fields CPACR_ELx
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-11 00:12:06 +08:00
|
|
|
Sysreg SMPRI_EL1 3 0 1 2 4
|
|
|
|
|
Res0 63:4
|
|
|
|
|
Field 3:0 PRIORITY
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-11 00:12:08 +08:00
|
|
|
SysregFields ZCR_ELx
|
|
|
|
|
Res0 63:9
|
|
|
|
|
Raz 8:4
|
|
|
|
|
Field 3:0 LEN
|
|
|
|
|
EndSysregFields
|
|
|
|
|
|
|
|
|
|
Sysreg ZCR_EL1 3 0 1 2 0
|
|
|
|
|
Fields ZCR_ELx
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-11 00:12:03 +08:00
|
|
|
SysregFields SMCR_ELx
|
|
|
|
|
Res0 63:32
|
|
|
|
|
Field 31 FA64
|
|
|
|
|
Res0 30:9
|
|
|
|
|
Raz 8:4
|
|
|
|
|
Field 3:0 LEN
|
|
|
|
|
EndSysregFields
|
|
|
|
|
|
|
|
|
|
Sysreg SMCR_EL1 3 0 1 2 6
|
|
|
|
|
Fields SMCR_ELx
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-09-06 06:54:25 +08:00
|
|
|
Sysreg ALLINT 3 0 4 3 0
|
|
|
|
|
Res0 63:14
|
|
|
|
|
Field 13 ALLINT
|
|
|
|
|
Res0 12:0
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-21 00:16:38 +08:00
|
|
|
Sysreg FAR_EL1 3 0 6 0 0
|
|
|
|
|
Field 63:0 ADDR
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-21 00:16:34 +08:00
|
|
|
SysregFields CONTEXTIDR_ELx
|
|
|
|
|
Res0 63:32
|
|
|
|
|
Field 31:0 PROCID
|
|
|
|
|
EndSysregFields
|
|
|
|
|
|
|
|
|
|
Sysreg CONTEXTIDR_EL1 3 0 13 0 1
|
|
|
|
|
Fields CONTEXTIDR_ELx
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-09-06 06:54:23 +08:00
|
|
|
Sysreg TPIDR_EL1 3 0 13 0 4
|
|
|
|
|
Field 63:0 ThreadID
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-09-06 06:54:24 +08:00
|
|
|
Sysreg SCXTNUM_EL1 3 0 13 0 7
|
|
|
|
|
Field 63:0 SoftwareContextNumber
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-21 00:16:33 +08:00
|
|
|
Sysreg CLIDR_EL1 3 1 0 0 1
|
|
|
|
|
Res0 63:47
|
|
|
|
|
Field 46:33 Ttypen
|
|
|
|
|
Field 32:30 ICB
|
|
|
|
|
Field 29:27 LoUU
|
|
|
|
|
Field 26:24 LoC
|
|
|
|
|
Field 23:21 LoUIS
|
|
|
|
|
Field 20:18 Ctype7
|
|
|
|
|
Field 17:15 Ctype6
|
|
|
|
|
Field 14:12 Ctype5
|
|
|
|
|
Field 11:9 Ctype4
|
|
|
|
|
Field 8:6 Ctype3
|
|
|
|
|
Field 5:3 Ctype2
|
|
|
|
|
Field 2:0 Ctype1
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-07-05 01:02:53 +08:00
|
|
|
Sysreg GMID_EL1 3 1 0 0 4
|
|
|
|
|
Res0 63:4
|
|
|
|
|
Field 3:0 BS
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-11 00:12:04 +08:00
|
|
|
Sysreg SMIDR_EL1 3 1 0 0 6
|
|
|
|
|
Res0 63:32
|
|
|
|
|
Field 31:24 IMPLEMENTER
|
|
|
|
|
Field 23:16 REVISION
|
|
|
|
|
Field 15 SMPS
|
|
|
|
|
Res0 14:12
|
|
|
|
|
Field 11:0 AFFINITY
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EndSysreg
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2022-05-21 00:16:36 +08:00
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Sysreg CSSELR_EL1 3 2 0 0 0
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Res0 63:5
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Field 4 TnD
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Field 3:1 Level
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Field 0 InD
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EndSysreg
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2022-07-05 01:02:51 +08:00
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Sysreg CTR_EL0 3 3 0 0 1
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Res0 63:38
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Field 37:32 TminLine
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Res1 31
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Res0 30
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Field 29 DIC
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Field 28 IDC
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Field 27:24 CWG
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Field 23:20 ERG
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Field 19:16 DminLine
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Enum 15:14 L1Ip
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0b00 VPIPT
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# This is named as AIVIVT in the ARM but documented as reserved
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0b01 RESERVED
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0b10 VIPT
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0b11 PIPT
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EndEnum
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Res0 13:4
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Field 3:0 IminLine
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EndSysreg
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2022-07-05 01:02:52 +08:00
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Sysreg DCZID_EL0 3 3 0 0 7
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Res0 63:5
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Field 4 DZP
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Field 3:0 BS
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EndSysreg
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|
2022-05-11 00:12:07 +08:00
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Sysreg SVCR 3 3 4 2 2
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Res0 63:2
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Field 1 ZA
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Field 0 SM
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EndSysreg
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|
2022-05-11 00:12:08 +08:00
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|
Sysreg ZCR_EL2 3 4 1 2 0
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Fields ZCR_ELx
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EndSysreg
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|
2022-09-06 06:54:17 +08:00
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|
Sysreg HCRX_EL2 3 4 1 2 2
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|
Res0 63:12
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|
Field 11 MSCEn
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Field 10 MCE2
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Field 9 CMOW
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Field 8 VFNMI
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Field 7 VINMI
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Field 6 TALLINT
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Field 5 SMPME
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Field 4 FGTnXS
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Field 3 FnXS
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Field 2 EnASR
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Field 1 EnALS
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Field 0 EnAS0
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EndSysreg
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|
2022-05-11 00:12:05 +08:00
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|
|
Sysreg SMPRIMAP_EL2 3 4 1 2 5
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Field 63:60 P15
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Field 59:56 P14
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Field 55:52 P13
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Field 51:48 P12
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Field 47:44 P11
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Field 43:40 P10
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Field 39:36 F9
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Field 35:32 P8
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Field 31:28 P7
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Field 27:24 P6
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Field 23:20 P5
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Field 19:16 P4
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Field 15:12 P3
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Field 11:8 P2
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Field 7:4 P1
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Field 3:0 P0
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EndSysreg
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|
|
2022-05-11 00:12:03 +08:00
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|
|
Sysreg SMCR_EL2 3 4 1 2 6
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|
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|
|
Fields SMCR_ELx
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EndSysreg
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|
|
2022-05-21 00:16:37 +08:00
|
|
|
Sysreg DACR32_EL2 3 4 3 0 0
|
|
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|
|
Res0 63:32
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|
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|
|
Field 31:30 D15
|
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|
|
Field 29:28 D14
|
|
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|
|
Field 27:26 D13
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|
Field 25:24 D12
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|
Field 23:22 D11
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Field 21:20 D10
|
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|
|
Field 19:18 D9
|
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|
|
Field 17:16 D8
|
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|
Field 15:14 D7
|
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|
Field 13:12 D6
|
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|
Field 11:10 D5
|
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|
Field 9:8 D4
|
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|
|
Field 7:6 D3
|
|
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|
|
Field 5:4 D2
|
|
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|
Field 3:2 D1
|
|
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|
|
Field 1:0 D0
|
|
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|
|
EndSysreg
|
|
|
|
|
|
2022-05-21 00:16:38 +08:00
|
|
|
Sysreg FAR_EL2 3 4 6 0 0
|
|
|
|
|
Field 63:0 ADDR
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-21 00:16:34 +08:00
|
|
|
Sysreg CONTEXTIDR_EL2 3 4 13 0 1
|
|
|
|
|
Fields CONTEXTIDR_ELx
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-21 00:16:35 +08:00
|
|
|
Sysreg CPACR_EL12 3 5 1 0 2
|
|
|
|
|
Fields CPACR_ELx
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-11 00:12:08 +08:00
|
|
|
Sysreg ZCR_EL12 3 5 1 2 0
|
|
|
|
|
Fields ZCR_ELx
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-11 00:12:03 +08:00
|
|
|
Sysreg SMCR_EL12 3 5 1 2 6
|
|
|
|
|
Fields SMCR_ELx
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-21 00:16:38 +08:00
|
|
|
Sysreg FAR_EL12 3 5 6 0 0
|
|
|
|
|
Field 63:0 ADDR
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-21 00:16:34 +08:00
|
|
|
Sysreg CONTEXTIDR_EL12 3 5 13 0 1
|
|
|
|
|
Fields CONTEXTIDR_ELx
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-05-04 01:02:32 +08:00
|
|
|
SysregFields TTBRx_EL1
|
|
|
|
|
Field 63:48 ASID
|
|
|
|
|
Field 47:1 BADDR
|
|
|
|
|
Field 0 CnP
|
|
|
|
|
EndSysregFields
|
|
|
|
|
|
|
|
|
|
Sysreg TTBR0_EL1 3 0 2 0 0
|
|
|
|
|
Fields TTBRx_EL1
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
|
|
|
|
Sysreg TTBR1_EL1 3 0 2 0 1
|
|
|
|
|
Fields TTBRx_EL1
|
|
|
|
|
EndSysreg
|
2022-07-05 01:02:56 +08:00
|
|
|
|
|
|
|
|
Sysreg LORSA_EL1 3 0 10 4 0
|
|
|
|
|
Res0 63:52
|
|
|
|
|
Field 51:16 SA
|
|
|
|
|
Res0 15:1
|
|
|
|
|
Field 0 Valid
|
|
|
|
|
EndSysreg
|
|
|
|
|
|
2022-07-05 01:02:57 +08:00
|
|
|
Sysreg LOREA_EL1 3 0 10 4 1
|
|
|
|
|
Res0 63:52
|
|
|
|
|
Field 51:48 EA_51_48
|
|
|
|
|
Field 47:16 EA_47_16
|
|
|
|
|
Res0 15:0
|
|
|
|
|
EndSysreg
|
2022-07-05 01:02:58 +08:00
|
|
|
|
|
|
|
|
Sysreg LORN_EL1 3 0 10 4 2
|
|
|
|
|
Res0 63:8
|
|
|
|
|
Field 7:0 Num
|
|
|
|
|
EndSysreg
|
2022-07-05 01:02:59 +08:00
|
|
|
|
|
|
|
|
Sysreg LORC_EL1 3 0 10 4 3
|
|
|
|
|
Res0 63:10
|
|
|
|
|
Field 9:2 DS
|
|
|
|
|
Res0 1
|
|
|
|
|
Field 0 EN
|
|
|
|
|
EndSysreg
|
2022-07-05 01:03:00 +08:00
|
|
|
|
|
|
|
|
Sysreg LORID_EL1 3 0 10 4 7
|
|
|
|
|
Res0 63:24
|
|
|
|
|
Field 23:16 LD
|
|
|
|
|
Res0 15:8
|
|
|
|
|
Field 7:0 LR
|
|
|
|
|
EndSysreg
|
