2013-07-20 00:59:32 +08:00
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "msm_gpu.h"
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#include "msm_gem.h"
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2013-11-17 01:56:06 +08:00
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#include "msm_mmu.h"
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2016-03-16 03:35:08 +08:00
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#include "msm_fence.h"
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2013-07-20 00:59:32 +08:00
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/*
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* Power Management:
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*/
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2015-06-04 22:26:37 +08:00
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#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
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2013-07-20 00:59:32 +08:00
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#include <mach/board.h>
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2013-11-15 22:03:15 +08:00
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static void bs_init(struct msm_gpu *gpu)
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2013-07-20 00:59:32 +08:00
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{
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2013-11-15 22:03:15 +08:00
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if (gpu->bus_scale_table) {
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gpu->bsc = msm_bus_scale_register_client(gpu->bus_scale_table);
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2013-07-20 00:59:32 +08:00
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DBG("bus scale client: %08x", gpu->bsc);
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}
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}
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static void bs_fini(struct msm_gpu *gpu)
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{
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if (gpu->bsc) {
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msm_bus_scale_unregister_client(gpu->bsc);
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gpu->bsc = 0;
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}
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}
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static void bs_set(struct msm_gpu *gpu, int idx)
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{
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if (gpu->bsc) {
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DBG("set bus scaling: %d", idx);
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msm_bus_scale_client_update_request(gpu->bsc, idx);
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}
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}
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#else
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2013-11-15 22:03:15 +08:00
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static void bs_init(struct msm_gpu *gpu) {}
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2013-07-20 00:59:32 +08:00
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static void bs_fini(struct msm_gpu *gpu) {}
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static void bs_set(struct msm_gpu *gpu, int idx) {}
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#endif
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static int enable_pwrrail(struct msm_gpu *gpu)
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{
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struct drm_device *dev = gpu->dev;
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int ret = 0;
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if (gpu->gpu_reg) {
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ret = regulator_enable(gpu->gpu_reg);
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if (ret) {
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dev_err(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
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return ret;
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}
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}
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if (gpu->gpu_cx) {
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ret = regulator_enable(gpu->gpu_cx);
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if (ret) {
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dev_err(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
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return ret;
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}
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}
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return 0;
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}
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static int disable_pwrrail(struct msm_gpu *gpu)
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{
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if (gpu->gpu_cx)
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regulator_disable(gpu->gpu_cx);
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if (gpu->gpu_reg)
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regulator_disable(gpu->gpu_reg);
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return 0;
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}
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static int enable_clk(struct msm_gpu *gpu)
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{
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int i;
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2017-03-08 01:02:56 +08:00
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if (gpu->core_clk && gpu->fast_rate)
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clk_set_rate(gpu->core_clk, gpu->fast_rate);
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2013-07-20 00:59:32 +08:00
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2016-11-29 03:28:33 +08:00
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/* Set the RBBM timer rate to 19.2Mhz */
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2017-03-08 01:02:56 +08:00
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if (gpu->rbbmtimer_clk)
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clk_set_rate(gpu->rbbmtimer_clk, 19200000);
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2016-11-29 03:28:33 +08:00
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2017-03-08 01:02:56 +08:00
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for (i = gpu->nr_clocks - 1; i >= 0; i--)
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2016-11-29 03:28:31 +08:00
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if (gpu->grp_clks[i])
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clk_prepare(gpu->grp_clks[i]);
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2013-07-20 00:59:32 +08:00
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2017-03-08 01:02:56 +08:00
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for (i = gpu->nr_clocks - 1; i >= 0; i--)
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2013-07-20 00:59:32 +08:00
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if (gpu->grp_clks[i])
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clk_enable(gpu->grp_clks[i]);
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return 0;
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}
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static int disable_clk(struct msm_gpu *gpu)
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{
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int i;
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2017-03-08 01:02:56 +08:00
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for (i = gpu->nr_clocks - 1; i >= 0; i--)
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2016-11-29 03:28:31 +08:00
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if (gpu->grp_clks[i])
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2013-07-20 00:59:32 +08:00
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clk_disable(gpu->grp_clks[i]);
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2017-03-08 01:02:56 +08:00
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for (i = gpu->nr_clocks - 1; i >= 0; i--)
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2013-07-20 00:59:32 +08:00
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if (gpu->grp_clks[i])
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clk_unprepare(gpu->grp_clks[i]);
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2017-03-08 01:02:54 +08:00
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/*
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* Set the clock to a deliberately low rate. On older targets the clock
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* speed had to be non zero to avoid problems. On newer targets this
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* will be rounded down to zero anyway so it all works out.
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*/
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2017-03-08 01:02:56 +08:00
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if (gpu->core_clk)
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clk_set_rate(gpu->core_clk, 27000000);
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2016-11-29 03:28:31 +08:00
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2017-03-08 01:02:56 +08:00
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if (gpu->rbbmtimer_clk)
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clk_set_rate(gpu->rbbmtimer_clk, 0);
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2016-11-29 03:28:33 +08:00
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2013-07-20 00:59:32 +08:00
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return 0;
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}
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static int enable_axi(struct msm_gpu *gpu)
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{
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if (gpu->ebi1_clk)
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clk_prepare_enable(gpu->ebi1_clk);
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if (gpu->bus_freq)
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bs_set(gpu, gpu->bus_freq);
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return 0;
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}
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static int disable_axi(struct msm_gpu *gpu)
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{
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if (gpu->ebi1_clk)
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clk_disable_unprepare(gpu->ebi1_clk);
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if (gpu->bus_freq)
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bs_set(gpu, 0);
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return 0;
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}
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int msm_gpu_pm_resume(struct msm_gpu *gpu)
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{
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int ret;
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2017-02-11 04:36:33 +08:00
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DBG("%s", gpu->name);
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2013-07-20 00:59:32 +08:00
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ret = enable_pwrrail(gpu);
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if (ret)
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return ret;
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ret = enable_clk(gpu);
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if (ret)
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return ret;
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ret = enable_axi(gpu);
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if (ret)
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return ret;
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2017-02-11 04:36:33 +08:00
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gpu->needs_hw_init = true;
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2013-07-20 00:59:32 +08:00
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return 0;
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}
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int msm_gpu_pm_suspend(struct msm_gpu *gpu)
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{
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int ret;
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2017-02-11 04:36:33 +08:00
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DBG("%s", gpu->name);
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2013-07-20 00:59:32 +08:00
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ret = disable_axi(gpu);
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if (ret)
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return ret;
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ret = disable_clk(gpu);
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if (ret)
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return ret;
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ret = disable_pwrrail(gpu);
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if (ret)
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return ret;
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return 0;
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}
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2017-02-11 04:36:33 +08:00
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int msm_gpu_hw_init(struct msm_gpu *gpu)
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2014-01-12 05:25:08 +08:00
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{
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2017-02-11 04:36:33 +08:00
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int ret;
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2014-01-12 05:25:08 +08:00
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2017-06-13 21:15:36 +08:00
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WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex));
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2017-02-11 04:36:33 +08:00
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if (!gpu->needs_hw_init)
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return 0;
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2014-01-12 05:25:08 +08:00
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2017-02-11 04:36:33 +08:00
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disable_irq(gpu->irq);
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ret = gpu->funcs->hw_init(gpu);
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if (!ret)
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gpu->needs_hw_init = false;
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enable_irq(gpu->irq);
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2014-01-12 05:25:08 +08:00
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2017-02-11 04:36:33 +08:00
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return ret;
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2014-01-12 05:25:08 +08:00
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}
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2013-08-25 02:20:38 +08:00
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/*
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* Hangcheck detection for locked gpu:
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*/
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2016-03-16 06:26:28 +08:00
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static void retire_submits(struct msm_gpu *gpu);
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2015-06-08 01:46:04 +08:00
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2013-08-25 02:20:38 +08:00
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static void recover_worker(struct work_struct *work)
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{
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struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
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struct drm_device *dev = gpu->dev;
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2016-05-03 22:10:15 +08:00
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struct msm_gem_submit *submit;
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2016-03-16 06:26:28 +08:00
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uint32_t fence = gpu->funcs->last_fence(gpu);
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2013-08-25 02:20:38 +08:00
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2016-03-16 06:26:28 +08:00
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msm_update_fence(gpu->fctx, fence + 1);
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2013-08-25 02:20:38 +08:00
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mutex_lock(&dev->struct_mutex);
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2015-06-08 01:46:04 +08:00
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2016-05-03 22:10:15 +08:00
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dev_err(dev->dev, "%s: hangcheck recover!\n", gpu->name);
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list_for_each_entry(submit, &gpu->submit_list, node) {
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if (submit->fence->seqno == (fence + 1)) {
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struct task_struct *task;
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rcu_read_lock();
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task = pid_task(submit->pid, PIDTYPE_PID);
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if (task) {
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dev_err(dev->dev, "%s: offending task: %s\n",
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gpu->name, task->comm);
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}
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rcu_read_unlock();
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break;
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}
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}
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if (msm_gpu_active(gpu)) {
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2015-06-08 01:46:04 +08:00
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/* retire completed submits, plus the one that hung: */
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2016-03-16 06:26:28 +08:00
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retire_submits(gpu);
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2015-06-08 01:46:04 +08:00
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2017-02-11 04:36:33 +08:00
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pm_runtime_get_sync(&gpu->pdev->dev);
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2014-01-12 05:25:08 +08:00
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gpu->funcs->recover(gpu);
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2017-02-11 04:36:33 +08:00
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pm_runtime_put_sync(&gpu->pdev->dev);
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2015-06-08 01:46:04 +08:00
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/* replay the remaining submits after the one that hung: */
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list_for_each_entry(submit, &gpu->submit_list, node) {
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gpu->funcs->submit(gpu, submit, NULL);
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}
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2014-01-12 05:25:08 +08:00
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}
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2016-05-03 22:10:15 +08:00
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2013-08-25 02:20:38 +08:00
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mutex_unlock(&dev->struct_mutex);
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msm_gpu_retire(gpu);
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}
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static void hangcheck_timer_reset(struct msm_gpu *gpu)
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{
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DBG("%s", gpu->name);
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mod_timer(&gpu->hangcheck_timer,
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round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
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}
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static void hangcheck_handler(unsigned long data)
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{
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struct msm_gpu *gpu = (struct msm_gpu *)data;
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2013-09-12 05:14:30 +08:00
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struct drm_device *dev = gpu->dev;
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struct msm_drm_private *priv = dev->dev_private;
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2013-08-25 02:20:38 +08:00
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uint32_t fence = gpu->funcs->last_fence(gpu);
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if (fence != gpu->hangcheck_fence) {
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/* some progress has been made.. ya! */
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gpu->hangcheck_fence = fence;
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2016-03-16 05:22:13 +08:00
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} else if (fence < gpu->fctx->last_fence) {
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2013-08-25 02:20:38 +08:00
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/* no progress and not done.. hung! */
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gpu->hangcheck_fence = fence;
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2013-09-03 19:12:03 +08:00
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dev_err(dev->dev, "%s: hangcheck detected gpu lockup!\n",
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gpu->name);
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dev_err(dev->dev, "%s: completed fence: %u\n",
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gpu->name, fence);
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dev_err(dev->dev, "%s: submitted fence: %u\n",
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2016-03-16 05:22:13 +08:00
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gpu->name, gpu->fctx->last_fence);
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2013-08-25 02:20:38 +08:00
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queue_work(priv->wq, &gpu->recover_work);
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}
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/* if still more pending work, reset the hangcheck timer: */
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2016-03-16 05:22:13 +08:00
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if (gpu->fctx->last_fence > gpu->hangcheck_fence)
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2013-08-25 02:20:38 +08:00
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hangcheck_timer_reset(gpu);
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2013-09-12 05:14:30 +08:00
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/* workaround for missing irq: */
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queue_work(priv->wq, &gpu->retire_work);
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2013-08-25 02:20:38 +08:00
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}
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2014-05-31 02:49:43 +08:00
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/*
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* Performance Counters:
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*/
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/* called under perf_lock */
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static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
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{
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uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
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int i, n = min(ncntrs, gpu->num_perfcntrs);
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/* read current values: */
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for (i = 0; i < gpu->num_perfcntrs; i++)
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current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
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/* update cntrs: */
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for (i = 0; i < n; i++)
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|
|
cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
|
|
|
|
|
|
|
|
/* save current values: */
|
|
|
|
for (i = 0; i < gpu->num_perfcntrs; i++)
|
|
|
|
gpu->last_cntrs[i] = current_cntrs[i];
|
|
|
|
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void update_sw_cntrs(struct msm_gpu *gpu)
|
|
|
|
{
|
|
|
|
ktime_t time;
|
|
|
|
uint32_t elapsed;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&gpu->perf_lock, flags);
|
|
|
|
if (!gpu->perfcntr_active)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
time = ktime_get();
|
|
|
|
elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
|
|
|
|
|
|
|
|
gpu->totaltime += elapsed;
|
|
|
|
if (gpu->last_sample.active)
|
|
|
|
gpu->activetime += elapsed;
|
|
|
|
|
|
|
|
gpu->last_sample.active = msm_gpu_active(gpu);
|
|
|
|
gpu->last_sample.time = time;
|
|
|
|
|
|
|
|
out:
|
|
|
|
spin_unlock_irqrestore(&gpu->perf_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
2017-02-11 04:36:33 +08:00
|
|
|
pm_runtime_get_sync(&gpu->pdev->dev);
|
|
|
|
|
2014-05-31 02:49:43 +08:00
|
|
|
spin_lock_irqsave(&gpu->perf_lock, flags);
|
|
|
|
/* we could dynamically enable/disable perfcntr registers too.. */
|
|
|
|
gpu->last_sample.active = msm_gpu_active(gpu);
|
|
|
|
gpu->last_sample.time = ktime_get();
|
|
|
|
gpu->activetime = gpu->totaltime = 0;
|
|
|
|
gpu->perfcntr_active = true;
|
|
|
|
update_hw_cntrs(gpu, 0, NULL);
|
|
|
|
spin_unlock_irqrestore(&gpu->perf_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
|
|
|
|
{
|
|
|
|
gpu->perfcntr_active = false;
|
2017-02-11 04:36:33 +08:00
|
|
|
pm_runtime_put_sync(&gpu->pdev->dev);
|
2014-05-31 02:49:43 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* returns -errno or # of cntrs sampled */
|
|
|
|
int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
|
|
|
|
uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&gpu->perf_lock, flags);
|
|
|
|
|
|
|
|
if (!gpu->perfcntr_active) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
*activetime = gpu->activetime;
|
|
|
|
*totaltime = gpu->totaltime;
|
|
|
|
|
|
|
|
gpu->activetime = gpu->totaltime = 0;
|
|
|
|
|
|
|
|
ret = update_hw_cntrs(gpu, ncntrs, cntrs);
|
|
|
|
|
|
|
|
out:
|
|
|
|
spin_unlock_irqrestore(&gpu->perf_lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-07-20 00:59:32 +08:00
|
|
|
/*
|
|
|
|
* Cmdstream submission/retirement:
|
|
|
|
*/
|
|
|
|
|
2016-03-17 04:07:38 +08:00
|
|
|
static void retire_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < submit->nr_bos; i++) {
|
|
|
|
struct msm_gem_object *msm_obj = submit->bos[i].obj;
|
|
|
|
/* move to inactive: */
|
|
|
|
msm_gem_move_to_inactive(&msm_obj->base);
|
2017-06-13 23:07:08 +08:00
|
|
|
msm_gem_put_iova(&msm_obj->base, gpu->aspace);
|
2016-03-17 04:07:38 +08:00
|
|
|
drm_gem_object_unreference(&msm_obj->base);
|
|
|
|
}
|
|
|
|
|
2017-02-11 04:36:33 +08:00
|
|
|
pm_runtime_mark_last_busy(&gpu->pdev->dev);
|
|
|
|
pm_runtime_put_autosuspend(&gpu->pdev->dev);
|
2016-05-03 21:50:26 +08:00
|
|
|
msm_gem_submit_free(submit);
|
2016-03-17 04:07:38 +08:00
|
|
|
}
|
|
|
|
|
2016-03-16 06:26:28 +08:00
|
|
|
static void retire_submits(struct msm_gpu *gpu)
|
2015-06-08 01:46:04 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = gpu->dev;
|
|
|
|
|
|
|
|
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
|
|
|
|
|
|
|
|
while (!list_empty(&gpu->submit_list)) {
|
|
|
|
struct msm_gem_submit *submit;
|
|
|
|
|
|
|
|
submit = list_first_entry(&gpu->submit_list,
|
|
|
|
struct msm_gem_submit, node);
|
|
|
|
|
2016-10-25 20:00:45 +08:00
|
|
|
if (dma_fence_is_signaled(submit->fence)) {
|
2016-03-17 04:07:38 +08:00
|
|
|
retire_submit(gpu, submit);
|
2015-06-08 01:46:04 +08:00
|
|
|
} else {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-07-20 00:59:32 +08:00
|
|
|
static void retire_worker(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
|
|
|
|
struct drm_device *dev = gpu->dev;
|
|
|
|
uint32_t fence = gpu->funcs->last_fence(gpu);
|
|
|
|
|
2016-03-16 05:22:13 +08:00
|
|
|
msm_update_fence(gpu->fctx, fence);
|
2013-09-15 02:01:55 +08:00
|
|
|
|
2013-07-20 00:59:32 +08:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
2016-03-16 06:26:28 +08:00
|
|
|
retire_submits(gpu);
|
2013-07-20 00:59:32 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* call from irq handler to schedule work to retire bo's */
|
|
|
|
void msm_gpu_retire(struct msm_gpu *gpu)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = gpu->dev->dev_private;
|
|
|
|
queue_work(priv->wq, &gpu->retire_work);
|
2014-05-31 02:49:43 +08:00
|
|
|
update_sw_cntrs(gpu);
|
2013-07-20 00:59:32 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* add bo's to gpu's ring, and kick gpu: */
|
2016-06-17 04:37:38 +08:00
|
|
|
void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
|
2013-07-20 00:59:32 +08:00
|
|
|
struct msm_file_private *ctx)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = gpu->dev;
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
2016-06-17 04:37:38 +08:00
|
|
|
int i;
|
2013-07-20 00:59:32 +08:00
|
|
|
|
2015-06-08 01:46:04 +08:00
|
|
|
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
|
|
|
|
|
2017-02-11 04:36:33 +08:00
|
|
|
pm_runtime_get_sync(&gpu->pdev->dev);
|
|
|
|
|
|
|
|
msm_gpu_hw_init(gpu);
|
2014-01-12 05:25:08 +08:00
|
|
|
|
2015-06-08 01:46:04 +08:00
|
|
|
list_add_tail(&submit->node, &gpu->submit_list);
|
|
|
|
|
2014-05-31 02:47:38 +08:00
|
|
|
msm_rd_dump_submit(submit);
|
|
|
|
|
2014-05-31 02:49:43 +08:00
|
|
|
update_sw_cntrs(gpu);
|
|
|
|
|
2013-07-20 00:59:32 +08:00
|
|
|
for (i = 0; i < submit->nr_bos; i++) {
|
|
|
|
struct msm_gem_object *msm_obj = submit->bos[i].obj;
|
2016-11-12 01:06:46 +08:00
|
|
|
uint64_t iova;
|
2013-07-20 00:59:32 +08:00
|
|
|
|
|
|
|
/* can't happen yet.. but when we add 2d support we'll have
|
|
|
|
* to deal w/ cross-ring synchronization:
|
|
|
|
*/
|
|
|
|
WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
|
|
|
|
|
2016-03-17 04:07:38 +08:00
|
|
|
/* submit takes a reference to the bo and iova until retired: */
|
|
|
|
drm_gem_object_reference(&msm_obj->base);
|
2017-06-14 06:52:54 +08:00
|
|
|
msm_gem_get_iova(&msm_obj->base,
|
2017-06-13 23:07:08 +08:00
|
|
|
submit->gpu->aspace, &iova);
|
2013-07-20 00:59:32 +08:00
|
|
|
|
2013-09-02 01:25:09 +08:00
|
|
|
if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
|
|
|
|
msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
|
2016-03-16 06:26:28 +08:00
|
|
|
else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
|
|
|
|
msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
|
2013-07-20 00:59:32 +08:00
|
|
|
}
|
2015-06-08 01:46:04 +08:00
|
|
|
|
2016-05-03 21:46:49 +08:00
|
|
|
gpu->funcs->submit(gpu, submit, ctx);
|
2015-06-08 01:46:04 +08:00
|
|
|
priv->lastctx = ctx;
|
|
|
|
|
2013-08-25 02:20:38 +08:00
|
|
|
hangcheck_timer_reset(gpu);
|
2013-07-20 00:59:32 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Init/Cleanup:
|
|
|
|
*/
|
|
|
|
|
|
|
|
static irqreturn_t irq_handler(int irq, void *data)
|
|
|
|
{
|
|
|
|
struct msm_gpu *gpu = data;
|
|
|
|
return gpu->funcs->irq(gpu);
|
|
|
|
}
|
|
|
|
|
2017-03-08 01:02:56 +08:00
|
|
|
static struct clk *get_clock(struct device *dev, const char *name)
|
|
|
|
{
|
|
|
|
struct clk *clk = devm_clk_get(dev, name);
|
|
|
|
|
|
|
|
return IS_ERR(clk) ? NULL : clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct property *prop;
|
|
|
|
const char *name;
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
gpu->nr_clocks = of_property_count_strings(dev->of_node, "clock-names");
|
|
|
|
if (gpu->nr_clocks < 1) {
|
|
|
|
gpu->nr_clocks = 0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
gpu->grp_clks = devm_kcalloc(dev, sizeof(struct clk *), gpu->nr_clocks,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!gpu->grp_clks)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
|
|
|
|
gpu->grp_clks[i] = get_clock(dev, name);
|
|
|
|
|
|
|
|
/* Remember the key clocks that we need to control later */
|
2017-05-03 22:43:14 +08:00
|
|
|
if (!strcmp(name, "core") || !strcmp(name, "core_clk"))
|
2017-03-08 01:02:56 +08:00
|
|
|
gpu->core_clk = gpu->grp_clks[i];
|
2017-05-03 22:43:14 +08:00
|
|
|
else if (!strcmp(name, "rbbmtimer") || !strcmp(name, "rbbmtimer_clk"))
|
2017-03-08 01:02:56 +08:00
|
|
|
gpu->rbbmtimer_clk = gpu->grp_clks[i];
|
|
|
|
|
|
|
|
++i;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2013-07-20 00:59:32 +08:00
|
|
|
|
2017-07-28 00:42:39 +08:00
|
|
|
static struct msm_gem_address_space *
|
|
|
|
msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev,
|
|
|
|
uint64_t va_start, uint64_t va_end)
|
|
|
|
{
|
|
|
|
struct iommu_domain *iommu;
|
|
|
|
struct msm_gem_address_space *aspace;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup IOMMU.. eventually we will (I think) do this once per context
|
|
|
|
* and have separate page tables per context. For now, to keep things
|
|
|
|
* simple and to get something working, just use a single address space:
|
|
|
|
*/
|
|
|
|
iommu = iommu_domain_alloc(&platform_bus_type);
|
|
|
|
if (!iommu)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
iommu->geometry.aperture_start = va_start;
|
|
|
|
iommu->geometry.aperture_end = va_end;
|
|
|
|
|
|
|
|
dev_info(gpu->dev->dev, "%s: using IOMMU\n", gpu->name);
|
|
|
|
|
|
|
|
aspace = msm_gem_address_space_create(&pdev->dev, iommu, "gpu");
|
|
|
|
if (IS_ERR(aspace)) {
|
|
|
|
dev_err(gpu->dev->dev, "failed to init iommu: %ld\n",
|
|
|
|
PTR_ERR(aspace));
|
|
|
|
iommu_domain_free(iommu);
|
|
|
|
return ERR_CAST(aspace);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0);
|
|
|
|
if (ret) {
|
|
|
|
msm_gem_address_space_put(aspace);
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
return aspace;
|
|
|
|
}
|
|
|
|
|
2013-07-20 00:59:32 +08:00
|
|
|
int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|
|
|
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
|
2017-05-09 04:35:03 +08:00
|
|
|
const char *name, struct msm_gpu_config *config)
|
2013-07-20 00:59:32 +08:00
|
|
|
{
|
2017-03-08 01:02:56 +08:00
|
|
|
int ret;
|
2013-07-20 00:59:32 +08:00
|
|
|
|
2014-05-31 02:49:43 +08:00
|
|
|
if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
|
|
|
|
gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
|
|
|
|
|
2013-07-20 00:59:32 +08:00
|
|
|
gpu->dev = drm;
|
|
|
|
gpu->funcs = funcs;
|
|
|
|
gpu->name = name;
|
2016-03-16 05:22:13 +08:00
|
|
|
gpu->fctx = msm_fence_context_alloc(drm, name);
|
|
|
|
if (IS_ERR(gpu->fctx)) {
|
|
|
|
ret = PTR_ERR(gpu->fctx);
|
|
|
|
gpu->fctx = NULL;
|
|
|
|
goto fail;
|
|
|
|
}
|
2013-07-20 00:59:32 +08:00
|
|
|
|
|
|
|
INIT_LIST_HEAD(&gpu->active_list);
|
|
|
|
INIT_WORK(&gpu->retire_work, retire_worker);
|
2013-08-25 02:20:38 +08:00
|
|
|
INIT_WORK(&gpu->recover_work, recover_worker);
|
|
|
|
|
2015-06-08 01:46:04 +08:00
|
|
|
INIT_LIST_HEAD(&gpu->submit_list);
|
|
|
|
|
2013-08-25 02:20:38 +08:00
|
|
|
setup_timer(&gpu->hangcheck_timer, hangcheck_handler,
|
|
|
|
(unsigned long)gpu);
|
2013-07-20 00:59:32 +08:00
|
|
|
|
2014-05-31 02:49:43 +08:00
|
|
|
spin_lock_init(&gpu->perf_lock);
|
|
|
|
|
2013-07-20 00:59:32 +08:00
|
|
|
|
|
|
|
/* Map registers: */
|
2017-05-09 04:35:03 +08:00
|
|
|
gpu->mmio = msm_ioremap(pdev, config->ioname, name);
|
2013-07-20 00:59:32 +08:00
|
|
|
if (IS_ERR(gpu->mmio)) {
|
|
|
|
ret = PTR_ERR(gpu->mmio);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get Interrupt: */
|
2017-05-09 04:35:03 +08:00
|
|
|
gpu->irq = platform_get_irq_byname(pdev, config->irqname);
|
2013-07-20 00:59:32 +08:00
|
|
|
if (gpu->irq < 0) {
|
|
|
|
ret = gpu->irq;
|
|
|
|
dev_err(drm->dev, "failed to get irq: %d\n", ret);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
|
|
|
|
IRQF_TRIGGER_HIGH, gpu->name, gpu);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
2017-03-08 01:02:56 +08:00
|
|
|
ret = get_clocks(pdev, gpu);
|
|
|
|
if (ret)
|
|
|
|
goto fail;
|
2013-07-20 00:59:32 +08:00
|
|
|
|
2017-01-31 00:30:58 +08:00
|
|
|
gpu->ebi1_clk = msm_clk_get(pdev, "bus");
|
2013-07-20 00:59:32 +08:00
|
|
|
DBG("ebi1_clk: %p", gpu->ebi1_clk);
|
|
|
|
if (IS_ERR(gpu->ebi1_clk))
|
|
|
|
gpu->ebi1_clk = NULL;
|
|
|
|
|
|
|
|
/* Acquire regulators: */
|
|
|
|
gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
|
|
|
|
DBG("gpu_reg: %p", gpu->gpu_reg);
|
|
|
|
if (IS_ERR(gpu->gpu_reg))
|
|
|
|
gpu->gpu_reg = NULL;
|
|
|
|
|
|
|
|
gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
|
|
|
|
DBG("gpu_cx: %p", gpu->gpu_cx);
|
|
|
|
if (IS_ERR(gpu->gpu_cx))
|
|
|
|
gpu->gpu_cx = NULL;
|
|
|
|
|
2017-07-28 00:42:39 +08:00
|
|
|
gpu->pdev = pdev;
|
|
|
|
platform_set_drvdata(pdev, gpu);
|
|
|
|
|
|
|
|
bs_init(gpu);
|
2015-09-15 20:41:46 +08:00
|
|
|
|
2017-07-28 00:42:39 +08:00
|
|
|
gpu->aspace = msm_gpu_create_address_space(gpu, pdev,
|
|
|
|
config->va_start, config->va_end);
|
|
|
|
|
|
|
|
if (gpu->aspace == NULL)
|
2013-11-17 01:56:06 +08:00
|
|
|
dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
|
2017-07-28 00:42:39 +08:00
|
|
|
else if (IS_ERR(gpu->aspace)) {
|
|
|
|
ret = PTR_ERR(gpu->aspace);
|
|
|
|
goto fail;
|
2013-07-20 00:59:32 +08:00
|
|
|
}
|
2014-07-11 23:59:22 +08:00
|
|
|
|
2013-07-20 00:59:32 +08:00
|
|
|
/* Create ringbuffer: */
|
2017-05-09 04:35:03 +08:00
|
|
|
gpu->rb = msm_ringbuffer_new(gpu, config->ringsz);
|
2013-07-20 00:59:32 +08:00
|
|
|
if (IS_ERR(gpu->rb)) {
|
|
|
|
ret = PTR_ERR(gpu->rb);
|
|
|
|
gpu->rb = NULL;
|
|
|
|
dev_err(drm->dev, "could not create ringbuffer: %d\n", ret);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
fail:
|
2017-07-28 00:42:39 +08:00
|
|
|
platform_set_drvdata(pdev, NULL);
|
2013-07-20 00:59:32 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void msm_gpu_cleanup(struct msm_gpu *gpu)
|
|
|
|
{
|
|
|
|
DBG("%s", gpu->name);
|
|
|
|
|
|
|
|
WARN_ON(!list_empty(&gpu->active_list));
|
|
|
|
|
|
|
|
bs_fini(gpu);
|
|
|
|
|
|
|
|
if (gpu->rb) {
|
|
|
|
if (gpu->rb_iova)
|
2017-06-13 23:07:08 +08:00
|
|
|
msm_gem_put_iova(gpu->rb->bo, gpu->aspace);
|
2013-07-20 00:59:32 +08:00
|
|
|
msm_ringbuffer_destroy(gpu->rb);
|
|
|
|
}
|
2017-07-28 00:42:39 +08:00
|
|
|
if (gpu->aspace) {
|
|
|
|
gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu,
|
|
|
|
NULL, 0);
|
|
|
|
msm_gem_address_space_put(gpu->aspace);
|
|
|
|
}
|
2013-07-20 00:59:32 +08:00
|
|
|
}
|