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linux/drivers/soc/mediatek/mt8167-pm-domains.h

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soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
#define __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
#include "mtk-pm-domains.h"
#include <dt-bindings/power/mt8167-power.h>
#define MT8167_PWR_STATUS_MFG_2D BIT(24)
#define MT8167_PWR_STATUS_MFG_ASYNC BIT(25)
/*
* MT8167 power domain support
*/
static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
[MT8167_POWER_DOMAIN_MM] = {
soc: mediatek: pm-domains: Add a power domain names for mt8167 Add the power domains names for the mt8167 SoC. Fixes: 207f13b419a6 ("soc: mediatek: pm-domains: Add support for mt8167") Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Link: https://lore.kernel.org/r/20210225175000.824661-4-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-02-26 01:50:00 +08:00
.name = "mm",
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sta_mask = PWR_STATUS_DISP,
.ctl_offs = SPM_DIS_PWR_CON,
soc: mediatek: pm-domains: Move power status offset to power domain data MT8195 has more than 32 power domains so it needs two set of pwr_sta and pwr_sta2nd registers, so move the register offset from soc data into power domain data. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-5-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:03 +08:00
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
MT8167_TOP_AXI_PROT_EN_MCU_MM),
},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8167_POWER_DOMAIN_VDEC] = {
soc: mediatek: pm-domains: Add a power domain names for mt8167 Add the power domains names for the mt8167 SoC. Fixes: 207f13b419a6 ("soc: mediatek: pm-domains: Add support for mt8167") Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Link: https://lore.kernel.org/r/20210225175000.824661-4-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-02-26 01:50:00 +08:00
.name = "vdec",
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sta_mask = PWR_STATUS_VDEC,
.ctl_offs = SPM_VDE_PWR_CON,
soc: mediatek: pm-domains: Move power status offset to power domain data MT8195 has more than 32 power domains so it needs two set of pwr_sta and pwr_sta2nd registers, so move the register offset from soc data into power domain data. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-5-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:03 +08:00
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8167_POWER_DOMAIN_ISP] = {
soc: mediatek: pm-domains: Add a power domain names for mt8167 Add the power domains names for the mt8167 SoC. Fixes: 207f13b419a6 ("soc: mediatek: pm-domains: Add support for mt8167") Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Link: https://lore.kernel.org/r/20210225175000.824661-4-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-02-26 01:50:00 +08:00
.name = "isp",
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sta_mask = PWR_STATUS_ISP,
.ctl_offs = SPM_ISP_PWR_CON,
soc: mediatek: pm-domains: Move power status offset to power domain data MT8195 has more than 32 power domains so it needs two set of pwr_sta and pwr_sta2nd registers, so move the register offset from soc data into power domain data. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-5-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:03 +08:00
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8167_POWER_DOMAIN_MFG_ASYNC] = {
soc: mediatek: pm-domains: Add a power domain names for mt8167 Add the power domains names for the mt8167 SoC. Fixes: 207f13b419a6 ("soc: mediatek: pm-domains: Add support for mt8167") Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Link: https://lore.kernel.org/r/20210225175000.824661-4-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-02-26 01:50:00 +08:00
.name = "mfg_async",
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
soc: mediatek: pm-domains: Move power status offset to power domain data MT8195 has more than 32 power domains so it needs two set of pwr_sta and pwr_sta2nd registers, so move the register offset from soc data into power domain data. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-5-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:03 +08:00
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
.bp_infracfg = {
BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
MT8167_TOP_AXI_PROT_EN_MFG_EMI),
},
},
[MT8167_POWER_DOMAIN_MFG_2D] = {
soc: mediatek: pm-domains: Add a power domain names for mt8167 Add the power domains names for the mt8167 SoC. Fixes: 207f13b419a6 ("soc: mediatek: pm-domains: Add support for mt8167") Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Link: https://lore.kernel.org/r/20210225175000.824661-4-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-02-26 01:50:00 +08:00
.name = "mfg_2d",
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sta_mask = MT8167_PWR_STATUS_MFG_2D,
.ctl_offs = SPM_MFG_2D_PWR_CON,
soc: mediatek: pm-domains: Move power status offset to power domain data MT8195 has more than 32 power domains so it needs two set of pwr_sta and pwr_sta2nd registers, so move the register offset from soc data into power domain data. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-5-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:03 +08:00
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
},
[MT8167_POWER_DOMAIN_MFG] = {
soc: mediatek: pm-domains: Add a power domain names for mt8167 Add the power domains names for the mt8167 SoC. Fixes: 207f13b419a6 ("soc: mediatek: pm-domains: Add support for mt8167") Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Link: https://lore.kernel.org/r/20210225175000.824661-4-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-02-26 01:50:00 +08:00
.name = "mfg",
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sta_mask = PWR_STATUS_MFG,
.ctl_offs = SPM_MFG_PWR_CON,
soc: mediatek: pm-domains: Move power status offset to power domain data MT8195 has more than 32 power domains so it needs two set of pwr_sta and pwr_sta2nd registers, so move the register offset from soc data into power domain data. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-5-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:03 +08:00
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
},
[MT8167_POWER_DOMAIN_CONN] = {
soc: mediatek: pm-domains: Add a power domain names for mt8167 Add the power domains names for the mt8167 SoC. Fixes: 207f13b419a6 ("soc: mediatek: pm-domains: Add support for mt8167") Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Link: https://lore.kernel.org/r/20210225175000.824661-4-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-02-26 01:50:00 +08:00
.name = "conn",
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sta_mask = PWR_STATUS_CONN,
.ctl_offs = SPM_CONN_PWR_CON,
soc: mediatek: pm-domains: Move power status offset to power domain data MT8195 has more than 32 power domains so it needs two set of pwr_sta and pwr_sta2nd registers, so move the register offset from soc data into power domain data. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-5-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:03 +08:00
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
soc: mediatek: pm-domains: Add support for mt8167 Add the needed board data to support mt8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-12-09 21:32:37 +08:00
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = 0,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
.bp_infracfg = {
BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
MT8167_TOP_AXI_PROT_EN_CONN_MCU |
MT8167_TOP_AXI_PROT_EN_MCU_CONN),
},
},
};
static const struct scpsys_soc_data mt8167_scpsys_data = {
.domains_data = scpsys_domain_data_mt8167,
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),
};
#endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */
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