2019-09-09 21:47:44 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2019, Intel Corporation. */
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#ifndef _ICE_FLEX_PIPE_H_
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#define _ICE_FLEX_PIPE_H_
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#include "ice_type.h"
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/* Package minimal version supported */
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#define ICE_PKG_SUPP_VER_MAJ 1
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#define ICE_PKG_SUPP_VER_MNR 3
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/* Package format version */
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#define ICE_PKG_FMT_VER_MAJ 1
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#define ICE_PKG_FMT_VER_MNR 0
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#define ICE_PKG_FMT_VER_UPD 0
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#define ICE_PKG_FMT_VER_DFT 0
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#define ICE_PKG_CNT 4
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2021-10-08 06:54:37 +08:00
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enum ice_ddp_state {
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/* Indicates that this call to ice_init_pkg
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* successfully loaded the requested DDP package
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*/
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ICE_DDP_PKG_SUCCESS = 0,
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/* Generic error for already loaded errors, it is mapped later to
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* the more specific one (one of the next 3)
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*/
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ICE_DDP_PKG_ALREADY_LOADED = -1,
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/* Indicates that a DDP package of the same version has already been
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* loaded onto the device by a previous call or by another PF
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*/
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ICE_DDP_PKG_SAME_VERSION_ALREADY_LOADED = -2,
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/* The device has a DDP package that is not supported by the driver */
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ICE_DDP_PKG_ALREADY_LOADED_NOT_SUPPORTED = -3,
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/* The device has a compatible package
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* (but different from the request) already loaded
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*/
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ICE_DDP_PKG_COMPATIBLE_ALREADY_LOADED = -4,
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/* The firmware loaded on the device is not compatible with
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* the DDP package loaded
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*/
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ICE_DDP_PKG_FW_MISMATCH = -5,
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/* The DDP package file is invalid */
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ICE_DDP_PKG_INVALID_FILE = -6,
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/* The version of the DDP package provided is higher than
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* the driver supports
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*/
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ICE_DDP_PKG_FILE_VERSION_TOO_HIGH = -7,
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/* The version of the DDP package provided is lower than the
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* driver supports
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*/
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ICE_DDP_PKG_FILE_VERSION_TOO_LOW = -8,
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/* The signature of the DDP package file provided is invalid */
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ICE_DDP_PKG_FILE_SIGNATURE_INVALID = -9,
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/* The DDP package file security revision is too low and not
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* supported by firmware
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*/
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ICE_DDP_PKG_FILE_REVISION_TOO_LOW = -10,
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/* An error occurred in firmware while loading the DDP package */
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ICE_DDP_PKG_LOAD_ERROR = -11,
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/* Other errors */
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ICE_DDP_PKG_ERR = -12
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};
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2021-10-08 06:56:57 +08:00
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int
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ice: create advanced switch recipe
These changes introduce code for creating advanced recipes for the
switch in hardware.
There are a couple of recipes already defined in the HW. They apply to
matching on basic protocol headers, like MAC, VLAN, MACVLAN,
ethertype or direction (promiscuous), etc.. If the user wants to match on
other protocol headers (eg. ip address, src/dst port etc.) or different
variation of already supported protocols, there is a need to create
new, more complex recipe. That new recipe is referred as
'advanced recipe', and the filtering rule created on top of that recipe
is called 'advanced rule'.
One recipe can have up to 5 words, but the first word is always reserved
for match on switch id, so the driver can define up to 4 words for one
recipe. To support recipes with more words up to 5 recipes can be
chained, so 20 words can be programmed for look up.
Input for adding recipe function is a list of protocols to support. Based
on this list correct profile is being chosen. Correct profile means
that it contains all protocol types from a list. Each profile have up to
48 field vector words and each of this word have protocol id and offset.
These two fields need to match with input data for adding recipe
function. If the correct profile can't be found the function returns an
error.
The next step after finding the correct profile is grouping words into
groups. One group can have up to 4 words. This is done to simplify
sending recipes to HW (because recipe also can have up to 4 words).
In case of chaining (so when look up consists of more than 4 words) last
recipe will always have results from the previous recipes used as words.
A recipe to profile map is used to store information about which profile
is associate with this recipe. This map is an array of 64 elements (max
number of recipes) and each element is a 256 bits bitmap (max number of
profiles)
Profile to recipe map is used to store information about which recipe is
associate with this profile. This map is an array of 256 elements (max
number of profiles) and each element is a 64 bits bitmap (max number of
recipes)
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Wojciech Drewek <wojciech.drewek@intel.com>
Tested-by: Sandeep Penigalapati <sandeep.penigalapati@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2021-08-06 16:49:00 +08:00
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ice_acquire_change_lock(struct ice_hw *hw, enum ice_aq_res_access_type access);
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void ice_release_change_lock(struct ice_hw *hw);
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2021-10-08 06:56:57 +08:00
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int
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ice: create advanced switch recipe
These changes introduce code for creating advanced recipes for the
switch in hardware.
There are a couple of recipes already defined in the HW. They apply to
matching on basic protocol headers, like MAC, VLAN, MACVLAN,
ethertype or direction (promiscuous), etc.. If the user wants to match on
other protocol headers (eg. ip address, src/dst port etc.) or different
variation of already supported protocols, there is a need to create
new, more complex recipe. That new recipe is referred as
'advanced recipe', and the filtering rule created on top of that recipe
is called 'advanced rule'.
One recipe can have up to 5 words, but the first word is always reserved
for match on switch id, so the driver can define up to 4 words for one
recipe. To support recipes with more words up to 5 recipes can be
chained, so 20 words can be programmed for look up.
Input for adding recipe function is a list of protocols to support. Based
on this list correct profile is being chosen. Correct profile means
that it contains all protocol types from a list. Each profile have up to
48 field vector words and each of this word have protocol id and offset.
These two fields need to match with input data for adding recipe
function. If the correct profile can't be found the function returns an
error.
The next step after finding the correct profile is grouping words into
groups. One group can have up to 4 words. This is done to simplify
sending recipes to HW (because recipe also can have up to 4 words).
In case of chaining (so when look up consists of more than 4 words) last
recipe will always have results from the previous recipes used as words.
A recipe to profile map is used to store information about which profile
is associate with this recipe. This map is an array of 64 elements (max
number of recipes) and each element is a 256 bits bitmap (max number of
profiles)
Profile to recipe map is used to store information about which recipe is
associate with this profile. This map is an array of 256 elements (max
number of profiles) and each element is a 64 bits bitmap (max number of
recipes)
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Wojciech Drewek <wojciech.drewek@intel.com>
Tested-by: Sandeep Penigalapati <sandeep.penigalapati@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2021-08-06 16:49:00 +08:00
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ice_find_prot_off(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 fv_idx,
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u8 *prot, u16 *off);
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2021-08-06 16:48:59 +08:00
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void
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ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,
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unsigned long *bm);
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void
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ice_init_prof_result_bm(struct ice_hw *hw);
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2021-10-08 06:56:57 +08:00
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int
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2022-03-05 00:40:47 +08:00
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ice_get_sw_fv_list(struct ice_hw *hw, struct ice_prot_lkup_ext *lkups,
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2021-08-06 16:48:59 +08:00
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unsigned long *bm, struct list_head *fv_list);
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2021-12-03 00:38:49 +08:00
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int
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ice_pkg_buf_unreserve_section(struct ice_buf_build *bld, u16 count);
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u16 ice_pkg_buf_get_free_space(struct ice_buf_build *bld);
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int
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ice_aq_upload_section(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf,
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u16 buf_size, struct ice_sq_cd *cd);
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2020-05-12 09:01:42 +08:00
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bool
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2021-11-22 23:39:25 +08:00
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ice_get_open_tunnel_port(struct ice_hw *hw, u16 *port,
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enum ice_tunnel_type type);
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2020-09-26 08:56:46 +08:00
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int ice_udp_tunnel_set_port(struct net_device *netdev, unsigned int table,
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unsigned int idx, struct udp_tunnel_info *ti);
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int ice_udp_tunnel_unset_port(struct net_device *netdev, unsigned int table,
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unsigned int idx, struct udp_tunnel_info *ti);
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2021-12-03 00:38:49 +08:00
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int ice_set_dvm_boost_entries(struct ice_hw *hw);
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2020-05-07 00:32:30 +08:00
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2021-07-17 06:16:42 +08:00
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/* Rx parser PTYPE functions */
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bool ice_hw_ptype_ena(struct ice_hw *hw, u16 ptype);
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/* XLT2/VSI group functions */
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2021-10-08 06:56:57 +08:00
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int
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2020-01-17 23:39:13 +08:00
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ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
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2021-03-09 11:08:01 +08:00
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const struct ice_ptype_attributes *attr, u16 attr_cnt,
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2021-03-09 11:07:59 +08:00
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struct ice_fv_word *es, u16 *masks);
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2021-10-08 06:56:57 +08:00
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int
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2020-01-17 23:39:14 +08:00
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ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);
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2021-10-08 06:56:57 +08:00
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int
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2020-01-17 23:39:16 +08:00
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ice_rem_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);
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2021-10-08 06:54:37 +08:00
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enum ice_ddp_state ice_init_pkg(struct ice_hw *hw, u8 *buff, u32 len);
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enum ice_ddp_state
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2019-09-09 21:47:44 +08:00
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ice_copy_and_init_pkg(struct ice_hw *hw, const u8 *buf, u32 len);
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2021-10-08 06:54:37 +08:00
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bool ice_is_init_pkg_successful(enum ice_ddp_state state);
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2021-10-08 06:56:57 +08:00
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int ice_init_hw_tbls(struct ice_hw *hw);
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2019-09-09 21:47:44 +08:00
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void ice_free_seg(struct ice_hw *hw);
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2019-09-09 21:47:46 +08:00
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void ice_fill_blk_tbls(struct ice_hw *hw);
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2019-09-09 21:47:45 +08:00
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void ice_clear_hw_tbls(struct ice_hw *hw);
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void ice_free_hw_tbls(struct ice_hw *hw);
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2021-10-08 06:59:03 +08:00
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int ice_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 id);
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2021-12-03 00:38:49 +08:00
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struct ice_buf_build *
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ice_pkg_buf_alloc_single_section(struct ice_hw *hw, u32 type, u16 size,
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void **section);
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struct ice_buf *ice_pkg_buf(struct ice_buf_build *bld);
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void ice_pkg_buf_free(struct ice_hw *hw, struct ice_buf_build *bld);
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2019-09-09 21:47:44 +08:00
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#endif /* _ICE_FLEX_PIPE_H_ */
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