License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2008-05-20 07:52:27 +08:00
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/*
|
2005-04-17 06:20:36 +08:00
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* ultra.S: Don't expand these all over the place...
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*
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2008-05-20 14:46:00 +08:00
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* Copyright (C) 1997, 2000, 2008 David S. Miller (davem@davemloft.net)
|
2005-04-17 06:20:36 +08:00
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*/
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2020-06-09 12:32:38 +08:00
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#include <linux/pgtable.h>
|
2020-06-09 12:32:42 +08:00
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#include <asm/asi.h>
|
2005-04-17 06:20:36 +08:00
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#include <asm/page.h>
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#include <asm/spitfire.h>
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#include <asm/mmu_context.h>
|
2005-08-31 11:21:34 +08:00
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#include <asm/mmu.h>
|
2005-04-17 06:20:36 +08:00
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|
|
#include <asm/pil.h>
|
|
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|
#include <asm/head.h>
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|
|
#include <asm/thread_info.h>
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#include <asm/cacheflush.h>
|
2006-02-04 19:08:37 +08:00
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#include <asm/hypervisor.h>
|
2008-05-20 14:46:00 +08:00
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#include <asm/cpudata.h>
|
2005-04-17 06:20:36 +08:00
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|
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/* Basically, most of the Spitfire vs. Cheetah madness
|
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|
* has to do with the fact that Cheetah does not support
|
|
|
|
* IMMU flushes out of the secondary context. Someone needs
|
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|
* to throw a south lake birthday party for the folks
|
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|
* in Microelectronics who refused to fix this shit.
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|
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*/
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/* This file is meant to be read efficiently by the CPU, not humans.
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* Staraj sie tego nikomu nie pierdolnac...
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*/
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.text
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|
.align 32
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|
|
|
.globl __flush_tlb_mm
|
2016-10-26 07:23:26 +08:00
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|
|
__flush_tlb_mm: /* 19 insns */
|
2006-02-04 19:08:37 +08:00
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|
|
/* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */
|
2005-04-17 06:20:36 +08:00
|
|
|
ldxa [%o1] ASI_DMMU, %g2
|
|
|
|
cmp %g2, %o0
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|
|
|
bne,pn %icc, __spitfire_flush_tlb_mm_slow
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|
|
|
mov 0x50, %g3
|
|
|
|
stxa %g0, [%g3] ASI_DMMU_DEMAP
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|
|
stxa %g0, [%g3] ASI_IMMU_DEMAP
|
2006-02-01 10:33:00 +08:00
|
|
|
sethi %hi(KERNBASE), %g3
|
|
|
|
flush %g3
|
2005-04-17 06:20:36 +08:00
|
|
|
retl
|
2006-02-01 10:33:00 +08:00
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|
|
nop
|
2005-04-17 06:20:36 +08:00
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|
|
nop
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|
nop
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|
nop
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|
nop
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|
nop
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|
nop
|
|
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|
nop
|
2005-08-31 11:21:34 +08:00
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|
|
nop
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|
|
|
nop
|
2005-04-17 06:20:36 +08:00
|
|
|
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
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|
|
.align 32
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|
|
|
.globl __flush_tlb_page
|
|
|
|
__flush_tlb_page: /* 22 insns */
|
|
|
|
/* %o0 = context, %o1 = vaddr */
|
|
|
|
rdpr %pstate, %g7
|
|
|
|
andn %g7, PSTATE_IE, %g2
|
|
|
|
wrpr %g2, %pstate
|
|
|
|
mov SECONDARY_CONTEXT, %o4
|
|
|
|
ldxa [%o4] ASI_DMMU, %g2
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|
|
|
stxa %o0, [%o4] ASI_DMMU
|
|
|
|
andcc %o1, 1, %g0
|
|
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|
andn %o1, 1, %o3
|
|
|
|
be,pn %icc, 1f
|
|
|
|
or %o3, 0x10, %o3
|
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|
stxa %g0, [%o3] ASI_IMMU_DEMAP
|
|
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|
1: stxa %g0, [%o3] ASI_DMMU_DEMAP
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|
|
|
membar #Sync
|
|
|
|
stxa %g2, [%o4] ASI_DMMU
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|
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|
sethi %hi(KERNBASE), %o4
|
|
|
|
flush %o4
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|
retl
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|
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|
wrpr %g7, 0x0, %pstate
|
|
|
|
nop
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|
|
|
nop
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|
|
|
nop
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|
|
|
nop
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
.align 32
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|
.globl __flush_tlb_pending
|
2016-10-26 07:23:26 +08:00
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__flush_tlb_pending: /* 27 insns */
|
2005-04-17 06:20:36 +08:00
|
|
|
/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
|
|
|
|
rdpr %pstate, %g7
|
|
|
|
sllx %o1, 3, %o1
|
|
|
|
andn %g7, PSTATE_IE, %g2
|
|
|
|
wrpr %g2, %pstate
|
|
|
|
mov SECONDARY_CONTEXT, %o4
|
|
|
|
ldxa [%o4] ASI_DMMU, %g2
|
|
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|
stxa %o0, [%o4] ASI_DMMU
|
|
|
|
1: sub %o1, (1 << 3), %o1
|
|
|
|
ldx [%o2 + %o1], %o3
|
|
|
|
andcc %o3, 1, %g0
|
|
|
|
andn %o3, 1, %o3
|
|
|
|
be,pn %icc, 2f
|
|
|
|
or %o3, 0x10, %o3
|
|
|
|
stxa %g0, [%o3] ASI_IMMU_DEMAP
|
|
|
|
2: stxa %g0, [%o3] ASI_DMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
brnz,pt %o1, 1b
|
|
|
|
nop
|
|
|
|
stxa %g2, [%o4] ASI_DMMU
|
2006-02-01 10:33:00 +08:00
|
|
|
sethi %hi(KERNBASE), %o4
|
|
|
|
flush %o4
|
2005-04-17 06:20:36 +08:00
|
|
|
retl
|
|
|
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wrpr %g7, 0x0, %pstate
|
2005-07-06 10:45:24 +08:00
|
|
|
nop
|
2005-08-31 11:21:34 +08:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
.align 32
|
|
|
|
.globl __flush_tlb_kernel_range
|
2016-10-28 00:04:54 +08:00
|
|
|
__flush_tlb_kernel_range: /* 31 insns */
|
2006-02-04 19:08:37 +08:00
|
|
|
/* %o0=start, %o1=end */
|
2005-04-17 06:20:36 +08:00
|
|
|
cmp %o0, %o1
|
|
|
|
be,pn %xcc, 2f
|
2016-10-28 00:04:54 +08:00
|
|
|
sub %o1, %o0, %o3
|
|
|
|
srlx %o3, 18, %o4
|
|
|
|
brnz,pn %o4, __spitfire_flush_tlb_kernel_range_slow
|
2005-04-17 06:20:36 +08:00
|
|
|
sethi %hi(PAGE_SIZE), %o4
|
|
|
|
sub %o3, %o4, %o3
|
|
|
|
or %o0, 0x20, %o0 ! Nucleus
|
|
|
|
1: stxa %g0, [%o0 + %o3] ASI_DMMU_DEMAP
|
|
|
|
stxa %g0, [%o0 + %o3] ASI_IMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
brnz,pt %o3, 1b
|
|
|
|
sub %o3, %o4, %o3
|
2006-02-01 10:33:00 +08:00
|
|
|
2: sethi %hi(KERNBASE), %o3
|
|
|
|
flush %o3
|
|
|
|
retl
|
|
|
|
nop
|
2006-02-04 19:08:37 +08:00
|
|
|
nop
|
2016-10-26 07:23:26 +08:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2016-10-28 00:04:54 +08:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
|
|
|
|
__spitfire_flush_tlb_kernel_range_slow:
|
|
|
|
mov 63 * 8, %o4
|
|
|
|
1: ldxa [%o4] ASI_ITLB_DATA_ACCESS, %o3
|
|
|
|
andcc %o3, 0x40, %g0 /* _PAGE_L_4U */
|
|
|
|
bne,pn %xcc, 2f
|
|
|
|
mov TLB_TAG_ACCESS, %o3
|
|
|
|
stxa %g0, [%o3] ASI_IMMU
|
|
|
|
stxa %g0, [%o4] ASI_ITLB_DATA_ACCESS
|
|
|
|
membar #Sync
|
|
|
|
2: ldxa [%o4] ASI_DTLB_DATA_ACCESS, %o3
|
|
|
|
andcc %o3, 0x40, %g0
|
|
|
|
bne,pn %xcc, 2f
|
|
|
|
mov TLB_TAG_ACCESS, %o3
|
|
|
|
stxa %g0, [%o3] ASI_DMMU
|
|
|
|
stxa %g0, [%o4] ASI_DTLB_DATA_ACCESS
|
|
|
|
membar #Sync
|
|
|
|
2: sub %o4, 8, %o4
|
|
|
|
brgez,pt %o4, 1b
|
|
|
|
nop
|
|
|
|
retl
|
|
|
|
nop
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
__spitfire_flush_tlb_mm_slow:
|
|
|
|
rdpr %pstate, %g1
|
|
|
|
wrpr %g1, PSTATE_IE, %pstate
|
|
|
|
stxa %o0, [%o1] ASI_DMMU
|
|
|
|
stxa %g0, [%g3] ASI_DMMU_DEMAP
|
|
|
|
stxa %g0, [%g3] ASI_IMMU_DEMAP
|
|
|
|
flush %g6
|
|
|
|
stxa %g2, [%o1] ASI_DMMU
|
2006-02-01 10:33:00 +08:00
|
|
|
sethi %hi(KERNBASE), %o1
|
|
|
|
flush %o1
|
2005-04-17 06:20:36 +08:00
|
|
|
retl
|
|
|
|
wrpr %g1, 0, %pstate
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The following code flushes one page_size worth.
|
|
|
|
*/
|
2005-09-07 06:19:31 +08:00
|
|
|
.section .kprobes.text, "ax"
|
2005-04-17 06:20:36 +08:00
|
|
|
.align 32
|
|
|
|
.globl __flush_icache_page
|
|
|
|
__flush_icache_page: /* %o0 = phys_page */
|
|
|
|
srlx %o0, PAGE_SHIFT, %o0
|
2013-09-21 12:50:41 +08:00
|
|
|
sethi %hi(PAGE_OFFSET), %g1
|
2005-04-17 06:20:36 +08:00
|
|
|
sllx %o0, PAGE_SHIFT, %o0
|
|
|
|
sethi %hi(PAGE_SIZE), %g2
|
2013-09-21 12:50:41 +08:00
|
|
|
ldx [%g1 + %lo(PAGE_OFFSET)], %g1
|
2005-04-17 06:20:36 +08:00
|
|
|
add %o0, %g1, %o0
|
|
|
|
1: subcc %g2, 32, %g2
|
|
|
|
bne,pt %icc, 1b
|
|
|
|
flush %o0 + %g2
|
|
|
|
retl
|
|
|
|
nop
|
|
|
|
|
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
|
|
|
|
|
|
#if (PAGE_SHIFT != 13)
|
|
|
|
#error only page shift of 13 is supported by dcache flush
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#define DTAG_MASK 0x3
|
|
|
|
|
2005-09-27 07:06:03 +08:00
|
|
|
/* This routine is Spitfire specific so the hardcoded
|
|
|
|
* D-cache size and line-size are OK.
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
.align 64
|
|
|
|
.globl __flush_dcache_page
|
|
|
|
__flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */
|
2013-09-21 12:50:41 +08:00
|
|
|
sethi %hi(PAGE_OFFSET), %g1
|
|
|
|
ldx [%g1 + %lo(PAGE_OFFSET)], %g1
|
2005-09-27 07:06:03 +08:00
|
|
|
sub %o0, %g1, %o0 ! physical address
|
|
|
|
srlx %o0, 11, %o0 ! make D-cache TAG
|
|
|
|
sethi %hi(1 << 14), %o2 ! D-cache size
|
|
|
|
sub %o2, (1 << 5), %o2 ! D-cache line size
|
|
|
|
1: ldxa [%o2] ASI_DCACHE_TAG, %o3 ! load D-cache TAG
|
|
|
|
andcc %o3, DTAG_MASK, %g0 ! Valid?
|
|
|
|
be,pn %xcc, 2f ! Nope, branch
|
|
|
|
andn %o3, DTAG_MASK, %o3 ! Clear valid bits
|
|
|
|
cmp %o3, %o0 ! TAG match?
|
|
|
|
bne,pt %xcc, 2f ! Nope, branch
|
|
|
|
nop
|
|
|
|
stxa %g0, [%o2] ASI_DCACHE_TAG ! Invalidate TAG
|
|
|
|
membar #Sync
|
|
|
|
2: brnz,pt %o2, 1b
|
|
|
|
sub %o2, (1 << 5), %o2 ! D-cache line size
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
/* The I-cache does not snoop local stores so we
|
|
|
|
* better flush that too when necessary.
|
|
|
|
*/
|
|
|
|
brnz,pt %o1, __flush_icache_page
|
|
|
|
sllx %o0, 11, %o0
|
|
|
|
retl
|
|
|
|
nop
|
|
|
|
|
|
|
|
#endif /* DCACHE_ALIASING_POSSIBLE */
|
|
|
|
|
2005-09-27 07:06:03 +08:00
|
|
|
.previous
|
|
|
|
|
2005-08-31 11:21:34 +08:00
|
|
|
/* Cheetah specific versions, patched at boot time. */
|
2006-02-01 10:33:00 +08:00
|
|
|
__cheetah_flush_tlb_mm: /* 19 insns */
|
2005-04-17 06:20:36 +08:00
|
|
|
rdpr %pstate, %g7
|
|
|
|
andn %g7, PSTATE_IE, %g2
|
|
|
|
wrpr %g2, 0x0, %pstate
|
|
|
|
wrpr %g0, 1, %tl
|
|
|
|
mov PRIMARY_CONTEXT, %o2
|
|
|
|
mov 0x40, %g3
|
|
|
|
ldxa [%o2] ASI_DMMU, %g2
|
2005-08-31 11:21:34 +08:00
|
|
|
srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o1
|
|
|
|
sllx %o1, CTX_PGSZ1_NUC_SHIFT, %o1
|
|
|
|
or %o0, %o1, %o0 /* Preserve nucleus page size fields */
|
2005-04-17 06:20:36 +08:00
|
|
|
stxa %o0, [%o2] ASI_DMMU
|
|
|
|
stxa %g0, [%g3] ASI_DMMU_DEMAP
|
|
|
|
stxa %g0, [%g3] ASI_IMMU_DEMAP
|
|
|
|
stxa %g2, [%o2] ASI_DMMU
|
2006-02-01 10:33:00 +08:00
|
|
|
sethi %hi(KERNBASE), %o2
|
|
|
|
flush %o2
|
2005-04-17 06:20:36 +08:00
|
|
|
wrpr %g0, 0, %tl
|
|
|
|
retl
|
|
|
|
wrpr %g7, 0x0, %pstate
|
|
|
|
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
__cheetah_flush_tlb_page: /* 22 insns */
|
|
|
|
/* %o0 = context, %o1 = vaddr */
|
|
|
|
rdpr %pstate, %g7
|
|
|
|
andn %g7, PSTATE_IE, %g2
|
|
|
|
wrpr %g2, 0x0, %pstate
|
|
|
|
wrpr %g0, 1, %tl
|
|
|
|
mov PRIMARY_CONTEXT, %o4
|
|
|
|
ldxa [%o4] ASI_DMMU, %g2
|
|
|
|
srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o3
|
|
|
|
sllx %o3, CTX_PGSZ1_NUC_SHIFT, %o3
|
|
|
|
or %o0, %o3, %o0 /* Preserve nucleus page size fields */
|
|
|
|
stxa %o0, [%o4] ASI_DMMU
|
|
|
|
andcc %o1, 1, %g0
|
|
|
|
be,pn %icc, 1f
|
|
|
|
andn %o1, 1, %o3
|
|
|
|
stxa %g0, [%o3] ASI_IMMU_DEMAP
|
|
|
|
1: stxa %g0, [%o3] ASI_DMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
stxa %g2, [%o4] ASI_DMMU
|
|
|
|
sethi %hi(KERNBASE), %o4
|
|
|
|
flush %o4
|
|
|
|
wrpr %g0, 0, %tl
|
|
|
|
retl
|
|
|
|
wrpr %g7, 0x0, %pstate
|
|
|
|
|
2006-02-01 10:33:00 +08:00
|
|
|
__cheetah_flush_tlb_pending: /* 27 insns */
|
2005-04-17 06:20:36 +08:00
|
|
|
/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
|
|
|
|
rdpr %pstate, %g7
|
|
|
|
sllx %o1, 3, %o1
|
|
|
|
andn %g7, PSTATE_IE, %g2
|
|
|
|
wrpr %g2, 0x0, %pstate
|
|
|
|
wrpr %g0, 1, %tl
|
|
|
|
mov PRIMARY_CONTEXT, %o4
|
|
|
|
ldxa [%o4] ASI_DMMU, %g2
|
2005-08-31 11:21:34 +08:00
|
|
|
srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o3
|
|
|
|
sllx %o3, CTX_PGSZ1_NUC_SHIFT, %o3
|
|
|
|
or %o0, %o3, %o0 /* Preserve nucleus page size fields */
|
2005-04-17 06:20:36 +08:00
|
|
|
stxa %o0, [%o4] ASI_DMMU
|
|
|
|
1: sub %o1, (1 << 3), %o1
|
|
|
|
ldx [%o2 + %o1], %o3
|
|
|
|
andcc %o3, 1, %g0
|
|
|
|
be,pn %icc, 2f
|
|
|
|
andn %o3, 1, %o3
|
|
|
|
stxa %g0, [%o3] ASI_IMMU_DEMAP
|
|
|
|
2: stxa %g0, [%o3] ASI_DMMU_DEMAP
|
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
|
|
|
membar #Sync
|
2005-04-17 06:20:36 +08:00
|
|
|
brnz,pt %o1, 1b
|
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
|
|
|
nop
|
2005-04-17 06:20:36 +08:00
|
|
|
stxa %g2, [%o4] ASI_DMMU
|
2006-02-01 10:33:00 +08:00
|
|
|
sethi %hi(KERNBASE), %o4
|
|
|
|
flush %o4
|
2005-04-17 06:20:36 +08:00
|
|
|
wrpr %g0, 0, %tl
|
|
|
|
retl
|
|
|
|
wrpr %g7, 0x0, %pstate
|
|
|
|
|
2016-10-28 00:04:54 +08:00
|
|
|
__cheetah_flush_tlb_kernel_range: /* 31 insns */
|
|
|
|
/* %o0=start, %o1=end */
|
|
|
|
cmp %o0, %o1
|
|
|
|
be,pn %xcc, 2f
|
|
|
|
sub %o1, %o0, %o3
|
|
|
|
srlx %o3, 18, %o4
|
|
|
|
brnz,pn %o4, 3f
|
|
|
|
sethi %hi(PAGE_SIZE), %o4
|
|
|
|
sub %o3, %o4, %o3
|
|
|
|
or %o0, 0x20, %o0 ! Nucleus
|
|
|
|
1: stxa %g0, [%o0 + %o3] ASI_DMMU_DEMAP
|
|
|
|
stxa %g0, [%o0 + %o3] ASI_IMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
brnz,pt %o3, 1b
|
|
|
|
sub %o3, %o4, %o3
|
|
|
|
2: sethi %hi(KERNBASE), %o3
|
|
|
|
flush %o3
|
|
|
|
retl
|
|
|
|
nop
|
|
|
|
3: mov 0x80, %o4
|
|
|
|
stxa %g0, [%o4] ASI_DMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
stxa %g0, [%o4] ASI_IMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
retl
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
2005-09-27 07:06:03 +08:00
|
|
|
__cheetah_flush_dcache_page: /* 11 insns */
|
2013-09-21 12:50:41 +08:00
|
|
|
sethi %hi(PAGE_OFFSET), %g1
|
|
|
|
ldx [%g1 + %lo(PAGE_OFFSET)], %g1
|
2005-04-17 06:20:36 +08:00
|
|
|
sub %o0, %g1, %o0
|
|
|
|
sethi %hi(PAGE_SIZE), %o4
|
|
|
|
1: subcc %o4, (1 << 5), %o4
|
|
|
|
stxa %g0, [%o0 + %o4] ASI_DCACHE_INVALIDATE
|
|
|
|
membar #Sync
|
|
|
|
bne,pt %icc, 1b
|
|
|
|
nop
|
|
|
|
retl /* I-cache flush never needed on Cheetah, see callers. */
|
|
|
|
nop
|
|
|
|
#endif /* DCACHE_ALIASING_POSSIBLE */
|
|
|
|
|
2006-02-04 19:08:37 +08:00
|
|
|
/* Hypervisor specific versions, patched at boot time. */
|
2006-02-27 11:31:49 +08:00
|
|
|
__hypervisor_tlb_tl0_error:
|
|
|
|
save %sp, -192, %sp
|
|
|
|
mov %i0, %o0
|
|
|
|
call hypervisor_tlbop_error
|
|
|
|
mov %i1, %o1
|
|
|
|
ret
|
|
|
|
restore
|
|
|
|
|
2016-10-26 07:23:26 +08:00
|
|
|
__hypervisor_flush_tlb_mm: /* 19 insns */
|
2006-02-04 19:08:37 +08:00
|
|
|
mov %o0, %o2 /* ARG2: mmu context */
|
|
|
|
mov 0, %o0 /* ARG0: CPU lists unimplemented */
|
|
|
|
mov 0, %o1 /* ARG1: CPU lists unimplemented */
|
|
|
|
mov HV_MMU_ALL, %o3 /* ARG3: flags */
|
|
|
|
mov HV_FAST_MMU_DEMAP_CTX, %o5
|
|
|
|
ta HV_FAST_TRAP
|
2016-10-26 07:23:26 +08:00
|
|
|
brnz,pn %o0, 1f
|
2006-02-27 11:31:49 +08:00
|
|
|
mov HV_FAST_MMU_DEMAP_CTX, %o1
|
2006-02-04 19:08:37 +08:00
|
|
|
retl
|
|
|
|
nop
|
2016-10-26 07:23:26 +08:00
|
|
|
1: sethi %hi(__hypervisor_tlb_tl0_error), %o5
|
|
|
|
jmpl %o5 + %lo(__hypervisor_tlb_tl0_error), %g0
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2006-02-04 19:08:37 +08:00
|
|
|
|
2016-10-26 07:23:26 +08:00
|
|
|
__hypervisor_flush_tlb_page: /* 22 insns */
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
/* %o0 = context, %o1 = vaddr */
|
|
|
|
mov %o0, %g2
|
|
|
|
mov %o1, %o0 /* ARG0: vaddr + IMMU-bit */
|
|
|
|
mov %g2, %o1 /* ARG1: mmu context */
|
|
|
|
mov HV_MMU_ALL, %o2 /* ARG2: flags */
|
|
|
|
srlx %o0, PAGE_SHIFT, %o0
|
|
|
|
sllx %o0, PAGE_SHIFT, %o0
|
|
|
|
ta HV_MMU_UNMAP_ADDR_TRAP
|
2016-10-26 07:23:26 +08:00
|
|
|
brnz,pn %o0, 1f
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
mov HV_MMU_UNMAP_ADDR_TRAP, %o1
|
|
|
|
retl
|
|
|
|
nop
|
2016-10-26 07:23:26 +08:00
|
|
|
1: sethi %hi(__hypervisor_tlb_tl0_error), %o2
|
|
|
|
jmpl %o2 + %lo(__hypervisor_tlb_tl0_error), %g0
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
|
2016-10-27 01:08:22 +08:00
|
|
|
__hypervisor_flush_tlb_pending: /* 27 insns */
|
2006-02-04 19:08:37 +08:00
|
|
|
/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
|
|
|
|
sllx %o1, 3, %g1
|
|
|
|
mov %o2, %g2
|
|
|
|
mov %o0, %g3
|
|
|
|
1: sub %g1, (1 << 3), %g1
|
|
|
|
ldx [%g2 + %g1], %o0 /* ARG0: vaddr + IMMU-bit */
|
|
|
|
mov %g3, %o1 /* ARG1: mmu context */
|
2006-02-27 11:31:49 +08:00
|
|
|
mov HV_MMU_ALL, %o2 /* ARG2: flags */
|
|
|
|
srlx %o0, PAGE_SHIFT, %o0
|
|
|
|
sllx %o0, PAGE_SHIFT, %o0
|
2006-02-04 19:08:37 +08:00
|
|
|
ta HV_MMU_UNMAP_ADDR_TRAP
|
2016-10-26 07:23:26 +08:00
|
|
|
brnz,pn %o0, 1f
|
2006-02-27 11:31:49 +08:00
|
|
|
mov HV_MMU_UNMAP_ADDR_TRAP, %o1
|
2006-02-04 19:08:37 +08:00
|
|
|
brnz,pt %g1, 1b
|
|
|
|
nop
|
|
|
|
retl
|
|
|
|
nop
|
2016-10-26 07:23:26 +08:00
|
|
|
1: sethi %hi(__hypervisor_tlb_tl0_error), %o2
|
|
|
|
jmpl %o2 + %lo(__hypervisor_tlb_tl0_error), %g0
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2006-02-04 19:08:37 +08:00
|
|
|
|
2016-10-28 00:04:54 +08:00
|
|
|
__hypervisor_flush_tlb_kernel_range: /* 31 insns */
|
2006-02-04 19:08:37 +08:00
|
|
|
/* %o0=start, %o1=end */
|
|
|
|
cmp %o0, %o1
|
|
|
|
be,pn %xcc, 2f
|
2016-10-28 00:04:54 +08:00
|
|
|
sub %o1, %o0, %g2
|
|
|
|
srlx %g2, 18, %g3
|
|
|
|
brnz,pn %g3, 4f
|
|
|
|
mov %o0, %g1
|
|
|
|
sethi %hi(PAGE_SIZE), %g3
|
2006-02-04 19:08:37 +08:00
|
|
|
sub %g2, %g3, %g2
|
|
|
|
1: add %g1, %g2, %o0 /* ARG0: virtual address */
|
|
|
|
mov 0, %o1 /* ARG1: mmu context */
|
|
|
|
mov HV_MMU_ALL, %o2 /* ARG2: flags */
|
|
|
|
ta HV_MMU_UNMAP_ADDR_TRAP
|
2016-10-26 07:23:26 +08:00
|
|
|
brnz,pn %o0, 3f
|
2006-02-27 11:31:49 +08:00
|
|
|
mov HV_MMU_UNMAP_ADDR_TRAP, %o1
|
2006-02-04 19:08:37 +08:00
|
|
|
brnz,pt %g2, 1b
|
|
|
|
sub %g2, %g3, %g2
|
|
|
|
2: retl
|
|
|
|
nop
|
2016-10-26 07:23:26 +08:00
|
|
|
3: sethi %hi(__hypervisor_tlb_tl0_error), %o2
|
|
|
|
jmpl %o2 + %lo(__hypervisor_tlb_tl0_error), %g0
|
|
|
|
nop
|
2016-10-28 00:04:54 +08:00
|
|
|
4: mov 0, %o0 /* ARG0: CPU lists unimplemented */
|
|
|
|
mov 0, %o1 /* ARG1: CPU lists unimplemented */
|
|
|
|
mov 0, %o2 /* ARG2: mmu context == nucleus */
|
|
|
|
mov HV_MMU_ALL, %o3 /* ARG3: flags */
|
|
|
|
mov HV_FAST_MMU_DEMAP_CTX, %o5
|
|
|
|
ta HV_FAST_TRAP
|
|
|
|
brnz,pn %o0, 3b
|
|
|
|
mov HV_FAST_MMU_DEMAP_CTX, %o1
|
|
|
|
retl
|
|
|
|
nop
|
2006-02-04 19:08:37 +08:00
|
|
|
|
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
|
|
/* XXX Niagara and friends have an 8K cache, so no aliasing is
|
|
|
|
* XXX possible, but nothing explicit in the Hypervisor API
|
|
|
|
* XXX guarantees this.
|
|
|
|
*/
|
|
|
|
__hypervisor_flush_dcache_page: /* 2 insns */
|
|
|
|
retl
|
|
|
|
nop
|
|
|
|
#endif
|
|
|
|
|
|
|
|
tlb_patch_one:
|
2005-04-17 06:20:36 +08:00
|
|
|
1: lduw [%o1], %g1
|
|
|
|
stw %g1, [%o0]
|
|
|
|
flush %o0
|
|
|
|
subcc %o2, 1, %o2
|
|
|
|
add %o1, 4, %o1
|
|
|
|
bne,pt %icc, 1b
|
|
|
|
add %o0, 4, %o0
|
|
|
|
retl
|
|
|
|
nop
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
/* These are all called by the slaves of a cross call, at
|
|
|
|
* trap level 1, with interrupts fully disabled.
|
|
|
|
*
|
|
|
|
* Register usage:
|
|
|
|
* %g5 mm->context (all tlb flushes)
|
|
|
|
* %g1 address arg 1 (tlb page and range flushes)
|
|
|
|
* %g7 address arg 2 (tlb range flush only)
|
|
|
|
*
|
2006-02-27 15:24:22 +08:00
|
|
|
* %g6 scratch 1
|
|
|
|
* %g2 scratch 2
|
|
|
|
* %g3 scratch 3
|
|
|
|
* %g4 scratch 4
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
|
|
|
.align 32
|
|
|
|
.globl xcall_flush_tlb_mm
|
2016-10-27 01:20:14 +08:00
|
|
|
xcall_flush_tlb_mm: /* 24 insns */
|
2005-04-17 06:20:36 +08:00
|
|
|
mov PRIMARY_CONTEXT, %g2
|
|
|
|
ldxa [%g2] ASI_DMMU, %g3
|
2005-08-31 11:21:34 +08:00
|
|
|
srlx %g3, CTX_PGSZ1_NUC_SHIFT, %g4
|
|
|
|
sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
|
|
|
|
or %g5, %g4, %g5 /* Preserve nucleus page size fields */
|
2005-04-17 06:20:36 +08:00
|
|
|
stxa %g5, [%g2] ASI_DMMU
|
2005-08-31 11:21:34 +08:00
|
|
|
mov 0x40, %g4
|
2005-04-17 06:20:36 +08:00
|
|
|
stxa %g0, [%g4] ASI_DMMU_DEMAP
|
|
|
|
stxa %g0, [%g4] ASI_IMMU_DEMAP
|
|
|
|
stxa %g3, [%g2] ASI_DMMU
|
|
|
|
retry
|
2006-02-04 19:08:37 +08:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2006-02-27 11:31:49 +08:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2016-10-27 01:20:14 +08:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2005-04-17 06:20:36 +08:00
|
|
|
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
.globl xcall_flush_tlb_page
|
2016-10-27 01:20:14 +08:00
|
|
|
xcall_flush_tlb_page: /* 20 insns */
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
/* %g5=context, %g1=vaddr */
|
2005-04-17 06:20:36 +08:00
|
|
|
mov PRIMARY_CONTEXT, %g4
|
|
|
|
ldxa [%g4] ASI_DMMU, %g2
|
2005-08-31 11:21:34 +08:00
|
|
|
srlx %g2, CTX_PGSZ1_NUC_SHIFT, %g4
|
|
|
|
sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
|
|
|
|
or %g5, %g4, %g5
|
|
|
|
mov PRIMARY_CONTEXT, %g4
|
2005-04-17 06:20:36 +08:00
|
|
|
stxa %g5, [%g4] ASI_DMMU
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
andcc %g1, 0x1, %g0
|
2005-04-17 06:20:36 +08:00
|
|
|
be,pn %icc, 2f
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
andn %g1, 0x1, %g5
|
2005-04-17 06:20:36 +08:00
|
|
|
stxa %g0, [%g5] ASI_IMMU_DEMAP
|
|
|
|
2: stxa %g0, [%g5] ASI_DMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
stxa %g2, [%g4] ASI_DMMU
|
|
|
|
retry
|
2006-02-27 11:31:49 +08:00
|
|
|
nop
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
nop
|
2016-10-27 01:20:14 +08:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
.globl xcall_flush_tlb_kernel_range
|
2016-10-28 00:04:54 +08:00
|
|
|
xcall_flush_tlb_kernel_range: /* 44 insns */
|
2005-04-17 06:20:36 +08:00
|
|
|
sethi %hi(PAGE_SIZE - 1), %g2
|
|
|
|
or %g2, %lo(PAGE_SIZE - 1), %g2
|
|
|
|
andn %g1, %g2, %g1
|
|
|
|
andn %g7, %g2, %g7
|
|
|
|
sub %g7, %g1, %g3
|
2016-10-28 00:04:54 +08:00
|
|
|
srlx %g3, 18, %g2
|
|
|
|
brnz,pn %g2, 2f
|
2019-05-30 05:31:31 +08:00
|
|
|
sethi %hi(PAGE_SIZE), %g2
|
2005-04-17 06:20:36 +08:00
|
|
|
sub %g3, %g2, %g3
|
|
|
|
or %g1, 0x20, %g1 ! Nucleus
|
|
|
|
1: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP
|
|
|
|
stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
brnz,pt %g3, 1b
|
|
|
|
sub %g3, %g2, %g3
|
|
|
|
retry
|
2016-10-28 00:04:54 +08:00
|
|
|
2: mov 63 * 8, %g1
|
|
|
|
1: ldxa [%g1] ASI_ITLB_DATA_ACCESS, %g2
|
|
|
|
andcc %g2, 0x40, %g0 /* _PAGE_L_4U */
|
|
|
|
bne,pn %xcc, 2f
|
|
|
|
mov TLB_TAG_ACCESS, %g2
|
|
|
|
stxa %g0, [%g2] ASI_IMMU
|
|
|
|
stxa %g0, [%g1] ASI_ITLB_DATA_ACCESS
|
|
|
|
membar #Sync
|
|
|
|
2: ldxa [%g1] ASI_DTLB_DATA_ACCESS, %g2
|
|
|
|
andcc %g2, 0x40, %g0
|
|
|
|
bne,pn %xcc, 2f
|
|
|
|
mov TLB_TAG_ACCESS, %g2
|
|
|
|
stxa %g0, [%g2] ASI_DMMU
|
|
|
|
stxa %g0, [%g1] ASI_DTLB_DATA_ACCESS
|
|
|
|
membar #Sync
|
|
|
|
2: sub %g1, 8, %g1
|
|
|
|
brgez,pt %g1, 1b
|
|
|
|
nop
|
|
|
|
retry
|
2006-02-04 19:08:37 +08:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2006-02-27 11:31:49 +08:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2016-10-27 01:20:14 +08:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
/* This runs in a very controlled environment, so we do
|
|
|
|
* not need to worry about BH races etc.
|
|
|
|
*/
|
|
|
|
.globl xcall_sync_tick
|
|
|
|
xcall_sync_tick:
|
2006-02-06 14:27:28 +08:00
|
|
|
|
|
|
|
661: rdpr %pstate, %g2
|
2005-04-17 06:20:36 +08:00
|
|
|
wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
|
2006-02-07 16:00:16 +08:00
|
|
|
.section .sun4v_2insn_patch, "ax"
|
2006-02-06 14:27:28 +08:00
|
|
|
.word 661b
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
.previous
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
rdpr %pil, %g2
|
2008-11-24 13:55:29 +08:00
|
|
|
wrpr %g0, PIL_NORMAL_MAX, %pil
|
2005-04-17 06:20:36 +08:00
|
|
|
sethi %hi(109f), %g7
|
|
|
|
b,pt %xcc, etrap_irq
|
|
|
|
109: or %g7, %lo(109b), %g7
|
2006-11-17 05:38:57 +08:00
|
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
|
|
|
call trace_hardirqs_off
|
|
|
|
nop
|
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
call smp_synchronize_tick_client
|
|
|
|
nop
|
|
|
|
b rtrap_xcall
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
|
|
|
|
|
2008-05-20 14:46:00 +08:00
|
|
|
.globl xcall_fetch_glob_regs
|
|
|
|
xcall_fetch_glob_regs:
|
2012-10-17 00:34:01 +08:00
|
|
|
sethi %hi(global_cpu_snapshot), %g1
|
|
|
|
or %g1, %lo(global_cpu_snapshot), %g1
|
2008-05-20 14:46:00 +08:00
|
|
|
__GET_CPUID(%g2)
|
|
|
|
sllx %g2, 6, %g3
|
|
|
|
add %g1, %g3, %g1
|
|
|
|
rdpr %tstate, %g7
|
|
|
|
stx %g7, [%g1 + GR_SNAP_TSTATE]
|
|
|
|
rdpr %tpc, %g7
|
|
|
|
stx %g7, [%g1 + GR_SNAP_TPC]
|
|
|
|
rdpr %tnpc, %g7
|
|
|
|
stx %g7, [%g1 + GR_SNAP_TNPC]
|
|
|
|
stx %o7, [%g1 + GR_SNAP_O7]
|
|
|
|
stx %i7, [%g1 + GR_SNAP_I7]
|
2008-07-31 12:57:59 +08:00
|
|
|
/* Don't try this at home kids... */
|
2012-05-11 02:00:46 +08:00
|
|
|
rdpr %cwp, %g3
|
|
|
|
sub %g3, 1, %g7
|
2008-07-31 12:57:59 +08:00
|
|
|
wrpr %g7, %cwp
|
|
|
|
mov %i7, %g7
|
2012-05-11 02:00:46 +08:00
|
|
|
wrpr %g3, %cwp
|
2008-07-31 12:57:59 +08:00
|
|
|
stx %g7, [%g1 + GR_SNAP_RPC]
|
2008-05-20 14:46:00 +08:00
|
|
|
sethi %hi(trap_block), %g7
|
|
|
|
or %g7, %lo(trap_block), %g7
|
|
|
|
sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2
|
|
|
|
add %g7, %g2, %g7
|
|
|
|
ldx [%g7 + TRAP_PER_CPU_THREAD], %g3
|
|
|
|
stx %g3, [%g1 + GR_SNAP_THREAD]
|
|
|
|
retry
|
|
|
|
|
2012-10-17 00:34:01 +08:00
|
|
|
.globl xcall_fetch_glob_pmu
|
|
|
|
xcall_fetch_glob_pmu:
|
|
|
|
sethi %hi(global_cpu_snapshot), %g1
|
|
|
|
or %g1, %lo(global_cpu_snapshot), %g1
|
|
|
|
__GET_CPUID(%g2)
|
|
|
|
sllx %g2, 6, %g3
|
|
|
|
add %g1, %g3, %g1
|
|
|
|
rd %pic, %g7
|
|
|
|
stx %g7, [%g1 + (4 * 8)]
|
|
|
|
rd %pcr, %g7
|
|
|
|
stx %g7, [%g1 + (0 * 8)]
|
|
|
|
retry
|
|
|
|
|
|
|
|
.globl xcall_fetch_glob_pmu_n4
|
|
|
|
xcall_fetch_glob_pmu_n4:
|
|
|
|
sethi %hi(global_cpu_snapshot), %g1
|
|
|
|
or %g1, %lo(global_cpu_snapshot), %g1
|
|
|
|
__GET_CPUID(%g2)
|
|
|
|
sllx %g2, 6, %g3
|
|
|
|
add %g1, %g3, %g1
|
|
|
|
|
|
|
|
ldxa [%g0] ASI_PIC, %g7
|
|
|
|
stx %g7, [%g1 + (4 * 8)]
|
|
|
|
mov 0x08, %g3
|
|
|
|
ldxa [%g3] ASI_PIC, %g7
|
|
|
|
stx %g7, [%g1 + (5 * 8)]
|
|
|
|
mov 0x10, %g3
|
|
|
|
ldxa [%g3] ASI_PIC, %g7
|
|
|
|
stx %g7, [%g1 + (6 * 8)]
|
|
|
|
mov 0x18, %g3
|
|
|
|
ldxa [%g3] ASI_PIC, %g7
|
|
|
|
stx %g7, [%g1 + (7 * 8)]
|
|
|
|
|
|
|
|
mov %o0, %g2
|
|
|
|
mov %o1, %g3
|
|
|
|
mov %o5, %g7
|
|
|
|
|
|
|
|
mov HV_FAST_VT_GET_PERFREG, %o5
|
|
|
|
mov 3, %o0
|
|
|
|
ta HV_FAST_TRAP
|
|
|
|
stx %o1, [%g1 + (3 * 8)]
|
|
|
|
mov HV_FAST_VT_GET_PERFREG, %o5
|
|
|
|
mov 2, %o0
|
|
|
|
ta HV_FAST_TRAP
|
|
|
|
stx %o1, [%g1 + (2 * 8)]
|
|
|
|
mov HV_FAST_VT_GET_PERFREG, %o5
|
|
|
|
mov 1, %o0
|
|
|
|
ta HV_FAST_TRAP
|
|
|
|
stx %o1, [%g1 + (1 * 8)]
|
|
|
|
mov HV_FAST_VT_GET_PERFREG, %o5
|
|
|
|
mov 0, %o0
|
|
|
|
ta HV_FAST_TRAP
|
|
|
|
stx %o1, [%g1 + (0 * 8)]
|
|
|
|
|
|
|
|
mov %g2, %o0
|
|
|
|
mov %g3, %o1
|
|
|
|
mov %g7, %o5
|
|
|
|
|
|
|
|
retry
|
|
|
|
|
2016-10-28 00:04:54 +08:00
|
|
|
__cheetah_xcall_flush_tlb_kernel_range: /* 44 insns */
|
|
|
|
sethi %hi(PAGE_SIZE - 1), %g2
|
|
|
|
or %g2, %lo(PAGE_SIZE - 1), %g2
|
|
|
|
andn %g1, %g2, %g1
|
|
|
|
andn %g7, %g2, %g7
|
|
|
|
sub %g7, %g1, %g3
|
|
|
|
srlx %g3, 18, %g2
|
|
|
|
brnz,pn %g2, 2f
|
2019-05-30 05:31:31 +08:00
|
|
|
sethi %hi(PAGE_SIZE), %g2
|
2016-10-28 00:04:54 +08:00
|
|
|
sub %g3, %g2, %g3
|
|
|
|
or %g1, 0x20, %g1 ! Nucleus
|
|
|
|
1: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP
|
|
|
|
stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
brnz,pt %g3, 1b
|
|
|
|
sub %g3, %g2, %g3
|
|
|
|
retry
|
|
|
|
2: mov 0x80, %g2
|
|
|
|
stxa %g0, [%g2] ASI_DMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
stxa %g0, [%g2] ASI_IMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
retry
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
|
|
.align 32
|
|
|
|
.globl xcall_flush_dcache_page_cheetah
|
|
|
|
xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */
|
|
|
|
sethi %hi(PAGE_SIZE), %g3
|
|
|
|
1: subcc %g3, (1 << 5), %g3
|
|
|
|
stxa %g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE
|
|
|
|
membar #Sync
|
|
|
|
bne,pt %icc, 1b
|
|
|
|
nop
|
|
|
|
retry
|
|
|
|
nop
|
|
|
|
#endif /* DCACHE_ALIASING_POSSIBLE */
|
|
|
|
|
|
|
|
.globl xcall_flush_dcache_page_spitfire
|
|
|
|
xcall_flush_dcache_page_spitfire: /* %g1 == physical page address
|
|
|
|
%g7 == kernel page virtual address
|
|
|
|
%g5 == (page->mapping != NULL) */
|
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
|
|
srlx %g1, (13 - 2), %g1 ! Form tag comparitor
|
|
|
|
sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K
|
|
|
|
sub %g3, (1 << 5), %g3 ! D$ linesize == 32
|
|
|
|
1: ldxa [%g3] ASI_DCACHE_TAG, %g2
|
|
|
|
andcc %g2, 0x3, %g0
|
|
|
|
be,pn %xcc, 2f
|
|
|
|
andn %g2, 0x3, %g2
|
|
|
|
cmp %g2, %g1
|
|
|
|
|
|
|
|
bne,pt %xcc, 2f
|
|
|
|
nop
|
|
|
|
stxa %g0, [%g3] ASI_DCACHE_TAG
|
|
|
|
membar #Sync
|
|
|
|
2: cmp %g3, 0
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
sub %g3, (1 << 5), %g3
|
|
|
|
|
|
|
|
brz,pn %g5, 2f
|
|
|
|
#endif /* DCACHE_ALIASING_POSSIBLE */
|
|
|
|
sethi %hi(PAGE_SIZE), %g3
|
|
|
|
|
|
|
|
1: flush %g7
|
|
|
|
subcc %g3, (1 << 5), %g3
|
|
|
|
bne,pt %icc, 1b
|
|
|
|
add %g7, (1 << 5), %g7
|
|
|
|
|
|
|
|
2: retry
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
|
2006-02-27 11:31:49 +08:00
|
|
|
/* %g5: error
|
|
|
|
* %g6: tlb op
|
|
|
|
*/
|
|
|
|
__hypervisor_tlb_xcall_error:
|
|
|
|
mov %g5, %g4
|
|
|
|
mov %g6, %g5
|
|
|
|
ba,pt %xcc, etrap
|
|
|
|
rd %pc, %g7
|
|
|
|
mov %l4, %o0
|
|
|
|
call hypervisor_tlbop_error_xcall
|
|
|
|
mov %l5, %o1
|
2008-04-24 18:15:22 +08:00
|
|
|
ba,a,pt %xcc, rtrap
|
2006-02-27 11:31:49 +08:00
|
|
|
|
2006-02-04 19:08:37 +08:00
|
|
|
.globl __hypervisor_xcall_flush_tlb_mm
|
2016-10-27 01:20:14 +08:00
|
|
|
__hypervisor_xcall_flush_tlb_mm: /* 24 insns */
|
2006-02-04 19:08:37 +08:00
|
|
|
/* %g5=ctx, g1,g2,g3,g4,g7=scratch, %g6=unusable */
|
|
|
|
mov %o0, %g2
|
|
|
|
mov %o1, %g3
|
|
|
|
mov %o2, %g4
|
|
|
|
mov %o3, %g1
|
|
|
|
mov %o5, %g7
|
|
|
|
clr %o0 /* ARG0: CPU lists unimplemented */
|
|
|
|
clr %o1 /* ARG1: CPU lists unimplemented */
|
|
|
|
mov %g5, %o2 /* ARG2: mmu context */
|
|
|
|
mov HV_MMU_ALL, %o3 /* ARG3: flags */
|
|
|
|
mov HV_FAST_MMU_DEMAP_CTX, %o5
|
|
|
|
ta HV_FAST_TRAP
|
2006-02-27 11:31:49 +08:00
|
|
|
mov HV_FAST_MMU_DEMAP_CTX, %g6
|
2016-10-27 01:20:14 +08:00
|
|
|
brnz,pn %o0, 1f
|
2006-02-27 11:31:49 +08:00
|
|
|
mov %o0, %g5
|
2006-02-04 19:08:37 +08:00
|
|
|
mov %g2, %o0
|
|
|
|
mov %g3, %o1
|
|
|
|
mov %g4, %o2
|
|
|
|
mov %g1, %o3
|
|
|
|
mov %g7, %o5
|
|
|
|
membar #Sync
|
|
|
|
retry
|
2016-10-27 01:20:14 +08:00
|
|
|
1: sethi %hi(__hypervisor_tlb_xcall_error), %g4
|
|
|
|
jmpl %g4 + %lo(__hypervisor_tlb_xcall_error), %g0
|
|
|
|
nop
|
2006-02-04 19:08:37 +08:00
|
|
|
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
.globl __hypervisor_xcall_flush_tlb_page
|
2016-10-27 01:20:14 +08:00
|
|
|
__hypervisor_xcall_flush_tlb_page: /* 20 insns */
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
/* %g5=ctx, %g1=vaddr */
|
2006-02-04 19:08:37 +08:00
|
|
|
mov %o0, %g2
|
|
|
|
mov %o1, %g3
|
|
|
|
mov %o2, %g4
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
mov %g1, %o0 /* ARG0: virtual address */
|
2006-02-04 19:08:37 +08:00
|
|
|
mov %g5, %o1 /* ARG1: mmu context */
|
2006-02-27 11:31:49 +08:00
|
|
|
mov HV_MMU_ALL, %o2 /* ARG2: flags */
|
|
|
|
srlx %o0, PAGE_SHIFT, %o0
|
|
|
|
sllx %o0, PAGE_SHIFT, %o0
|
2006-02-04 19:08:37 +08:00
|
|
|
ta HV_MMU_UNMAP_ADDR_TRAP
|
2006-02-27 11:31:49 +08:00
|
|
|
mov HV_MMU_UNMAP_ADDR_TRAP, %g6
|
2016-10-27 01:20:14 +08:00
|
|
|
brnz,a,pn %o0, 1f
|
2006-02-27 11:31:49 +08:00
|
|
|
mov %o0, %g5
|
2006-02-04 19:08:37 +08:00
|
|
|
mov %g2, %o0
|
|
|
|
mov %g3, %o1
|
|
|
|
mov %g4, %o2
|
|
|
|
membar #Sync
|
|
|
|
retry
|
2016-10-27 01:20:14 +08:00
|
|
|
1: sethi %hi(__hypervisor_tlb_xcall_error), %g4
|
|
|
|
jmpl %g4 + %lo(__hypervisor_tlb_xcall_error), %g0
|
|
|
|
nop
|
2006-02-04 19:08:37 +08:00
|
|
|
|
|
|
|
.globl __hypervisor_xcall_flush_tlb_kernel_range
|
2016-10-28 00:04:54 +08:00
|
|
|
__hypervisor_xcall_flush_tlb_kernel_range: /* 44 insns */
|
2006-02-27 11:31:49 +08:00
|
|
|
/* %g1=start, %g7=end, g2,g3,g4,g5,g6=scratch */
|
2006-02-04 19:08:37 +08:00
|
|
|
sethi %hi(PAGE_SIZE - 1), %g2
|
|
|
|
or %g2, %lo(PAGE_SIZE - 1), %g2
|
|
|
|
andn %g1, %g2, %g1
|
|
|
|
andn %g7, %g2, %g7
|
|
|
|
sub %g7, %g1, %g3
|
2016-10-28 00:04:54 +08:00
|
|
|
srlx %g3, 18, %g7
|
2006-02-04 19:08:37 +08:00
|
|
|
add %g2, 1, %g2
|
|
|
|
sub %g3, %g2, %g3
|
|
|
|
mov %o0, %g2
|
|
|
|
mov %o1, %g4
|
2016-10-28 00:04:54 +08:00
|
|
|
brnz,pn %g7, 2f
|
|
|
|
mov %o2, %g7
|
2006-02-04 19:08:37 +08:00
|
|
|
1: add %g1, %g3, %o0 /* ARG0: virtual address */
|
|
|
|
mov 0, %o1 /* ARG1: mmu context */
|
|
|
|
mov HV_MMU_ALL, %o2 /* ARG2: flags */
|
|
|
|
ta HV_MMU_UNMAP_ADDR_TRAP
|
2006-02-27 11:31:49 +08:00
|
|
|
mov HV_MMU_UNMAP_ADDR_TRAP, %g6
|
2016-10-27 01:20:14 +08:00
|
|
|
brnz,pn %o0, 1f
|
2006-02-27 11:31:49 +08:00
|
|
|
mov %o0, %g5
|
2006-02-04 19:08:37 +08:00
|
|
|
sethi %hi(PAGE_SIZE), %o2
|
|
|
|
brnz,pt %g3, 1b
|
|
|
|
sub %g3, %o2, %g3
|
2016-10-28 00:04:54 +08:00
|
|
|
5: mov %g2, %o0
|
2006-02-04 19:08:37 +08:00
|
|
|
mov %g4, %o1
|
2006-02-27 11:31:49 +08:00
|
|
|
mov %g7, %o2
|
2006-02-04 19:08:37 +08:00
|
|
|
membar #Sync
|
|
|
|
retry
|
2016-10-27 01:20:14 +08:00
|
|
|
1: sethi %hi(__hypervisor_tlb_xcall_error), %g4
|
|
|
|
jmpl %g4 + %lo(__hypervisor_tlb_xcall_error), %g0
|
|
|
|
nop
|
2016-10-28 00:04:54 +08:00
|
|
|
2: mov %o3, %g1
|
|
|
|
mov %o5, %g3
|
|
|
|
mov 0, %o0 /* ARG0: CPU lists unimplemented */
|
|
|
|
mov 0, %o1 /* ARG1: CPU lists unimplemented */
|
|
|
|
mov 0, %o2 /* ARG2: mmu context == nucleus */
|
|
|
|
mov HV_MMU_ALL, %o3 /* ARG3: flags */
|
|
|
|
mov HV_FAST_MMU_DEMAP_CTX, %o5
|
|
|
|
ta HV_FAST_TRAP
|
|
|
|
mov %g1, %o3
|
|
|
|
brz,pt %o0, 5b
|
|
|
|
mov %g3, %o5
|
|
|
|
mov HV_FAST_MMU_DEMAP_CTX, %g6
|
|
|
|
ba,pt %xcc, 1b
|
|
|
|
clr %g5
|
2006-02-04 19:08:37 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/* These just get rescheduled to PIL vectors. */
|
|
|
|
.globl xcall_call_function
|
|
|
|
xcall_call_function:
|
|
|
|
wr %g0, (1 << PIL_SMP_CALL_FUNC), %set_softint
|
|
|
|
retry
|
|
|
|
|
2008-07-18 14:44:50 +08:00
|
|
|
.globl xcall_call_function_single
|
|
|
|
xcall_call_function_single:
|
|
|
|
wr %g0, (1 << PIL_SMP_CALL_FUNC_SNGL), %set_softint
|
|
|
|
retry
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
.globl xcall_receive_signal
|
|
|
|
xcall_receive_signal:
|
|
|
|
wr %g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint
|
|
|
|
retry
|
|
|
|
|
|
|
|
.globl xcall_capture
|
|
|
|
xcall_capture:
|
|
|
|
wr %g0, (1 << PIL_SMP_CAPTURE), %set_softint
|
|
|
|
retry
|
|
|
|
|
2008-04-29 17:38:50 +08:00
|
|
|
#ifdef CONFIG_KGDB
|
|
|
|
.globl xcall_kgdb_capture
|
|
|
|
xcall_kgdb_capture:
|
2009-03-19 14:51:57 +08:00
|
|
|
wr %g0, (1 << PIL_KGDB_CAPTURE), %set_softint
|
|
|
|
retry
|
2008-04-29 17:38:50 +08:00
|
|
|
#endif
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#endif /* CONFIG_SMP */
|
2006-02-04 19:08:37 +08:00
|
|
|
|
2016-10-28 00:04:54 +08:00
|
|
|
.globl cheetah_patch_cachetlbops
|
|
|
|
cheetah_patch_cachetlbops:
|
|
|
|
save %sp, -128, %sp
|
|
|
|
|
|
|
|
sethi %hi(__flush_tlb_mm), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_mm), %o0
|
|
|
|
sethi %hi(__cheetah_flush_tlb_mm), %o1
|
|
|
|
or %o1, %lo(__cheetah_flush_tlb_mm), %o1
|
|
|
|
call tlb_patch_one
|
|
|
|
mov 19, %o2
|
|
|
|
|
|
|
|
sethi %hi(__flush_tlb_page), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_page), %o0
|
|
|
|
sethi %hi(__cheetah_flush_tlb_page), %o1
|
|
|
|
or %o1, %lo(__cheetah_flush_tlb_page), %o1
|
|
|
|
call tlb_patch_one
|
|
|
|
mov 22, %o2
|
|
|
|
|
|
|
|
sethi %hi(__flush_tlb_pending), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_pending), %o0
|
|
|
|
sethi %hi(__cheetah_flush_tlb_pending), %o1
|
|
|
|
or %o1, %lo(__cheetah_flush_tlb_pending), %o1
|
|
|
|
call tlb_patch_one
|
|
|
|
mov 27, %o2
|
|
|
|
|
|
|
|
sethi %hi(__flush_tlb_kernel_range), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_kernel_range), %o0
|
|
|
|
sethi %hi(__cheetah_flush_tlb_kernel_range), %o1
|
|
|
|
or %o1, %lo(__cheetah_flush_tlb_kernel_range), %o1
|
|
|
|
call tlb_patch_one
|
|
|
|
mov 31, %o2
|
|
|
|
|
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
|
|
sethi %hi(__flush_dcache_page), %o0
|
|
|
|
or %o0, %lo(__flush_dcache_page), %o0
|
|
|
|
sethi %hi(__cheetah_flush_dcache_page), %o1
|
|
|
|
or %o1, %lo(__cheetah_flush_dcache_page), %o1
|
|
|
|
call tlb_patch_one
|
|
|
|
mov 11, %o2
|
|
|
|
#endif /* DCACHE_ALIASING_POSSIBLE */
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
sethi %hi(xcall_flush_tlb_kernel_range), %o0
|
|
|
|
or %o0, %lo(xcall_flush_tlb_kernel_range), %o0
|
|
|
|
sethi %hi(__cheetah_xcall_flush_tlb_kernel_range), %o1
|
|
|
|
or %o1, %lo(__cheetah_xcall_flush_tlb_kernel_range), %o1
|
|
|
|
call tlb_patch_one
|
|
|
|
mov 44, %o2
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
|
|
|
ret
|
|
|
|
restore
|
2006-02-04 19:08:37 +08:00
|
|
|
|
|
|
|
.globl hypervisor_patch_cachetlbops
|
|
|
|
hypervisor_patch_cachetlbops:
|
|
|
|
save %sp, -128, %sp
|
|
|
|
|
|
|
|
sethi %hi(__flush_tlb_mm), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_mm), %o0
|
|
|
|
sethi %hi(__hypervisor_flush_tlb_mm), %o1
|
|
|
|
or %o1, %lo(__hypervisor_flush_tlb_mm), %o1
|
|
|
|
call tlb_patch_one
|
2016-10-26 07:23:26 +08:00
|
|
|
mov 19, %o2
|
2006-02-04 19:08:37 +08:00
|
|
|
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
sethi %hi(__flush_tlb_page), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_page), %o0
|
|
|
|
sethi %hi(__hypervisor_flush_tlb_page), %o1
|
|
|
|
or %o1, %lo(__hypervisor_flush_tlb_page), %o1
|
|
|
|
call tlb_patch_one
|
2016-10-26 07:23:26 +08:00
|
|
|
mov 22, %o2
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
|
2006-02-04 19:08:37 +08:00
|
|
|
sethi %hi(__flush_tlb_pending), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_pending), %o0
|
|
|
|
sethi %hi(__hypervisor_flush_tlb_pending), %o1
|
|
|
|
or %o1, %lo(__hypervisor_flush_tlb_pending), %o1
|
|
|
|
call tlb_patch_one
|
2016-10-26 07:23:26 +08:00
|
|
|
mov 27, %o2
|
2006-02-04 19:08:37 +08:00
|
|
|
|
|
|
|
sethi %hi(__flush_tlb_kernel_range), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_kernel_range), %o0
|
|
|
|
sethi %hi(__hypervisor_flush_tlb_kernel_range), %o1
|
|
|
|
or %o1, %lo(__hypervisor_flush_tlb_kernel_range), %o1
|
|
|
|
call tlb_patch_one
|
2016-10-28 00:04:54 +08:00
|
|
|
mov 31, %o2
|
2006-02-04 19:08:37 +08:00
|
|
|
|
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
|
|
sethi %hi(__flush_dcache_page), %o0
|
|
|
|
or %o0, %lo(__flush_dcache_page), %o0
|
|
|
|
sethi %hi(__hypervisor_flush_dcache_page), %o1
|
|
|
|
or %o1, %lo(__hypervisor_flush_dcache_page), %o1
|
|
|
|
call tlb_patch_one
|
|
|
|
mov 2, %o2
|
|
|
|
#endif /* DCACHE_ALIASING_POSSIBLE */
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
sethi %hi(xcall_flush_tlb_mm), %o0
|
|
|
|
or %o0, %lo(xcall_flush_tlb_mm), %o0
|
|
|
|
sethi %hi(__hypervisor_xcall_flush_tlb_mm), %o1
|
|
|
|
or %o1, %lo(__hypervisor_xcall_flush_tlb_mm), %o1
|
|
|
|
call tlb_patch_one
|
2016-10-27 01:20:14 +08:00
|
|
|
mov 24, %o2
|
2006-02-04 19:08:37 +08:00
|
|
|
|
sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-20 05:26:26 +08:00
|
|
|
sethi %hi(xcall_flush_tlb_page), %o0
|
|
|
|
or %o0, %lo(xcall_flush_tlb_page), %o0
|
|
|
|
sethi %hi(__hypervisor_xcall_flush_tlb_page), %o1
|
|
|
|
or %o1, %lo(__hypervisor_xcall_flush_tlb_page), %o1
|
2006-02-04 19:08:37 +08:00
|
|
|
call tlb_patch_one
|
2016-10-27 01:20:14 +08:00
|
|
|
mov 20, %o2
|
2006-02-04 19:08:37 +08:00
|
|
|
|
|
|
|
sethi %hi(xcall_flush_tlb_kernel_range), %o0
|
|
|
|
or %o0, %lo(xcall_flush_tlb_kernel_range), %o0
|
|
|
|
sethi %hi(__hypervisor_xcall_flush_tlb_kernel_range), %o1
|
|
|
|
or %o1, %lo(__hypervisor_xcall_flush_tlb_kernel_range), %o1
|
|
|
|
call tlb_patch_one
|
2016-10-28 00:04:54 +08:00
|
|
|
mov 44, %o2
|
2006-02-04 19:08:37 +08:00
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
|
|
|
ret
|
|
|
|
restore
|