linux/drivers/gpu/drm/nouveau/dispnv50/crcc57d.c

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drm/nouveau/kms/nv140-: Use hard-coded wndws or core channel for CRC channel Originally it was assumed based on Nvidia's open-gpu-docs and testing that NVDisplay required that at least one wndw which belongs to a given head to be used as the controlling channel (NVC37D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL) in order for CRC capture to function. While this is the case on Volta, Turing actually adds the ability to instead use the core channel as the controlling channel. For Turing this is quite useful, as it means that we can always default to the core channel as the controlling channel and we don't need to be concerned about ensuring we have at least one wndw channel owned by a head with CRC output enabled. While Volta lacks this ability, Volta conveniently also lacks flexible wndw mapping - meaning that we can always rely on each head having four wndw channels mapped to it regardless of the atomic state. So, simply use the hard-coded wndw mappings we're guaranteed to have on Volta as the controlling channel, and use the core channel as the controlling channel for Turing+. As a result this also renders the plane ownership logic in nv50_crc_atomic_check() unnessecary, which gives us one less thing to implement when we get support for flexible wndw mapping. We also can entirely drop the wndw parameter from our set_src callbacks, and the atomic state. v2 (Karol): put prackets around complex macro definition removed spaces before :32 in structs Cc: Martin Peres <martin.peres@free.fr> Cc: Jeremy Cline <jcline@redhat.com> Cc: Simon Ser <contact@emersion.fr> Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Karol Herbst <kherbst@redhat.com> Signed-off-by: Karol Herbst <kherbst@redhat.com> Link: https://gitlab.freedesktop.org/drm/nouveau/-/merge_requests/10
2021-01-19 09:48:47 +08:00
// SPDX-License-Identifier: MIT
#include "crc.h"
#include "crcc37d.h"
#include "core.h"
#include "disp.h"
#include "head.h"
#include <nvif/pushc37b.h>
#include <nvhw/class/clc57d.h>
static int crcc57d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source,
struct nv50_crc_notifier_ctx *ctx)
{
struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
const int i = head->base.index;
u32 crc_args = NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |
NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |
NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) |
NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE);
int ret;
switch (source) {
case NV50_CRC_SOURCE_TYPE_SOR:
crc_args |= NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SOR(or));
break;
case NV50_CRC_SOURCE_TYPE_SF:
crc_args |= NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SF);
break;
default:
break;
}
ret = PUSH_WAIT(push, 4);
if (ret)
return ret;
if (source) {
PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), crc_args);
} else {
PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), 0);
PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
}
return 0;
}
const struct nv50_crc_func crcc57d = {
.set_src = crcc57d_set_src,
.set_ctx = crcc37d_set_ctx,
.get_entry = crcc37d_get_entry,
.ctx_finished = crcc37d_ctx_finished,
.flip_threshold = CRCC37D_FLIP_THRESHOLD,
.num_entries = CRCC37D_MAX_ENTRIES,
.notifier_len = sizeof(struct crcc37d_notifier),
};