2019-05-27 14:55:01 +08:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2016-06-27 01:37:05 +08:00
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/*
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* Common Performance counter support functions for PowerISA v2.07 processors.
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*
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* Copyright 2009 Paul Mackerras, IBM Corporation.
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* Copyright 2013 Michael Ellerman, IBM Corporation.
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* Copyright 2016 Madhavan Srinivasan, IBM Corporation.
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*/
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#include "isa207-common.h"
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2016-12-02 08:34:59 +08:00
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PMU_FORMAT_ATTR(event, "config:0-49");
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PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
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PMU_FORMAT_ATTR(mark, "config:8");
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PMU_FORMAT_ATTR(combine, "config:11");
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PMU_FORMAT_ATTR(unit, "config:12-15");
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PMU_FORMAT_ATTR(pmc, "config:16-19");
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PMU_FORMAT_ATTR(cache_sel, "config:20-23");
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PMU_FORMAT_ATTR(sample_mode, "config:24-28");
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PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
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PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
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PMU_FORMAT_ATTR(thresh_start, "config:36-39");
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PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
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2021-04-09 17:01:19 +08:00
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static struct attribute *isa207_pmu_format_attr[] = {
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2016-12-02 08:34:59 +08:00
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&format_attr_event.attr,
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&format_attr_pmcxsel.attr,
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&format_attr_mark.attr,
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&format_attr_combine.attr,
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&format_attr_unit.attr,
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&format_attr_pmc.attr,
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&format_attr_cache_sel.attr,
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&format_attr_sample_mode.attr,
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&format_attr_thresh_sel.attr,
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&format_attr_thresh_stop.attr,
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&format_attr_thresh_start.attr,
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&format_attr_thresh_cmp.attr,
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NULL,
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};
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2022-03-08 07:14:14 +08:00
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const struct attribute_group isa207_pmu_format_group = {
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2016-12-02 08:34:59 +08:00
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.name = "format",
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.attrs = isa207_pmu_format_attr,
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};
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2016-06-27 01:37:05 +08:00
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static inline bool event_is_fab_match(u64 event)
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{
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/* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
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event &= 0xff0fe;
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/* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */
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return (event == 0x30056 || event == 0x4f052);
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}
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2016-12-02 08:35:02 +08:00
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static bool is_event_valid(u64 event)
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{
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u64 valid_mask = EVENT_VALID_MASK;
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2020-07-17 22:38:20 +08:00
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if (cpu_has_feature(CPU_FTR_ARCH_31))
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valid_mask = p10_EVENT_VALID_MASK;
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else if (cpu_has_feature(CPU_FTR_ARCH_300))
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2016-12-02 08:35:02 +08:00
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valid_mask = p9_EVENT_VALID_MASK;
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return !(event & ~valid_mask);
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}
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2017-02-20 21:59:03 +08:00
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static inline bool is_event_marked(u64 event)
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2016-12-02 08:35:02 +08:00
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{
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2017-02-20 21:59:03 +08:00
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if (event & EVENT_IS_MARKED)
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return true;
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return false;
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}
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2016-12-02 08:35:02 +08:00
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2020-07-17 22:38:20 +08:00
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static unsigned long sdar_mod_val(u64 event)
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{
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if (cpu_has_feature(CPU_FTR_ARCH_31))
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return p10_SDAR_MODE(event);
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return p9_SDAR_MODE(event);
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}
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2017-02-20 21:59:03 +08:00
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static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
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{
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/*
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2022-05-01 02:56:54 +08:00
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* MMCRA[SDAR_MODE] specifies how the SDAR should be updated in
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* continuous sampling mode.
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2017-02-20 21:59:03 +08:00
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*
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* Incase of Power8:
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2022-05-01 02:56:54 +08:00
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* MMCRA[SDAR_MODE] will be programmed as "0b01" for continuous sampling
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2017-02-20 21:59:03 +08:00
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* mode and will be un-changed when setting MMCRA[63] (Marked events).
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*
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2020-07-17 22:38:20 +08:00
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* Incase of Power9/power10:
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2017-02-20 21:59:03 +08:00
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* Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'),
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* or if group already have any marked events.
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* For rest
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* MMCRA[SDAR_MODE] will be set from event code.
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2017-07-11 18:57:49 +08:00
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* If sdar_mode from event is zero, default to 0b01. Hardware
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* requires that we set a non-zero value.
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2017-02-20 21:59:03 +08:00
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*/
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if (cpu_has_feature(CPU_FTR_ARCH_300)) {
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if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
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*mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
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2020-07-17 22:38:20 +08:00
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else if (sdar_mod_val(event))
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*mmcra |= sdar_mod_val(event) << MMCRA_SDAR_MODE_SHIFT;
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2017-07-11 18:57:49 +08:00
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else
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2017-07-25 13:35:51 +08:00
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*mmcra |= MMCRA_SDAR_MODE_DCACHE;
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2017-02-20 21:59:03 +08:00
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} else
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*mmcra |= MMCRA_SDAR_MODE_TLB;
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2016-12-02 08:35:02 +08:00
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}
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2022-05-06 14:10:14 +08:00
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static int p10_thresh_cmp_val(u64 value)
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powerpc/perf: Adds support for programming of Thresholding in P10
Thresholding, a performance monitoring unit feature, can be
used to identify marked instructions which take more than
expected cycles between start event and end event.
Threshold compare (thresh_cmp) bits are programmed in MMCRA
register. In Power9, thresh_cmp bits were part of the
event code. But in case of P10, thresh_cmp are not part of
event code due to inclusion of MMCR3 bits.
Patch here adds an option to use attr.config1 variable
to be used to pass thresh_cmp value to be programmed in
MMCRA register. A new ppmu flag called PPMU_HAS_ATTR_CONFIG1
has been added and this flag is used to notify the use of
attr.config1 variable.
Patch has extended the parameter list of 'compute_mmcr',
to include power_pmu's 'flags' element and parameter list of
get_constraint to include attr.config1 value. It also extend
parameter list of power_check_constraints inorder to pass
perf_event list.
As stated by commit ef0e3b650f8d ("powerpc/perf: Fix Threshold
Event Counter Multiplier width for P10"), constraint bits for
thresh_cmp is also needed to be increased to 11 bits, which is
handled as part of this patch. We added bit number 53 as part
of constraint bits of thresh_cmp for power10 to make it an
11 bit field.
Updated layout for p10:
/*
* Layout of constraint bits:
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
* | |
* [ thresh_cmp bits for p10] thresh_sel -*
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
* | | | | |
* BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
* EBB -* | | p1, p2, p3, p4, p5, p6.
* L1 I/D qualifier -* |
* nc - number of counters -*
*
* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
* we want the low bit of each field to be added to any existing value.
*
* Everything else is a value field.
*/
Result:
command#: cat /sys/devices/cpu/format/thresh_cmp
config1:0-17
ex. usage:
command#: perf record -I --weight -d -e
cpu/event=0x67340101EC,thresh_cmp=500/ ./ebizzy -S 2 -t 1 -s 4096
1826636 records/s
real 2.00 s
user 2.00 s
sys 0.00 s
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.038 MB perf.data (61 samples) ]
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210209095234.837356-1-kjain@linux.ibm.com
2021-02-09 17:52:34 +08:00
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{
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int exp = 0;
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u64 result = value;
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if (!value)
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return value;
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/*
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* Incase of P10, thresh_cmp value is not part of raw event code
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* and provided via attr.config1 parameter. To program threshold in MMCRA,
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* take a 18 bit number N and shift right 2 places and increment
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* the exponent E by 1 until the upper 10 bits of N are zero.
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* Write E to the threshold exponent and write the lower 8 bits of N
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* to the threshold mantissa.
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* The max threshold that can be written is 261120.
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*/
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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if (value > 261120)
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value = 261120;
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while ((64 - __builtin_clzl(value)) > 8) {
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exp++;
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value >>= 2;
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}
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/*
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* Note that it is invalid to write a mantissa with the
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* upper 2 bits of mantissa being zero, unless the
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* exponent is also zero.
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*/
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if (!(value & 0xC0) && exp)
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2022-05-06 14:10:14 +08:00
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result = -1;
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powerpc/perf: Adds support for programming of Thresholding in P10
Thresholding, a performance monitoring unit feature, can be
used to identify marked instructions which take more than
expected cycles between start event and end event.
Threshold compare (thresh_cmp) bits are programmed in MMCRA
register. In Power9, thresh_cmp bits were part of the
event code. But in case of P10, thresh_cmp are not part of
event code due to inclusion of MMCR3 bits.
Patch here adds an option to use attr.config1 variable
to be used to pass thresh_cmp value to be programmed in
MMCRA register. A new ppmu flag called PPMU_HAS_ATTR_CONFIG1
has been added and this flag is used to notify the use of
attr.config1 variable.
Patch has extended the parameter list of 'compute_mmcr',
to include power_pmu's 'flags' element and parameter list of
get_constraint to include attr.config1 value. It also extend
parameter list of power_check_constraints inorder to pass
perf_event list.
As stated by commit ef0e3b650f8d ("powerpc/perf: Fix Threshold
Event Counter Multiplier width for P10"), constraint bits for
thresh_cmp is also needed to be increased to 11 bits, which is
handled as part of this patch. We added bit number 53 as part
of constraint bits of thresh_cmp for power10 to make it an
11 bit field.
Updated layout for p10:
/*
* Layout of constraint bits:
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
* | |
* [ thresh_cmp bits for p10] thresh_sel -*
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
* | | | | |
* BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
* EBB -* | | p1, p2, p3, p4, p5, p6.
* L1 I/D qualifier -* |
* nc - number of counters -*
*
* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
* we want the low bit of each field to be added to any existing value.
*
* Everything else is a value field.
*/
Result:
command#: cat /sys/devices/cpu/format/thresh_cmp
config1:0-17
ex. usage:
command#: perf record -I --weight -d -e
cpu/event=0x67340101EC,thresh_cmp=500/ ./ebizzy -S 2 -t 1 -s 4096
1826636 records/s
real 2.00 s
user 2.00 s
sys 0.00 s
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.038 MB perf.data (61 samples) ]
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210209095234.837356-1-kjain@linux.ibm.com
2021-02-09 17:52:34 +08:00
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else
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result = (exp << 8) | value;
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}
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return result;
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}
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2016-12-02 08:35:02 +08:00
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static u64 thresh_cmp_val(u64 value)
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{
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powerpc/perf: Adds support for programming of Thresholding in P10
Thresholding, a performance monitoring unit feature, can be
used to identify marked instructions which take more than
expected cycles between start event and end event.
Threshold compare (thresh_cmp) bits are programmed in MMCRA
register. In Power9, thresh_cmp bits were part of the
event code. But in case of P10, thresh_cmp are not part of
event code due to inclusion of MMCR3 bits.
Patch here adds an option to use attr.config1 variable
to be used to pass thresh_cmp value to be programmed in
MMCRA register. A new ppmu flag called PPMU_HAS_ATTR_CONFIG1
has been added and this flag is used to notify the use of
attr.config1 variable.
Patch has extended the parameter list of 'compute_mmcr',
to include power_pmu's 'flags' element and parameter list of
get_constraint to include attr.config1 value. It also extend
parameter list of power_check_constraints inorder to pass
perf_event list.
As stated by commit ef0e3b650f8d ("powerpc/perf: Fix Threshold
Event Counter Multiplier width for P10"), constraint bits for
thresh_cmp is also needed to be increased to 11 bits, which is
handled as part of this patch. We added bit number 53 as part
of constraint bits of thresh_cmp for power10 to make it an
11 bit field.
Updated layout for p10:
/*
* Layout of constraint bits:
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
* | |
* [ thresh_cmp bits for p10] thresh_sel -*
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
* | | | | |
* BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
* EBB -* | | p1, p2, p3, p4, p5, p6.
* L1 I/D qualifier -* |
* nc - number of counters -*
*
* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
* we want the low bit of each field to be added to any existing value.
*
* Everything else is a value field.
*/
Result:
command#: cat /sys/devices/cpu/format/thresh_cmp
config1:0-17
ex. usage:
command#: perf record -I --weight -d -e
cpu/event=0x67340101EC,thresh_cmp=500/ ./ebizzy -S 2 -t 1 -s 4096
1826636 records/s
real 2.00 s
user 2.00 s
sys 0.00 s
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.038 MB perf.data (61 samples) ]
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210209095234.837356-1-kjain@linux.ibm.com
2021-02-09 17:52:34 +08:00
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if (cpu_has_feature(CPU_FTR_ARCH_31))
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value = p10_thresh_cmp_val(value);
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/*
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* Since location of threshold compare bits in MMCRA
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* is different for p8, using different shift value.
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*/
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2018-07-05 16:47:00 +08:00
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if (cpu_has_feature(CPU_FTR_ARCH_300))
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2016-12-02 08:35:02 +08:00
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return value << p9_MMCRA_THR_CMP_SHIFT;
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powerpc/perf: Adds support for programming of Thresholding in P10
Thresholding, a performance monitoring unit feature, can be
used to identify marked instructions which take more than
expected cycles between start event and end event.
Threshold compare (thresh_cmp) bits are programmed in MMCRA
register. In Power9, thresh_cmp bits were part of the
event code. But in case of P10, thresh_cmp are not part of
event code due to inclusion of MMCR3 bits.
Patch here adds an option to use attr.config1 variable
to be used to pass thresh_cmp value to be programmed in
MMCRA register. A new ppmu flag called PPMU_HAS_ATTR_CONFIG1
has been added and this flag is used to notify the use of
attr.config1 variable.
Patch has extended the parameter list of 'compute_mmcr',
to include power_pmu's 'flags' element and parameter list of
get_constraint to include attr.config1 value. It also extend
parameter list of power_check_constraints inorder to pass
perf_event list.
As stated by commit ef0e3b650f8d ("powerpc/perf: Fix Threshold
Event Counter Multiplier width for P10"), constraint bits for
thresh_cmp is also needed to be increased to 11 bits, which is
handled as part of this patch. We added bit number 53 as part
of constraint bits of thresh_cmp for power10 to make it an
11 bit field.
Updated layout for p10:
/*
* Layout of constraint bits:
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
* | |
* [ thresh_cmp bits for p10] thresh_sel -*
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
* | | | | |
* BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
* EBB -* | | p1, p2, p3, p4, p5, p6.
* L1 I/D qualifier -* |
* nc - number of counters -*
*
* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
* we want the low bit of each field to be added to any existing value.
*
* Everything else is a value field.
*/
Result:
command#: cat /sys/devices/cpu/format/thresh_cmp
config1:0-17
ex. usage:
command#: perf record -I --weight -d -e
cpu/event=0x67340101EC,thresh_cmp=500/ ./ebizzy -S 2 -t 1 -s 4096
1826636 records/s
real 2.00 s
user 2.00 s
sys 0.00 s
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.038 MB perf.data (61 samples) ]
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210209095234.837356-1-kjain@linux.ibm.com
2021-02-09 17:52:34 +08:00
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else
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return value << MMCRA_THR_CMP_SHIFT;
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2016-12-02 08:35:02 +08:00
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}
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|
|
static unsigned long combine_from_event(u64 event)
|
|
|
|
{
|
2018-07-05 16:47:00 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_300))
|
2016-12-02 08:35:02 +08:00
|
|
|
return p9_EVENT_COMBINE(event);
|
|
|
|
|
|
|
|
return EVENT_COMBINE(event);
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned long combine_shift(unsigned long pmc)
|
|
|
|
{
|
2018-07-05 16:47:00 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_300))
|
2016-12-02 08:35:02 +08:00
|
|
|
return p9_MMCR1_COMBINE_SHIFT(pmc);
|
|
|
|
|
|
|
|
return MMCR1_COMBINE_SHIFT(pmc);
|
|
|
|
}
|
|
|
|
|
2017-02-13 19:32:54 +08:00
|
|
|
static inline bool event_is_threshold(u64 event)
|
|
|
|
{
|
|
|
|
return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool is_thresh_cmp_valid(u64 event)
|
|
|
|
{
|
|
|
|
unsigned int cmp, exp;
|
|
|
|
|
powerpc/perf: Adds support for programming of Thresholding in P10
Thresholding, a performance monitoring unit feature, can be
used to identify marked instructions which take more than
expected cycles between start event and end event.
Threshold compare (thresh_cmp) bits are programmed in MMCRA
register. In Power9, thresh_cmp bits were part of the
event code. But in case of P10, thresh_cmp are not part of
event code due to inclusion of MMCR3 bits.
Patch here adds an option to use attr.config1 variable
to be used to pass thresh_cmp value to be programmed in
MMCRA register. A new ppmu flag called PPMU_HAS_ATTR_CONFIG1
has been added and this flag is used to notify the use of
attr.config1 variable.
Patch has extended the parameter list of 'compute_mmcr',
to include power_pmu's 'flags' element and parameter list of
get_constraint to include attr.config1 value. It also extend
parameter list of power_check_constraints inorder to pass
perf_event list.
As stated by commit ef0e3b650f8d ("powerpc/perf: Fix Threshold
Event Counter Multiplier width for P10"), constraint bits for
thresh_cmp is also needed to be increased to 11 bits, which is
handled as part of this patch. We added bit number 53 as part
of constraint bits of thresh_cmp for power10 to make it an
11 bit field.
Updated layout for p10:
/*
* Layout of constraint bits:
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
* | |
* [ thresh_cmp bits for p10] thresh_sel -*
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
* | | | | |
* BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
* EBB -* | | p1, p2, p3, p4, p5, p6.
* L1 I/D qualifier -* |
* nc - number of counters -*
*
* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
* we want the low bit of each field to be added to any existing value.
*
* Everything else is a value field.
*/
Result:
command#: cat /sys/devices/cpu/format/thresh_cmp
config1:0-17
ex. usage:
command#: perf record -I --weight -d -e
cpu/event=0x67340101EC,thresh_cmp=500/ ./ebizzy -S 2 -t 1 -s 4096
1826636 records/s
real 2.00 s
user 2.00 s
sys 0.00 s
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.038 MB perf.data (61 samples) ]
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210209095234.837356-1-kjain@linux.ibm.com
2021-02-09 17:52:34 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31))
|
2022-05-06 14:10:14 +08:00
|
|
|
return p10_thresh_cmp_val(event) >= 0;
|
powerpc/perf: Adds support for programming of Thresholding in P10
Thresholding, a performance monitoring unit feature, can be
used to identify marked instructions which take more than
expected cycles between start event and end event.
Threshold compare (thresh_cmp) bits are programmed in MMCRA
register. In Power9, thresh_cmp bits were part of the
event code. But in case of P10, thresh_cmp are not part of
event code due to inclusion of MMCR3 bits.
Patch here adds an option to use attr.config1 variable
to be used to pass thresh_cmp value to be programmed in
MMCRA register. A new ppmu flag called PPMU_HAS_ATTR_CONFIG1
has been added and this flag is used to notify the use of
attr.config1 variable.
Patch has extended the parameter list of 'compute_mmcr',
to include power_pmu's 'flags' element and parameter list of
get_constraint to include attr.config1 value. It also extend
parameter list of power_check_constraints inorder to pass
perf_event list.
As stated by commit ef0e3b650f8d ("powerpc/perf: Fix Threshold
Event Counter Multiplier width for P10"), constraint bits for
thresh_cmp is also needed to be increased to 11 bits, which is
handled as part of this patch. We added bit number 53 as part
of constraint bits of thresh_cmp for power10 to make it an
11 bit field.
Updated layout for p10:
/*
* Layout of constraint bits:
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
* | |
* [ thresh_cmp bits for p10] thresh_sel -*
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
* | | | | |
* BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
* EBB -* | | p1, p2, p3, p4, p5, p6.
* L1 I/D qualifier -* |
* nc - number of counters -*
*
* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
* we want the low bit of each field to be added to any existing value.
*
* Everything else is a value field.
*/
Result:
command#: cat /sys/devices/cpu/format/thresh_cmp
config1:0-17
ex. usage:
command#: perf record -I --weight -d -e
cpu/event=0x67340101EC,thresh_cmp=500/ ./ebizzy -S 2 -t 1 -s 4096
1826636 records/s
real 2.00 s
user 2.00 s
sys 0.00 s
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.038 MB perf.data (61 samples) ]
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210209095234.837356-1-kjain@linux.ibm.com
2021-02-09 17:52:34 +08:00
|
|
|
|
2017-02-13 19:32:54 +08:00
|
|
|
/*
|
|
|
|
* Check the mantissa upper two bits are not zero, unless the
|
|
|
|
* exponent is also zero. See the THRESH_CMP_MANTISSA doc.
|
|
|
|
*/
|
2020-07-17 22:38:20 +08:00
|
|
|
|
2017-02-13 19:32:54 +08:00
|
|
|
cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
|
|
|
|
exp = cmp >> 7;
|
|
|
|
|
|
|
|
if (exp && (cmp & 0x60) == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-10-09 22:12:40 +08:00
|
|
|
static unsigned int dc_ic_rld_quad_l1_sel(u64 event)
|
|
|
|
{
|
|
|
|
unsigned int cache;
|
|
|
|
|
|
|
|
cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK;
|
|
|
|
return cache;
|
|
|
|
}
|
|
|
|
|
2017-04-11 09:51:06 +08:00
|
|
|
static inline u64 isa207_find_source(u64 idx, u32 sub_idx)
|
|
|
|
{
|
|
|
|
u64 ret = PERF_MEM_NA;
|
|
|
|
|
|
|
|
switch(idx) {
|
|
|
|
case 0:
|
|
|
|
/* Nothing to do */
|
|
|
|
break;
|
|
|
|
case 1:
|
powerpc/perf: Add encodings to represent data based on newer composite PERF_MEM_LVLNUM* fields
The code represent data coming from L1/L2/L3 cache hits based on
PERF_MEM_LVL_* namespace, which is in the process of deprecation in
the favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_,HOPS_}
fields.
Add data source encodings to represent L1/L2/L3 cache hits based on
newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_,HOPS_} fields for
power10 and older platforms
Result in power9 system without patch changes:
localhost:# ./perf mem report --sort="mem,sym,dso" --stdio
# Overhead Samples Memory access Symbol Shared Object
# ........ ............ ........................ ................................. ................
#
29.51% 1 L2 hit [k] perf_event_exec [kernel.vmlinux]
27.05% 1 L1 hit [k] perf_ctx_unlock [kernel.vmlinux]
13.93% 1 L1 hit [k] vtime_delta [kernel.vmlinux]
13.11% 1 L1 hit [k] prepend_path.isra.11 [kernel.vmlinux]
8.20% 1 L1 hit [.] 00000038.plt_call.__GI_strlen libc-2.28.so
8.20% 1 L1 hit [k] perf_event_interrupt [kernel.vmlinux]
Result in power9 system with patch changes:
localhost:# ./perf mem report --sort="mem,sym,dso" --stdio
# Overhead Samples Memory access Symbol Shared Object
# ........ ............ ........................ .......................... ................
#
36.63% 1 L2 or L2 hit [k] perf_event_exec [kernel.vmlinux]
25.50% 1 L1 or L1 hit [k] vtime_delta [kernel.vmlinux]
13.12% 1 L1 or L1 hit [k] unmap_region [kernel.vmlinux]
12.62% 1 L1 or L1 hit [k] perf_sample_event_took [kernel.vmlinux]
6.93% 1 L1 or L1 hit [k] perf_ctx_unlock [kernel.vmlinux]
5.20% 1 L1 or L1 hit [.] __memcpy_power7 libc-2.28.so
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Reviewed-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211206091749.87585-4-kjain@linux.ibm.com
2021-12-06 17:17:48 +08:00
|
|
|
ret = PH(LVL, L1) | LEVEL(L1) | P(SNOOP, HIT);
|
2017-04-11 09:51:06 +08:00
|
|
|
break;
|
|
|
|
case 2:
|
powerpc/perf: Add encodings to represent data based on newer composite PERF_MEM_LVLNUM* fields
The code represent data coming from L1/L2/L3 cache hits based on
PERF_MEM_LVL_* namespace, which is in the process of deprecation in
the favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_,HOPS_}
fields.
Add data source encodings to represent L1/L2/L3 cache hits based on
newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_,HOPS_} fields for
power10 and older platforms
Result in power9 system without patch changes:
localhost:# ./perf mem report --sort="mem,sym,dso" --stdio
# Overhead Samples Memory access Symbol Shared Object
# ........ ............ ........................ ................................. ................
#
29.51% 1 L2 hit [k] perf_event_exec [kernel.vmlinux]
27.05% 1 L1 hit [k] perf_ctx_unlock [kernel.vmlinux]
13.93% 1 L1 hit [k] vtime_delta [kernel.vmlinux]
13.11% 1 L1 hit [k] prepend_path.isra.11 [kernel.vmlinux]
8.20% 1 L1 hit [.] 00000038.plt_call.__GI_strlen libc-2.28.so
8.20% 1 L1 hit [k] perf_event_interrupt [kernel.vmlinux]
Result in power9 system with patch changes:
localhost:# ./perf mem report --sort="mem,sym,dso" --stdio
# Overhead Samples Memory access Symbol Shared Object
# ........ ............ ........................ .......................... ................
#
36.63% 1 L2 or L2 hit [k] perf_event_exec [kernel.vmlinux]
25.50% 1 L1 or L1 hit [k] vtime_delta [kernel.vmlinux]
13.12% 1 L1 or L1 hit [k] unmap_region [kernel.vmlinux]
12.62% 1 L1 or L1 hit [k] perf_sample_event_took [kernel.vmlinux]
6.93% 1 L1 or L1 hit [k] perf_ctx_unlock [kernel.vmlinux]
5.20% 1 L1 or L1 hit [.] __memcpy_power7 libc-2.28.so
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Reviewed-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211206091749.87585-4-kjain@linux.ibm.com
2021-12-06 17:17:48 +08:00
|
|
|
ret = PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT);
|
2017-04-11 09:51:06 +08:00
|
|
|
break;
|
|
|
|
case 3:
|
powerpc/perf: Add encodings to represent data based on newer composite PERF_MEM_LVLNUM* fields
The code represent data coming from L1/L2/L3 cache hits based on
PERF_MEM_LVL_* namespace, which is in the process of deprecation in
the favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_,HOPS_}
fields.
Add data source encodings to represent L1/L2/L3 cache hits based on
newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_,HOPS_} fields for
power10 and older platforms
Result in power9 system without patch changes:
localhost:# ./perf mem report --sort="mem,sym,dso" --stdio
# Overhead Samples Memory access Symbol Shared Object
# ........ ............ ........................ ................................. ................
#
29.51% 1 L2 hit [k] perf_event_exec [kernel.vmlinux]
27.05% 1 L1 hit [k] perf_ctx_unlock [kernel.vmlinux]
13.93% 1 L1 hit [k] vtime_delta [kernel.vmlinux]
13.11% 1 L1 hit [k] prepend_path.isra.11 [kernel.vmlinux]
8.20% 1 L1 hit [.] 00000038.plt_call.__GI_strlen libc-2.28.so
8.20% 1 L1 hit [k] perf_event_interrupt [kernel.vmlinux]
Result in power9 system with patch changes:
localhost:# ./perf mem report --sort="mem,sym,dso" --stdio
# Overhead Samples Memory access Symbol Shared Object
# ........ ............ ........................ .......................... ................
#
36.63% 1 L2 or L2 hit [k] perf_event_exec [kernel.vmlinux]
25.50% 1 L1 or L1 hit [k] vtime_delta [kernel.vmlinux]
13.12% 1 L1 or L1 hit [k] unmap_region [kernel.vmlinux]
12.62% 1 L1 or L1 hit [k] perf_sample_event_took [kernel.vmlinux]
6.93% 1 L1 or L1 hit [k] perf_ctx_unlock [kernel.vmlinux]
5.20% 1 L1 or L1 hit [.] __memcpy_power7 libc-2.28.so
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Reviewed-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211206091749.87585-4-kjain@linux.ibm.com
2021-12-06 17:17:48 +08:00
|
|
|
ret = PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
|
2017-04-11 09:51:06 +08:00
|
|
|
break;
|
|
|
|
case 4:
|
powerpc/perf: Add data source encodings for power10 platform
The code represent memory/cache level data based on PERF_MEM_LVL_*
namespace, which is in the process of deprication in the favour of
newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_,HOPS_} fields.
Add data source encodings to represent cache/memory data based on
newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_,HOPS_} fields.
Add data source encodings to represent data coming from local
memory/Remote memory/distant memory and remote/distant cache hits.
In order to represent data coming from OpenCAPI cache/memory, we use
LVLNUM "PMEM" field which is used to present persistent memory accesses.
Result in power10 system with patch changes:
localhost:# ./perf mem report --sort="mem,sym,dso" --stdio
# Overhead Samples Memory access Symbol Shared Object
# ........ ............ ........................ .......................... ................
#
29.46% 2331 L1 or L1 hit [.] __random libc-2.28.so
23.11% 2121 L1 or L1 hit [.] producer_populate_cache producer_consumer
18.56% 1758 L1 or L1 hit [.] __random_r libc-2.28.so
15.64% 1559 L2 or L2 hit [.] __random libc-2.28.so
.....
0.09% 5 Remote socket, same board Any cache hit [.] __random libc-2.28.so
0.07% 4 Remote socket, same board Any cache hit [.] __random libc-2.28.so
.....
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Reviewed-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211206091749.87585-5-kjain@linux.ibm.com
2021-12-06 17:17:49 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
|
|
|
ret = P(SNOOP, HIT);
|
|
|
|
|
|
|
|
if (sub_idx == 1)
|
|
|
|
ret |= PH(LVL, LOC_RAM) | LEVEL(RAM);
|
|
|
|
else if (sub_idx == 2 || sub_idx == 3)
|
|
|
|
ret |= P(LVL, HIT) | LEVEL(PMEM);
|
|
|
|
else if (sub_idx == 4)
|
|
|
|
ret |= PH(LVL, REM_RAM1) | REM | LEVEL(RAM) | P(HOPS, 2);
|
|
|
|
else if (sub_idx == 5 || sub_idx == 7)
|
|
|
|
ret |= P(LVL, HIT) | LEVEL(PMEM) | REM;
|
|
|
|
else if (sub_idx == 6)
|
|
|
|
ret |= PH(LVL, REM_RAM2) | REM | LEVEL(RAM) | P(HOPS, 3);
|
|
|
|
} else {
|
|
|
|
if (sub_idx <= 1)
|
|
|
|
ret = PH(LVL, LOC_RAM);
|
|
|
|
else if (sub_idx > 1 && sub_idx <= 2)
|
|
|
|
ret = PH(LVL, REM_RAM1);
|
|
|
|
else
|
|
|
|
ret = PH(LVL, REM_RAM2);
|
|
|
|
ret |= P(SNOOP, HIT);
|
|
|
|
}
|
2017-04-11 09:51:06 +08:00
|
|
|
break;
|
|
|
|
case 5:
|
2021-10-06 22:06:54 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
|
|
|
ret = REM | P(HOPS, 0);
|
|
|
|
|
|
|
|
if (sub_idx == 0 || sub_idx == 4)
|
|
|
|
ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT);
|
|
|
|
else if (sub_idx == 1 || sub_idx == 5)
|
|
|
|
ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM);
|
|
|
|
else if (sub_idx == 2 || sub_idx == 6)
|
|
|
|
ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
|
|
|
|
else if (sub_idx == 3 || sub_idx == 7)
|
|
|
|
ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
|
|
|
|
} else {
|
|
|
|
if (sub_idx == 0)
|
|
|
|
ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0);
|
|
|
|
else if (sub_idx == 1)
|
|
|
|
ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0);
|
|
|
|
else if (sub_idx == 2 || sub_idx == 4)
|
|
|
|
ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HIT) | P(HOPS, 0);
|
|
|
|
else if (sub_idx == 3 || sub_idx == 5)
|
|
|
|
ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HITM) | P(HOPS, 0);
|
|
|
|
}
|
2017-04-11 09:51:06 +08:00
|
|
|
break;
|
|
|
|
case 6:
|
powerpc/perf: Add data source encodings for power10 platform
The code represent memory/cache level data based on PERF_MEM_LVL_*
namespace, which is in the process of deprication in the favour of
newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_,HOPS_} fields.
Add data source encodings to represent cache/memory data based on
newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_,HOPS_} fields.
Add data source encodings to represent data coming from local
memory/Remote memory/distant memory and remote/distant cache hits.
In order to represent data coming from OpenCAPI cache/memory, we use
LVLNUM "PMEM" field which is used to present persistent memory accesses.
Result in power10 system with patch changes:
localhost:# ./perf mem report --sort="mem,sym,dso" --stdio
# Overhead Samples Memory access Symbol Shared Object
# ........ ............ ........................ .......................... ................
#
29.46% 2331 L1 or L1 hit [.] __random libc-2.28.so
23.11% 2121 L1 or L1 hit [.] producer_populate_cache producer_consumer
18.56% 1758 L1 or L1 hit [.] __random_r libc-2.28.so
15.64% 1559 L2 or L2 hit [.] __random libc-2.28.so
.....
0.09% 5 Remote socket, same board Any cache hit [.] __random libc-2.28.so
0.07% 4 Remote socket, same board Any cache hit [.] __random libc-2.28.so
.....
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Reviewed-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211206091749.87585-5-kjain@linux.ibm.com
2021-12-06 17:17:49 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
|
|
|
if (sub_idx == 0)
|
|
|
|
ret = PH(LVL, REM_CCE1) | LEVEL(ANY_CACHE) | REM |
|
|
|
|
P(SNOOP, HIT) | P(HOPS, 2);
|
|
|
|
else if (sub_idx == 1)
|
|
|
|
ret = PH(LVL, REM_CCE1) | LEVEL(ANY_CACHE) | REM |
|
|
|
|
P(SNOOP, HITM) | P(HOPS, 2);
|
|
|
|
else if (sub_idx == 2)
|
|
|
|
ret = PH(LVL, REM_CCE2) | LEVEL(ANY_CACHE) | REM |
|
|
|
|
P(SNOOP, HIT) | P(HOPS, 3);
|
|
|
|
else if (sub_idx == 3)
|
|
|
|
ret = PH(LVL, REM_CCE2) | LEVEL(ANY_CACHE) | REM |
|
|
|
|
P(SNOOP, HITM) | P(HOPS, 3);
|
|
|
|
} else {
|
|
|
|
ret = PH(LVL, REM_CCE2);
|
|
|
|
if (sub_idx == 0 || sub_idx == 2)
|
|
|
|
ret |= P(SNOOP, HIT);
|
|
|
|
else if (sub_idx == 1 || sub_idx == 3)
|
|
|
|
ret |= P(SNOOP, HITM);
|
|
|
|
}
|
2017-04-11 09:51:06 +08:00
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
ret = PM(LVL, L1);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
|
|
|
|
struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
u64 idx;
|
|
|
|
u32 sub_idx;
|
|
|
|
u64 sier;
|
|
|
|
u64 val;
|
|
|
|
|
|
|
|
/* Skip if no SIER support */
|
|
|
|
if (!(flags & PPMU_HAS_SIER)) {
|
|
|
|
dsrc->val = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
sier = mfspr(SPRN_SIER);
|
|
|
|
val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
|
2021-03-04 19:55:37 +08:00
|
|
|
if (val != 1 && val != 2 && !(val == 7 && cpu_has_feature(CPU_FTR_ARCH_31)))
|
|
|
|
return;
|
|
|
|
|
|
|
|
idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT;
|
|
|
|
sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT;
|
|
|
|
|
|
|
|
dsrc->val = isa207_find_source(idx, sub_idx);
|
|
|
|
if (val == 7) {
|
|
|
|
u64 mmcra;
|
|
|
|
u32 op_type;
|
2017-04-11 09:51:06 +08:00
|
|
|
|
2021-03-04 19:55:37 +08:00
|
|
|
/*
|
|
|
|
* Type 0b111 denotes either larx or stcx instruction. Use the
|
|
|
|
* MMCRA sampling bits [57:59] along with the type value
|
|
|
|
* to determine the exact instruction type. If the sampling
|
|
|
|
* criteria is neither load or store, set the type as default
|
|
|
|
* to NA.
|
|
|
|
*/
|
|
|
|
mmcra = mfspr(SPRN_MMCRA);
|
|
|
|
|
|
|
|
op_type = (mmcra >> MMCRA_SAMP_ELIG_SHIFT) & MMCRA_SAMP_ELIG_MASK;
|
|
|
|
switch (op_type) {
|
|
|
|
case 5:
|
|
|
|
dsrc->val |= P(OP, LOAD);
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
dsrc->val |= P(OP, STORE);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dsrc->val |= P(OP, NA);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
2017-04-11 09:51:06 +08:00
|
|
|
dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-03-22 22:57:23 +08:00
|
|
|
void isa207_get_mem_weight(u64 *weight, u64 type)
|
2017-04-11 09:51:07 +08:00
|
|
|
{
|
2021-03-22 22:57:23 +08:00
|
|
|
union perf_sample_weight *weight_fields;
|
|
|
|
u64 weight_lat;
|
2017-04-11 09:51:07 +08:00
|
|
|
u64 mmcra = mfspr(SPRN_MMCRA);
|
|
|
|
u64 exp = MMCRA_THR_CTR_EXP(mmcra);
|
|
|
|
u64 mantissa = MMCRA_THR_CTR_MANT(mmcra);
|
2018-12-09 17:18:15 +08:00
|
|
|
u64 sier = mfspr(SPRN_SIER);
|
|
|
|
u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
|
2017-04-11 09:51:07 +08:00
|
|
|
|
2020-12-15 16:56:18 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31))
|
|
|
|
mantissa = P10_MMCRA_THR_CTR_MANT(mmcra);
|
|
|
|
|
2021-03-04 19:55:37 +08:00
|
|
|
if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31)))
|
2021-03-22 22:57:23 +08:00
|
|
|
weight_lat = 0;
|
2018-12-09 17:18:15 +08:00
|
|
|
else
|
2021-03-22 22:57:23 +08:00
|
|
|
weight_lat = mantissa << (2 * exp);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Use 64 bit weight field (full) if sample type is
|
|
|
|
* WEIGHT.
|
|
|
|
*
|
|
|
|
* if sample type is WEIGHT_STRUCT:
|
|
|
|
* - store memory latency in the lower 32 bits.
|
|
|
|
* - For ISA v3.1, use remaining two 16 bit fields of
|
|
|
|
* perf_sample_weight to store cycle counter values
|
|
|
|
* from sier2.
|
|
|
|
*/
|
|
|
|
weight_fields = (union perf_sample_weight *)weight;
|
|
|
|
if (type & PERF_SAMPLE_WEIGHT)
|
|
|
|
weight_fields->full = weight_lat;
|
|
|
|
else {
|
|
|
|
weight_fields->var1_dw = (u32)weight_lat;
|
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
|
|
|
weight_fields->var2_w = P10_SIER2_FINISH_CYC(mfspr(SPRN_SIER2));
|
|
|
|
weight_fields->var3_w = P10_SIER2_DISPATCH_CYC(mfspr(SPRN_SIER2));
|
|
|
|
}
|
|
|
|
}
|
2017-04-11 09:51:07 +08:00
|
|
|
}
|
2017-04-11 09:51:06 +08:00
|
|
|
|
powerpc/perf: Adds support for programming of Thresholding in P10
Thresholding, a performance monitoring unit feature, can be
used to identify marked instructions which take more than
expected cycles between start event and end event.
Threshold compare (thresh_cmp) bits are programmed in MMCRA
register. In Power9, thresh_cmp bits were part of the
event code. But in case of P10, thresh_cmp are not part of
event code due to inclusion of MMCR3 bits.
Patch here adds an option to use attr.config1 variable
to be used to pass thresh_cmp value to be programmed in
MMCRA register. A new ppmu flag called PPMU_HAS_ATTR_CONFIG1
has been added and this flag is used to notify the use of
attr.config1 variable.
Patch has extended the parameter list of 'compute_mmcr',
to include power_pmu's 'flags' element and parameter list of
get_constraint to include attr.config1 value. It also extend
parameter list of power_check_constraints inorder to pass
perf_event list.
As stated by commit ef0e3b650f8d ("powerpc/perf: Fix Threshold
Event Counter Multiplier width for P10"), constraint bits for
thresh_cmp is also needed to be increased to 11 bits, which is
handled as part of this patch. We added bit number 53 as part
of constraint bits of thresh_cmp for power10 to make it an
11 bit field.
Updated layout for p10:
/*
* Layout of constraint bits:
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
* | |
* [ thresh_cmp bits for p10] thresh_sel -*
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
* | | | | |
* BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
* EBB -* | | p1, p2, p3, p4, p5, p6.
* L1 I/D qualifier -* |
* nc - number of counters -*
*
* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
* we want the low bit of each field to be added to any existing value.
*
* Everything else is a value field.
*/
Result:
command#: cat /sys/devices/cpu/format/thresh_cmp
config1:0-17
ex. usage:
command#: perf record -I --weight -d -e
cpu/event=0x67340101EC,thresh_cmp=500/ ./ebizzy -S 2 -t 1 -s 4096
1826636 records/s
real 2.00 s
user 2.00 s
sys 0.00 s
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.038 MB perf.data (61 samples) ]
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210209095234.837356-1-kjain@linux.ibm.com
2021-02-09 17:52:34 +08:00
|
|
|
int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1)
|
2016-06-27 01:37:05 +08:00
|
|
|
{
|
|
|
|
unsigned int unit, pmc, cache, ebb;
|
|
|
|
unsigned long mask, value;
|
|
|
|
|
|
|
|
mask = value = 0;
|
|
|
|
|
2016-12-02 08:35:02 +08:00
|
|
|
if (!is_event_valid(event))
|
2016-06-27 01:37:05 +08:00
|
|
|
return -1;
|
|
|
|
|
|
|
|
pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
|
|
|
|
unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
|
2020-07-17 22:38:20 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31))
|
|
|
|
cache = (event >> EVENT_CACHE_SEL_SHIFT) &
|
|
|
|
p10_EVENT_CACHE_SEL_MASK;
|
|
|
|
else
|
|
|
|
cache = (event >> EVENT_CACHE_SEL_SHIFT) &
|
|
|
|
EVENT_CACHE_SEL_MASK;
|
2016-06-27 01:37:05 +08:00
|
|
|
ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK;
|
|
|
|
|
|
|
|
if (pmc) {
|
|
|
|
u64 base_event;
|
|
|
|
|
|
|
|
if (pmc > 6)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
/* Ignore Linux defined bits when checking event below */
|
|
|
|
base_event = event & ~EVENT_LINUX_MASK;
|
|
|
|
|
|
|
|
if (pmc >= 5 && base_event != 0x500fa &&
|
|
|
|
base_event != 0x600f4)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
mask |= CNST_PMC_MASK(pmc);
|
|
|
|
value |= CNST_PMC_VAL(pmc);
|
2020-09-21 15:10:04 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* PMC5 and PMC6 are used to count cycles and instructions and
|
|
|
|
* they do not support most of the constraint bits. Add a check
|
|
|
|
* to exclude PMC5/6 from most of the constraints except for
|
|
|
|
* EBB/BHRB.
|
|
|
|
*/
|
|
|
|
if (pmc >= 5)
|
|
|
|
goto ebb_bhrb;
|
2016-06-27 01:37:05 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (pmc <= 4) {
|
|
|
|
/*
|
|
|
|
* Add to number of counters in use. Note this includes events with
|
|
|
|
* a PMC of 0 - they still need a PMC, it's just assigned later.
|
|
|
|
* Don't count events on PMC 5 & 6, there is only one valid event
|
|
|
|
* on each of those counters, and they are handled above.
|
|
|
|
*/
|
|
|
|
mask |= CNST_NC_MASK;
|
|
|
|
value |= CNST_NC_VAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unit >= 6 && unit <= 9) {
|
2020-11-27 00:54:39 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
|
|
|
if (unit == 6) {
|
|
|
|
mask |= CNST_L2L3_GROUP_MASK;
|
|
|
|
value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT);
|
|
|
|
}
|
2020-07-17 22:38:20 +08:00
|
|
|
} else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
|
powerpc/perf: Add constraints for power9 l2/l3 bus events
In previous generation processors, both bus events and direct
events of performance monitoring unit can be individually
programmabled and monitored in PMCs.
But in Power9, L2/L3 bus events are always available as a
"bank" of 4 events. To obtain the counts for any of the
l2/l3 bus events in a given bank, the user will have to
program PMC4 with corresponding l2/l3 bus event for that
bank.
Patch enforce two contraints incase of L2/L3 bus events.
1)Any L2/L3 event when programmed is also expected to program corresponding
PMC4 event from that group.
2)PMC4 event should always been programmed first due to group constraint
logic limitation
For ex. consider these L3 bus events
PM_L3_PF_ON_CHIP_MEM (0x460A0),
PM_L3_PF_MISS_L3 (0x160A0),
PM_L3_CO_MEM (0x260A0),
PM_L3_PF_ON_CHIP_CACHE (0x360A0),
1) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
perf stat -e "{r160A0,r260A0,r360A0}" < >
And this is a VALID group for L3 Bus events:
perf stat -e "{r460A0,r160A0,r260A0,r360A0}" < >
2) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
perf stat -e "{r260A0,r360A0}" < >
And this is a VALID group for L3 Bus events:
perf stat -e "{r460A0,r260A0,r360A0}" < >
3) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
perf stat -e "{r360A0}" < >
And this is a VALID group for L3 Bus events:
perf stat -e "{r460A0,r360A0}" < >
Patch here implements group constraint logic suggested by Michael Ellerman.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-06-10 22:27:01 +08:00
|
|
|
mask |= CNST_CACHE_GROUP_MASK;
|
|
|
|
value |= CNST_CACHE_GROUP_VAL(event & 0xff);
|
|
|
|
|
|
|
|
mask |= CNST_CACHE_PMC4_MASK;
|
|
|
|
if (pmc == 4)
|
|
|
|
value |= CNST_CACHE_PMC4_VAL;
|
|
|
|
} else if (cache & 0x7) {
|
|
|
|
/*
|
|
|
|
* L2/L3 events contain a cache selector field, which is
|
|
|
|
* supposed to be programmed into MMCRC. However MMCRC is only
|
|
|
|
* HV writable, and there is no API for guest kernels to modify
|
|
|
|
* it. The solution is for the hypervisor to initialise the
|
|
|
|
* field to zeroes, and for us to only ever allow events that
|
|
|
|
* have a cache selector of zero. The bank selector (bit 3) is
|
|
|
|
* irrelevant, as long as the rest of the value is 0.
|
|
|
|
*/
|
2016-06-27 01:37:05 +08:00
|
|
|
return -1;
|
powerpc/perf: Add constraints for power9 l2/l3 bus events
In previous generation processors, both bus events and direct
events of performance monitoring unit can be individually
programmabled and monitored in PMCs.
But in Power9, L2/L3 bus events are always available as a
"bank" of 4 events. To obtain the counts for any of the
l2/l3 bus events in a given bank, the user will have to
program PMC4 with corresponding l2/l3 bus event for that
bank.
Patch enforce two contraints incase of L2/L3 bus events.
1)Any L2/L3 event when programmed is also expected to program corresponding
PMC4 event from that group.
2)PMC4 event should always been programmed first due to group constraint
logic limitation
For ex. consider these L3 bus events
PM_L3_PF_ON_CHIP_MEM (0x460A0),
PM_L3_PF_MISS_L3 (0x160A0),
PM_L3_CO_MEM (0x260A0),
PM_L3_PF_ON_CHIP_CACHE (0x360A0),
1) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
perf stat -e "{r160A0,r260A0,r360A0}" < >
And this is a VALID group for L3 Bus events:
perf stat -e "{r460A0,r160A0,r260A0,r360A0}" < >
2) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
perf stat -e "{r260A0,r360A0}" < >
And this is a VALID group for L3 Bus events:
perf stat -e "{r460A0,r260A0,r360A0}" < >
3) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
perf stat -e "{r360A0}" < >
And this is a VALID group for L3 Bus events:
perf stat -e "{r460A0,r360A0}" < >
Patch here implements group constraint logic suggested by Michael Ellerman.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-06-10 22:27:01 +08:00
|
|
|
}
|
2016-06-27 01:37:05 +08:00
|
|
|
|
2017-10-09 22:12:40 +08:00
|
|
|
} else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) {
|
2016-06-27 01:37:05 +08:00
|
|
|
mask |= CNST_L1_QUAL_MASK;
|
|
|
|
value |= CNST_L1_QUAL_VAL(cache);
|
|
|
|
}
|
|
|
|
|
2020-11-27 00:54:38 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
|
|
|
mask |= CNST_RADIX_SCOPE_GROUP_MASK;
|
|
|
|
value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT);
|
|
|
|
}
|
|
|
|
|
2017-02-20 21:59:03 +08:00
|
|
|
if (is_event_marked(event)) {
|
2016-06-27 01:37:05 +08:00
|
|
|
mask |= CNST_SAMPLE_MASK;
|
|
|
|
value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
|
|
|
|
}
|
|
|
|
|
2020-11-27 00:54:40 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
powerpc/perf: Adds support for programming of Thresholding in P10
Thresholding, a performance monitoring unit feature, can be
used to identify marked instructions which take more than
expected cycles between start event and end event.
Threshold compare (thresh_cmp) bits are programmed in MMCRA
register. In Power9, thresh_cmp bits were part of the
event code. But in case of P10, thresh_cmp are not part of
event code due to inclusion of MMCR3 bits.
Patch here adds an option to use attr.config1 variable
to be used to pass thresh_cmp value to be programmed in
MMCRA register. A new ppmu flag called PPMU_HAS_ATTR_CONFIG1
has been added and this flag is used to notify the use of
attr.config1 variable.
Patch has extended the parameter list of 'compute_mmcr',
to include power_pmu's 'flags' element and parameter list of
get_constraint to include attr.config1 value. It also extend
parameter list of power_check_constraints inorder to pass
perf_event list.
As stated by commit ef0e3b650f8d ("powerpc/perf: Fix Threshold
Event Counter Multiplier width for P10"), constraint bits for
thresh_cmp is also needed to be increased to 11 bits, which is
handled as part of this patch. We added bit number 53 as part
of constraint bits of thresh_cmp for power10 to make it an
11 bit field.
Updated layout for p10:
/*
* Layout of constraint bits:
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
* | |
* [ thresh_cmp bits for p10] thresh_sel -*
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
* | | | | |
* BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
* EBB -* | | p1, p2, p3, p4, p5, p6.
* L1 I/D qualifier -* |
* nc - number of counters -*
*
* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
* we want the low bit of each field to be added to any existing value.
*
* Everything else is a value field.
*/
Result:
command#: cat /sys/devices/cpu/format/thresh_cmp
config1:0-17
ex. usage:
command#: perf record -I --weight -d -e
cpu/event=0x67340101EC,thresh_cmp=500/ ./ebizzy -S 2 -t 1 -s 4096
1826636 records/s
real 2.00 s
user 2.00 s
sys 0.00 s
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.038 MB perf.data (61 samples) ]
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210209095234.837356-1-kjain@linux.ibm.com
2021-02-09 17:52:34 +08:00
|
|
|
if (event_is_threshold(event) && is_thresh_cmp_valid(event_config1)) {
|
2020-11-27 00:54:40 +08:00
|
|
|
mask |= CNST_THRESH_CTL_SEL_MASK;
|
|
|
|
value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT);
|
powerpc/perf: Adds support for programming of Thresholding in P10
Thresholding, a performance monitoring unit feature, can be
used to identify marked instructions which take more than
expected cycles between start event and end event.
Threshold compare (thresh_cmp) bits are programmed in MMCRA
register. In Power9, thresh_cmp bits were part of the
event code. But in case of P10, thresh_cmp are not part of
event code due to inclusion of MMCR3 bits.
Patch here adds an option to use attr.config1 variable
to be used to pass thresh_cmp value to be programmed in
MMCRA register. A new ppmu flag called PPMU_HAS_ATTR_CONFIG1
has been added and this flag is used to notify the use of
attr.config1 variable.
Patch has extended the parameter list of 'compute_mmcr',
to include power_pmu's 'flags' element and parameter list of
get_constraint to include attr.config1 value. It also extend
parameter list of power_check_constraints inorder to pass
perf_event list.
As stated by commit ef0e3b650f8d ("powerpc/perf: Fix Threshold
Event Counter Multiplier width for P10"), constraint bits for
thresh_cmp is also needed to be increased to 11 bits, which is
handled as part of this patch. We added bit number 53 as part
of constraint bits of thresh_cmp for power10 to make it an
11 bit field.
Updated layout for p10:
/*
* Layout of constraint bits:
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
* | |
* [ thresh_cmp bits for p10] thresh_sel -*
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
* | | | | |
* BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
* EBB -* | | p1, p2, p3, p4, p5, p6.
* L1 I/D qualifier -* |
* nc - number of counters -*
*
* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
* we want the low bit of each field to be added to any existing value.
*
* Everything else is a value field.
*/
Result:
command#: cat /sys/devices/cpu/format/thresh_cmp
config1:0-17
ex. usage:
command#: perf record -I --weight -d -e
cpu/event=0x67340101EC,thresh_cmp=500/ ./ebizzy -S 2 -t 1 -s 4096
1826636 records/s
real 2.00 s
user 2.00 s
sys 0.00 s
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.038 MB perf.data (61 samples) ]
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210209095234.837356-1-kjain@linux.ibm.com
2021-02-09 17:52:34 +08:00
|
|
|
mask |= p10_CNST_THRESH_CMP_MASK;
|
|
|
|
value |= p10_CNST_THRESH_CMP_VAL(p10_thresh_cmp_val(event_config1));
|
2022-05-06 14:10:14 +08:00
|
|
|
} else if (event_is_threshold(event))
|
|
|
|
return -1;
|
2020-11-27 00:54:40 +08:00
|
|
|
} else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
|
2017-02-13 19:32:54 +08:00
|
|
|
if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
|
|
|
|
mask |= CNST_THRESH_MASK;
|
|
|
|
value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
|
powerpc/perf: Fix the threshold compare group constraint for power9
Thresh compare bits for a event is used to program thresh compare
field in Monitor Mode Control Register A (MMCRA: 9-18 bits for power9).
When scheduling events as a group, all events in that group should
match value in threshold bits (like thresh compare, thresh control,
thresh select). Otherwise event open for the sibling events should fail.
But in the current code, incase thresh compare bits are not valid,
we are not failing in group_constraint function which can result
in invalid group schduling.
Fix the issue by returning -1 incase event is threshold and threshold
compare value is not valid.
Thresh control bits in the event code is used to program thresh_ctl
field in Monitor Mode Control Register A (MMCRA: 48-55). In below example,
the scheduling of group events PM_MRK_INST_CMPL (873534401e0) and
PM_THRESH_MET (8734340101ec) is expected to fail as both event
request different thresh control bits and invalid thresh compare value.
Result before the patch changes:
[command]# perf stat -e "{r8735340401e0,r8734340101ec}" sleep 1
Performance counter stats for 'sleep 1':
11,048 r8735340401e0
1,967 r8734340101ec
1.001354036 seconds time elapsed
0.001421000 seconds user
0.000000000 seconds sys
Result after the patch changes:
[command]# perf stat -e "{r8735340401e0,r8734340101ec}" sleep 1
Error:
The sys_perf_event_open() syscall returned with 22 (Invalid argument)
for event (r8735340401e0).
/bin/dmesg | grep -i perf may provide additional information.
Fixes: 78a16d9fc1206 ("powerpc/perf: Avoid FAB_*_MATCH checks for power9")
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Reviewed-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220506061015.43916-2-kjain@linux.ibm.com
2022-05-06 14:10:15 +08:00
|
|
|
} else if (event_is_threshold(event))
|
|
|
|
return -1;
|
2016-06-27 01:37:05 +08:00
|
|
|
} else {
|
|
|
|
/*
|
2017-02-13 19:32:54 +08:00
|
|
|
* Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
|
|
|
|
* the threshold control bits are used for the match value.
|
2016-06-27 01:37:05 +08:00
|
|
|
*/
|
2017-02-13 19:32:54 +08:00
|
|
|
if (event_is_fab_match(event)) {
|
|
|
|
mask |= CNST_FAB_MATCH_MASK;
|
|
|
|
value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
|
|
|
|
} else {
|
|
|
|
if (!is_thresh_cmp_valid(event))
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
mask |= CNST_THRESH_MASK;
|
|
|
|
value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
|
|
|
|
}
|
2016-06-27 01:37:05 +08:00
|
|
|
}
|
|
|
|
|
2020-09-21 15:10:04 +08:00
|
|
|
ebb_bhrb:
|
2016-06-27 01:37:05 +08:00
|
|
|
if (!pmc && ebb)
|
|
|
|
/* EBB events must specify the PMC */
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
if (event & EVENT_WANTS_BHRB) {
|
|
|
|
if (!ebb)
|
|
|
|
/* Only EBB events can request BHRB */
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
mask |= CNST_IFM_MASK;
|
|
|
|
value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* All events must agree on EBB, either all request it or none.
|
|
|
|
* EBB events are pinned & exclusive, so this should never actually
|
|
|
|
* hit, but we leave it as a fallback in case.
|
|
|
|
*/
|
2021-04-07 00:16:01 +08:00
|
|
|
mask |= CNST_EBB_MASK;
|
|
|
|
value |= CNST_EBB_VAL(ebb);
|
2016-06-27 01:37:05 +08:00
|
|
|
|
|
|
|
*maskp = mask;
|
|
|
|
*valp = value;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int isa207_compute_mmcr(u64 event[], int n_ev,
|
2020-07-17 22:38:13 +08:00
|
|
|
unsigned int hwc[], struct mmcr_regs *mmcr,
|
powerpc/perf: Adds support for programming of Thresholding in P10
Thresholding, a performance monitoring unit feature, can be
used to identify marked instructions which take more than
expected cycles between start event and end event.
Threshold compare (thresh_cmp) bits are programmed in MMCRA
register. In Power9, thresh_cmp bits were part of the
event code. But in case of P10, thresh_cmp are not part of
event code due to inclusion of MMCR3 bits.
Patch here adds an option to use attr.config1 variable
to be used to pass thresh_cmp value to be programmed in
MMCRA register. A new ppmu flag called PPMU_HAS_ATTR_CONFIG1
has been added and this flag is used to notify the use of
attr.config1 variable.
Patch has extended the parameter list of 'compute_mmcr',
to include power_pmu's 'flags' element and parameter list of
get_constraint to include attr.config1 value. It also extend
parameter list of power_check_constraints inorder to pass
perf_event list.
As stated by commit ef0e3b650f8d ("powerpc/perf: Fix Threshold
Event Counter Multiplier width for P10"), constraint bits for
thresh_cmp is also needed to be increased to 11 bits, which is
handled as part of this patch. We added bit number 53 as part
of constraint bits of thresh_cmp for power10 to make it an
11 bit field.
Updated layout for p10:
/*
* Layout of constraint bits:
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
* | |
* [ thresh_cmp bits for p10] thresh_sel -*
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
* | | | | |
* BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
* EBB -* | | p1, p2, p3, p4, p5, p6.
* L1 I/D qualifier -* |
* nc - number of counters -*
*
* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
* we want the low bit of each field to be added to any existing value.
*
* Everything else is a value field.
*/
Result:
command#: cat /sys/devices/cpu/format/thresh_cmp
config1:0-17
ex. usage:
command#: perf record -I --weight -d -e
cpu/event=0x67340101EC,thresh_cmp=500/ ./ebizzy -S 2 -t 1 -s 4096
1826636 records/s
real 2.00 s
user 2.00 s
sys 0.00 s
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.038 MB perf.data (61 samples) ]
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210209095234.837356-1-kjain@linux.ibm.com
2021-02-09 17:52:34 +08:00
|
|
|
struct perf_event *pevents[], u32 flags)
|
2016-06-27 01:37:05 +08:00
|
|
|
{
|
|
|
|
unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
|
2020-07-17 22:38:20 +08:00
|
|
|
unsigned long mmcr3;
|
2016-06-27 01:37:05 +08:00
|
|
|
unsigned int pmc, pmc_inuse;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
pmc_inuse = 0;
|
|
|
|
|
|
|
|
/* First pass to count resource use */
|
|
|
|
for (i = 0; i < n_ev; ++i) {
|
|
|
|
pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
|
|
|
|
if (pmc)
|
|
|
|
pmc_inuse |= 1 << pmc;
|
|
|
|
}
|
|
|
|
|
2020-07-17 22:38:20 +08:00
|
|
|
mmcra = mmcr1 = mmcr2 = mmcr3 = 0;
|
2016-06-27 01:37:05 +08:00
|
|
|
|
2020-07-17 22:38:23 +08:00
|
|
|
/*
|
|
|
|
* Disable bhrb unless explicitly requested
|
|
|
|
* by setting MMCRA (BHRBRD) bit.
|
|
|
|
*/
|
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31))
|
|
|
|
mmcra |= MMCRA_BHRB_DISABLE;
|
|
|
|
|
2016-06-27 01:37:05 +08:00
|
|
|
/* Second pass: assign PMCs, set all MMCR1 fields */
|
|
|
|
for (i = 0; i < n_ev; ++i) {
|
|
|
|
pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
|
|
|
|
unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
|
2016-12-02 08:35:02 +08:00
|
|
|
combine = combine_from_event(event[i]);
|
2016-06-27 01:37:05 +08:00
|
|
|
psel = event[i] & EVENT_PSEL_MASK;
|
|
|
|
|
|
|
|
if (!pmc) {
|
|
|
|
for (pmc = 1; pmc <= 4; ++pmc) {
|
|
|
|
if (!(pmc_inuse & (1 << pmc)))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
pmc_inuse |= 1 << pmc;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pmc <= 4) {
|
|
|
|
mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
|
2016-12-02 08:35:02 +08:00
|
|
|
mmcr1 |= combine << combine_shift(pmc);
|
2016-06-27 01:37:05 +08:00
|
|
|
mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
|
|
|
|
}
|
|
|
|
|
2016-12-02 08:35:02 +08:00
|
|
|
/* In continuous sampling mode, update SDAR on TLB miss */
|
2017-02-20 21:59:03 +08:00
|
|
|
mmcra_sdar_mode(event[i], &mmcra);
|
2016-12-02 08:35:02 +08:00
|
|
|
|
2017-10-09 22:12:40 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_300)) {
|
|
|
|
cache = dc_ic_rld_quad_l1_sel(event[i]);
|
|
|
|
mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
|
|
|
|
} else {
|
|
|
|
if (event[i] & EVENT_IS_L1) {
|
|
|
|
cache = dc_ic_rld_quad_l1_sel(event[i]);
|
|
|
|
mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
|
|
|
|
}
|
2016-06-27 01:37:05 +08:00
|
|
|
}
|
|
|
|
|
2020-11-27 00:54:38 +08:00
|
|
|
/* Set RADIX_SCOPE_QUAL bit */
|
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
|
|
|
val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) &
|
|
|
|
p10_EVENT_RADIX_SCOPE_QUAL_MASK;
|
|
|
|
mmcr1 |= val << p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT;
|
|
|
|
}
|
|
|
|
|
2017-02-20 21:59:03 +08:00
|
|
|
if (is_event_marked(event[i])) {
|
2016-06-27 01:37:05 +08:00
|
|
|
mmcra |= MMCRA_SAMPLE_ENABLE;
|
|
|
|
|
|
|
|
val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
|
|
|
|
if (val) {
|
|
|
|
mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT;
|
|
|
|
mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
|
|
|
|
* the threshold bits are used for the match value.
|
|
|
|
*/
|
2017-02-13 19:32:54 +08:00
|
|
|
if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) {
|
2016-06-27 01:37:05 +08:00
|
|
|
mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
|
|
|
|
EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
|
|
|
|
} else {
|
|
|
|
val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
|
|
|
|
mmcra |= val << MMCRA_THR_CTL_SHIFT;
|
|
|
|
val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
|
|
|
|
mmcra |= val << MMCRA_THR_SEL_SHIFT;
|
2020-07-17 22:38:20 +08:00
|
|
|
if (!cpu_has_feature(CPU_FTR_ARCH_31)) {
|
|
|
|
val = (event[i] >> EVENT_THR_CMP_SHIFT) &
|
|
|
|
EVENT_THR_CMP_MASK;
|
|
|
|
mmcra |= thresh_cmp_val(val);
|
powerpc/perf: Adds support for programming of Thresholding in P10
Thresholding, a performance monitoring unit feature, can be
used to identify marked instructions which take more than
expected cycles between start event and end event.
Threshold compare (thresh_cmp) bits are programmed in MMCRA
register. In Power9, thresh_cmp bits were part of the
event code. But in case of P10, thresh_cmp are not part of
event code due to inclusion of MMCR3 bits.
Patch here adds an option to use attr.config1 variable
to be used to pass thresh_cmp value to be programmed in
MMCRA register. A new ppmu flag called PPMU_HAS_ATTR_CONFIG1
has been added and this flag is used to notify the use of
attr.config1 variable.
Patch has extended the parameter list of 'compute_mmcr',
to include power_pmu's 'flags' element and parameter list of
get_constraint to include attr.config1 value. It also extend
parameter list of power_check_constraints inorder to pass
perf_event list.
As stated by commit ef0e3b650f8d ("powerpc/perf: Fix Threshold
Event Counter Multiplier width for P10"), constraint bits for
thresh_cmp is also needed to be increased to 11 bits, which is
handled as part of this patch. We added bit number 53 as part
of constraint bits of thresh_cmp for power10 to make it an
11 bit field.
Updated layout for p10:
/*
* Layout of constraint bits:
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
* | |
* [ thresh_cmp bits for p10] thresh_sel -*
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
* | | | | |
* BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
* EBB -* | | p1, p2, p3, p4, p5, p6.
* L1 I/D qualifier -* |
* nc - number of counters -*
*
* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
* we want the low bit of each field to be added to any existing value.
*
* Everything else is a value field.
*/
Result:
command#: cat /sys/devices/cpu/format/thresh_cmp
config1:0-17
ex. usage:
command#: perf record -I --weight -d -e
cpu/event=0x67340101EC,thresh_cmp=500/ ./ebizzy -S 2 -t 1 -s 4096
1826636 records/s
real 2.00 s
user 2.00 s
sys 0.00 s
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.038 MB perf.data (61 samples) ]
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210209095234.837356-1-kjain@linux.ibm.com
2021-02-09 17:52:34 +08:00
|
|
|
} else if (flags & PPMU_HAS_ATTR_CONFIG1) {
|
|
|
|
val = (pevents[i]->attr.config1 >> p10_EVENT_THR_CMP_SHIFT) &
|
|
|
|
p10_EVENT_THR_CMP_MASK;
|
|
|
|
mmcra |= thresh_cmp_val(val);
|
2020-07-17 22:38:20 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) {
|
|
|
|
val = (event[i] >> p10_L2L3_EVENT_SHIFT) &
|
|
|
|
p10_EVENT_L2L3_SEL_MASK;
|
|
|
|
mmcr2 |= val << p10_L2L3_SEL_SHIFT;
|
2016-06-27 01:37:05 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (event[i] & EVENT_WANTS_BHRB) {
|
|
|
|
val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
|
|
|
|
mmcra |= val << MMCRA_IFM_SHIFT;
|
|
|
|
}
|
|
|
|
|
2020-07-17 22:38:23 +08:00
|
|
|
/* set MMCRA (BHRBRD) to 0 if there is user request for BHRB */
|
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31) &&
|
|
|
|
(has_branch_stack(pevents[i]) || (event[i] & EVENT_WANTS_BHRB)))
|
|
|
|
mmcra &= ~MMCRA_BHRB_DISABLE;
|
|
|
|
|
2016-06-27 01:37:05 +08:00
|
|
|
if (pevents[i]->attr.exclude_user)
|
|
|
|
mmcr2 |= MMCR2_FCP(pmc);
|
|
|
|
|
|
|
|
if (pevents[i]->attr.exclude_hv)
|
|
|
|
mmcr2 |= MMCR2_FCH(pmc);
|
|
|
|
|
|
|
|
if (pevents[i]->attr.exclude_kernel) {
|
|
|
|
if (cpu_has_feature(CPU_FTR_HVMODE))
|
|
|
|
mmcr2 |= MMCR2_FCH(pmc);
|
|
|
|
else
|
|
|
|
mmcr2 |= MMCR2_FCS(pmc);
|
|
|
|
}
|
|
|
|
|
2021-04-29 13:02:08 +08:00
|
|
|
if (pevents[i]->attr.exclude_idle)
|
|
|
|
mmcr2 |= MMCR2_FCWAIT(pmc);
|
|
|
|
|
2020-07-17 22:38:20 +08:00
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
|
|
|
if (pmc <= 4) {
|
|
|
|
val = (event[i] >> p10_EVENT_MMCR3_SHIFT) &
|
|
|
|
p10_EVENT_MMCR3_MASK;
|
|
|
|
mmcr3 |= val << MMCR3_SHIFT(pmc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-06-27 01:37:05 +08:00
|
|
|
hwc[i] = pmc - 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return MMCRx values */
|
2020-07-17 22:38:13 +08:00
|
|
|
mmcr->mmcr0 = 0;
|
2016-06-27 01:37:05 +08:00
|
|
|
|
|
|
|
/* pmc_inuse is 1-based */
|
|
|
|
if (pmc_inuse & 2)
|
2020-07-17 22:38:13 +08:00
|
|
|
mmcr->mmcr0 = MMCR0_PMC1CE;
|
2016-06-27 01:37:05 +08:00
|
|
|
|
|
|
|
if (pmc_inuse & 0x7c)
|
2020-07-17 22:38:13 +08:00
|
|
|
mmcr->mmcr0 |= MMCR0_PMCjCE;
|
2016-06-27 01:37:05 +08:00
|
|
|
|
|
|
|
/* If we're not using PMC 5 or 6, freeze them */
|
|
|
|
if (!(pmc_inuse & 0x60))
|
2020-07-17 22:38:13 +08:00
|
|
|
mmcr->mmcr0 |= MMCR0_FC56;
|
2016-06-27 01:37:05 +08:00
|
|
|
|
2020-11-27 00:54:44 +08:00
|
|
|
/*
|
|
|
|
* Set mmcr0 (PMCCEXT) for p10 which
|
|
|
|
* will restrict access to group B registers
|
|
|
|
* when MMCR0 PMCC=0b00.
|
|
|
|
*/
|
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31))
|
|
|
|
mmcr->mmcr0 |= MMCR0_PMCCEXT;
|
|
|
|
|
2020-07-17 22:38:13 +08:00
|
|
|
mmcr->mmcr1 = mmcr1;
|
|
|
|
mmcr->mmcra = mmcra;
|
|
|
|
mmcr->mmcr2 = mmcr2;
|
2020-07-17 22:38:20 +08:00
|
|
|
mmcr->mmcr3 = mmcr3;
|
2016-06-27 01:37:05 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-07-17 22:38:13 +08:00
|
|
|
void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
|
2016-06-27 01:37:05 +08:00
|
|
|
{
|
|
|
|
if (pmc <= 3)
|
2020-07-17 22:38:13 +08:00
|
|
|
mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
|
2016-06-27 01:37:05 +08:00
|
|
|
}
|
2017-02-13 01:03:10 +08:00
|
|
|
|
|
|
|
static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size)
|
|
|
|
{
|
|
|
|
int i, j;
|
|
|
|
|
|
|
|
for (i = 0; i < size; ++i) {
|
|
|
|
if (event < ev_alt[i][0])
|
|
|
|
break;
|
|
|
|
|
|
|
|
for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j)
|
|
|
|
if (event == ev_alt[i][j])
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2017-07-31 16:02:41 +08:00
|
|
|
int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
|
|
|
|
const unsigned int ev_alt[][MAX_ALT])
|
2017-02-13 01:03:10 +08:00
|
|
|
{
|
|
|
|
int i, j, num_alt = 0;
|
|
|
|
u64 alt_event;
|
|
|
|
|
|
|
|
alt[num_alt++] = event;
|
|
|
|
i = find_alternative(event, ev_alt, size);
|
|
|
|
if (i >= 0) {
|
|
|
|
/* Filter out the original event, it's already in alt[0] */
|
|
|
|
for (j = 0; j < MAX_ALT; ++j) {
|
|
|
|
alt_event = ev_alt[i][j];
|
|
|
|
if (alt_event && alt_event != event)
|
|
|
|
alt[num_alt++] = alt_event;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-31 16:02:41 +08:00
|
|
|
if (flags & PPMU_ONLY_COUNT_RUN) {
|
|
|
|
/*
|
|
|
|
* We're only counting in RUN state, so PM_CYC is equivalent to
|
|
|
|
* PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL.
|
|
|
|
*/
|
|
|
|
j = num_alt;
|
|
|
|
for (i = 0; i < num_alt; ++i) {
|
|
|
|
switch (alt[i]) {
|
|
|
|
case 0x1e: /* PMC_CYC */
|
|
|
|
alt[j++] = 0x600f4; /* PM_RUN_CYC */
|
|
|
|
break;
|
|
|
|
case 0x600f4:
|
|
|
|
alt[j++] = 0x1e;
|
|
|
|
break;
|
|
|
|
case 0x2: /* PM_INST_CMPL */
|
|
|
|
alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
|
|
|
|
break;
|
|
|
|
case 0x500fa:
|
|
|
|
alt[j++] = 0x2;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
num_alt = j;
|
|
|
|
}
|
|
|
|
|
2017-02-13 01:03:10 +08:00
|
|
|
return num_alt;
|
|
|
|
}
|
2021-04-08 15:45:04 +08:00
|
|
|
|
|
|
|
int isa3XX_check_attr_config(struct perf_event *ev)
|
|
|
|
{
|
|
|
|
u64 val, sample_mode;
|
|
|
|
u64 event = ev->attr.config;
|
|
|
|
|
|
|
|
val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
|
|
|
|
sample_mode = val & 0x3;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* MMCRA[61:62] is Random Sampling Mode (SM).
|
|
|
|
* value of 0b11 is reserved.
|
|
|
|
*/
|
|
|
|
if (sample_mode == 0x3)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check for all reserved value
|
|
|
|
* Source: Performance Monitoring Unit User Guide
|
|
|
|
*/
|
|
|
|
switch (val) {
|
|
|
|
case 0x5:
|
|
|
|
case 0x9:
|
|
|
|
case 0xD:
|
|
|
|
case 0x19:
|
|
|
|
case 0x1D:
|
|
|
|
case 0x1A:
|
|
|
|
case 0x1E:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* MMCRA[48:51]/[52:55]) Threshold Start/Stop
|
|
|
|
* Events Selection.
|
|
|
|
* 0b11110000/0b00001111 is reserved.
|
|
|
|
*/
|
|
|
|
val = (event >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
|
|
|
|
if (((val & 0xF0) == 0xF0) || ((val & 0xF) == 0xF))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|