2020-05-01 22:58:50 +08:00
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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2019-04-13 00:08:49 +08:00
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for generic Intel audio DSP HDA IP
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*/
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2020-01-30 06:07:26 +08:00
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#include <linux/module.h>
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2019-04-13 00:08:49 +08:00
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#include <sound/hdaudio_ext.h>
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#include <sound/hda_register.h>
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2022-09-19 20:21:06 +08:00
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#include <trace/events/sof_intel.h>
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2020-01-30 06:07:25 +08:00
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#include "../sof-audio.h"
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2019-04-13 00:08:49 +08:00
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#include "../ops.h"
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#include "hda.h"
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2019-10-26 06:41:12 +08:00
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#include "hda-ipc.h"
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2019-04-13 00:08:49 +08:00
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2020-01-30 06:07:26 +08:00
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static bool hda_enable_trace_D0I3_S0;
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
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module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444);
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MODULE_PARM_DESC(enable_trace_D0I3_S0,
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"SOF HDA enable trace when the DSP is in D0I3 in S0");
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#endif
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2019-04-13 00:08:49 +08:00
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/*
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* DSP Core control.
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*/
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2021-09-15 15:18:03 +08:00
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static int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
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2019-04-13 00:08:49 +08:00
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{
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u32 adspcs;
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u32 reset;
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int ret;
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/* set reset bits for cores */
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reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS,
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2020-10-11 17:19:36 +08:00
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reset, reset);
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2019-04-13 00:08:49 +08:00
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/* poll with timeout to check if operation successful */
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS, adspcs,
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((adspcs & reset) == reset),
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HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_RESET_TIMEOUT_US);
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2019-10-23 03:28:44 +08:00
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
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__func__);
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return ret;
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}
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2019-04-13 00:08:49 +08:00
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/* has core entered reset ? */
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adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS);
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if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
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HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
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dev_err(sdev->dev,
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"error: reset enter failed: core_mask %x adspcs 0x%x\n",
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core_mask, adspcs);
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ret = -EIO;
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}
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return ret;
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}
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2021-09-15 15:18:03 +08:00
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static int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
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2019-04-13 00:08:49 +08:00
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{
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unsigned int crst;
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u32 adspcs;
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int ret;
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/* clear reset bits for cores */
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS,
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HDA_DSP_ADSPCS_CRST_MASK(core_mask),
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0);
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/* poll with timeout to check if operation successful */
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crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS, adspcs,
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!(adspcs & crst),
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HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_RESET_TIMEOUT_US);
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2019-10-23 03:28:44 +08:00
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
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__func__);
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return ret;
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}
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2019-04-13 00:08:49 +08:00
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/* has core left reset ? */
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adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS);
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if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
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dev_err(sdev->dev,
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"error: reset leave failed: core_mask %x adspcs 0x%x\n",
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core_mask, adspcs);
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ret = -EIO;
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}
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return ret;
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}
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2022-09-20 21:16:57 +08:00
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int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
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2019-04-13 00:08:49 +08:00
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{
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/* stall core */
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS,
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HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
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HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
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/* set reset state */
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return hda_dsp_core_reset_enter(sdev, core_mask);
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}
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2022-09-20 21:16:57 +08:00
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bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask)
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2021-09-15 15:18:03 +08:00
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{
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int val;
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bool is_enable;
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val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
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#define MASK_IS_EQUAL(v, m, field) ({ \
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u32 _m = field(m); \
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((v) & _m) == _m; \
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})
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is_enable = MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_CPA_MASK) &&
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MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_SPA_MASK) &&
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!(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
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!(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
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#undef MASK_IS_EQUAL
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dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
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is_enable, core_mask);
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return is_enable;
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}
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2019-04-13 00:08:49 +08:00
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int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
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{
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int ret;
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/* leave reset state */
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ret = hda_dsp_core_reset_leave(sdev, core_mask);
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if (ret < 0)
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return ret;
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/* run core */
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dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS,
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HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
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0);
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/* is core now running ? */
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if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
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hda_dsp_core_stall_reset(sdev, core_mask);
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dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
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core_mask);
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ret = -EIO;
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}
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return ret;
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}
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/*
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* Power Management.
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*/
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2022-06-09 16:59:47 +08:00
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int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
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2019-04-13 00:08:49 +08:00
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{
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2022-06-09 16:59:47 +08:00
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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2019-04-13 00:08:49 +08:00
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unsigned int cpa;
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u32 adspcs;
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int ret;
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2022-06-09 16:59:47 +08:00
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/* restrict core_mask to host managed cores mask */
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core_mask &= chip->host_managed_cores_mask;
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/* return if core_mask is not valid */
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if (!core_mask)
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return 0;
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2019-04-13 00:08:49 +08:00
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/* update bits */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
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HDA_DSP_ADSPCS_SPA_MASK(core_mask),
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HDA_DSP_ADSPCS_SPA_MASK(core_mask));
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/* poll with timeout to check if operation successful */
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cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS, adspcs,
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(adspcs & cpa) == cpa,
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HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_RESET_TIMEOUT_US);
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2019-10-23 03:28:44 +08:00
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
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__func__);
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return ret;
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}
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2019-04-13 00:08:49 +08:00
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/* did core power up ? */
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adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS);
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if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
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HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
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dev_err(sdev->dev,
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"error: power up core failed core_mask %xadspcs 0x%x\n",
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core_mask, adspcs);
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ret = -EIO;
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}
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return ret;
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}
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2021-09-15 15:18:03 +08:00
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static int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
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2019-04-13 00:08:49 +08:00
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{
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u32 adspcs;
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2019-10-23 03:28:44 +08:00
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int ret;
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2019-04-13 00:08:49 +08:00
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/* update bits */
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS,
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HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
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2019-10-23 03:28:44 +08:00
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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2019-04-13 00:08:49 +08:00
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HDA_DSP_REG_ADSPCS, adspcs,
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2021-03-09 08:41:27 +08:00
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!(adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)),
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2019-04-13 00:08:49 +08:00
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HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
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2019-10-23 03:28:44 +08:00
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if (ret < 0)
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dev_err(sdev->dev,
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"error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
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__func__);
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return ret;
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2019-04-13 00:08:49 +08:00
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}
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int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
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{
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2020-09-11 00:41:23 +08:00
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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2019-04-13 00:08:49 +08:00
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int ret;
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2020-09-11 00:41:23 +08:00
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/* restrict core_mask to host managed cores mask */
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core_mask &= chip->host_managed_cores_mask;
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/* return if core_mask is not valid or cores are already enabled */
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if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask))
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2019-04-13 00:08:49 +08:00
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return 0;
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/* power up */
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ret = hda_dsp_core_power_up(sdev, core_mask);
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if (ret < 0) {
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dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
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core_mask);
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return ret;
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}
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return hda_dsp_core_run(sdev, core_mask);
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}
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int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
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unsigned int core_mask)
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{
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2020-09-11 00:41:23 +08:00
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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2019-04-13 00:08:49 +08:00
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int ret;
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2020-09-11 00:41:23 +08:00
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/* restrict core_mask to host managed cores mask */
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core_mask &= chip->host_managed_cores_mask;
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/* return if core_mask is not valid */
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if (!core_mask)
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return 0;
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2019-04-13 00:08:49 +08:00
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/* place core in reset prior to power down */
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ret = hda_dsp_core_stall_reset(sdev, core_mask);
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if (ret < 0) {
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dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
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core_mask);
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return ret;
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}
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/* power down core */
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ret = hda_dsp_core_power_down(sdev, core_mask);
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if (ret < 0) {
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dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
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core_mask, ret);
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return ret;
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}
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/* make sure we are in OFF state */
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|
|
if (hda_dsp_core_is_enabled(sdev, core_mask)) {
|
|
|
|
dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
|
|
|
|
core_mask, ret);
|
|
|
|
ret = -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
|
|
|
|
{
|
|
|
|
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
|
|
|
|
const struct sof_intel_dsp_desc *chip = hda->desc;
|
|
|
|
|
|
|
|
/* enable IPC DONE and BUSY interrupts */
|
|
|
|
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
|
|
|
|
HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
|
|
|
|
HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
|
|
|
|
|
|
|
|
/* enable IPC interrupt */
|
|
|
|
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
|
|
|
|
HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
|
|
|
|
}
|
|
|
|
|
|
|
|
void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
|
|
|
|
{
|
|
|
|
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
|
|
|
|
const struct sof_intel_dsp_desc *chip = hda->desc;
|
|
|
|
|
|
|
|
/* disable IPC interrupt */
|
|
|
|
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
|
|
|
|
HDA_DSP_ADSPIC_IPC, 0);
|
|
|
|
|
|
|
|
/* disable IPC BUSY and DONE interrupt */
|
|
|
|
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
|
|
|
|
HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
|
|
|
|
}
|
|
|
|
|
2019-11-02 01:09:16 +08:00
|
|
|
static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
|
2019-10-26 06:41:00 +08:00
|
|
|
{
|
|
|
|
struct hdac_bus *bus = sof_to_bus(sdev);
|
2019-11-02 01:09:16 +08:00
|
|
|
int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
|
2019-10-26 06:41:00 +08:00
|
|
|
|
|
|
|
while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
|
|
|
|
if (!retry--)
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
usleep_range(10, 15);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-10-26 06:41:12 +08:00
|
|
|
static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
|
|
|
|
{
|
|
|
|
struct sof_ipc_pm_gate pm_gate;
|
|
|
|
struct sof_ipc_reply reply;
|
|
|
|
|
|
|
|
memset(&pm_gate, 0, sizeof(pm_gate));
|
|
|
|
|
|
|
|
/* configure pm_gate ipc message */
|
|
|
|
pm_gate.hdr.size = sizeof(pm_gate);
|
|
|
|
pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
|
|
|
|
pm_gate.flags = flags;
|
|
|
|
|
|
|
|
/* send pm_gate ipc to dsp */
|
2022-03-31 04:19:24 +08:00
|
|
|
return sof_ipc_tx_message_no_pm(sdev->ipc, &pm_gate, sizeof(pm_gate),
|
|
|
|
&reply, sizeof(reply));
|
2019-10-26 06:41:12 +08:00
|
|
|
}
|
|
|
|
|
2020-01-30 06:07:22 +08:00
|
|
|
static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
|
2019-10-26 06:41:00 +08:00
|
|
|
{
|
|
|
|
struct hdac_bus *bus = sof_to_bus(sdev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Write to D0I3C after Command-In-Progress bit is cleared */
|
2019-11-02 01:09:16 +08:00
|
|
|
ret = hda_dsp_wait_d0i3c_done(sdev);
|
2019-10-26 06:41:00 +08:00
|
|
|
if (ret < 0) {
|
2019-10-26 06:41:06 +08:00
|
|
|
dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
|
2019-10-26 06:41:00 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Update D0I3C register */
|
|
|
|
snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
|
|
|
|
|
|
|
|
/* Wait for cmd in progress to be cleared before exiting the function */
|
2019-11-02 01:09:16 +08:00
|
|
|
ret = hda_dsp_wait_d0i3c_done(sdev);
|
2019-10-26 06:41:00 +08:00
|
|
|
if (ret < 0) {
|
2019-10-26 06:41:06 +08:00
|
|
|
dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
|
2019-10-26 06:41:00 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2022-09-19 20:21:06 +08:00
|
|
|
trace_sof_intel_D0I3C_updated(sdev, snd_hdac_chip_readb(bus, VS_D0I3C));
|
2019-10-26 06:41:00 +08:00
|
|
|
|
2020-01-30 06:07:22 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2019-10-26 06:41:12 +08:00
|
|
|
|
2020-01-30 06:07:22 +08:00
|
|
|
static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
|
|
|
|
const struct sof_dsp_power_state *target_state)
|
|
|
|
{
|
|
|
|
u32 flags = 0;
|
|
|
|
int ret;
|
|
|
|
u8 value = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Sanity check for illegal state transitions
|
|
|
|
* The only allowed transitions are:
|
|
|
|
* 1. D3 -> D0I0
|
|
|
|
* 2. D0I0 -> D0I3
|
|
|
|
* 3. D0I3 -> D0I0
|
|
|
|
*/
|
|
|
|
switch (sdev->dsp_power_state.state) {
|
|
|
|
case SOF_DSP_PM_D0:
|
|
|
|
/* Follow the sequence below for D0 substate transitions */
|
|
|
|
break;
|
|
|
|
case SOF_DSP_PM_D3:
|
|
|
|
/* Follow regular flow for D3 -> D0 transition */
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
|
|
|
|
sdev->dsp_power_state.state, target_state->state);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set flags and register value for D0 target substate */
|
|
|
|
if (target_state->substate == SOF_HDA_DSP_PM_D0I3) {
|
|
|
|
value = SOF_HDA_VS_D0I3C_I3;
|
|
|
|
|
2020-01-30 06:07:26 +08:00
|
|
|
/*
|
2020-07-28 02:36:13 +08:00
|
|
|
* Trace DMA need to be disabled when the DSP enters
|
|
|
|
* D0I3 for S0Ix suspend, but it can be kept enabled
|
|
|
|
* when the DSP enters D0I3 while the system is in S0
|
|
|
|
* for debug purpose.
|
2020-01-30 06:07:26 +08:00
|
|
|
*/
|
2022-05-16 18:47:05 +08:00
|
|
|
if (!sdev->fw_trace_is_supported ||
|
2020-07-28 02:36:13 +08:00
|
|
|
!hda_enable_trace_D0I3_S0 ||
|
2020-01-30 06:07:26 +08:00
|
|
|
sdev->system_suspend_target != SOF_SUSPEND_NONE)
|
|
|
|
flags = HDA_PM_NO_DMA_TRACE;
|
2020-01-30 06:07:22 +08:00
|
|
|
} else {
|
|
|
|
/* prevent power gating in D0I0 */
|
|
|
|
flags = HDA_PM_PPG;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* update D0I3C register */
|
|
|
|
ret = hda_dsp_update_d0i3c_register(sdev, value);
|
2019-10-26 06:41:12 +08:00
|
|
|
if (ret < 0)
|
2020-01-30 06:07:22 +08:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Notify the DSP of the state change.
|
|
|
|
* If this IPC fails, revert the D0I3C register update in order
|
|
|
|
* to prevent partial state change.
|
|
|
|
*/
|
|
|
|
ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
|
|
|
|
if (ret < 0) {
|
2019-10-26 06:41:12 +08:00
|
|
|
dev_err(sdev->dev,
|
|
|
|
"error: PM_GATE ipc error %d\n", ret);
|
2020-01-30 06:07:22 +08:00
|
|
|
goto revert;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
revert:
|
|
|
|
/* fallback to the previous register value */
|
|
|
|
value = value ? 0 : SOF_HDA_VS_D0I3C_I3;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This can fail but return the IPC error to signal that
|
|
|
|
* the state change failed.
|
|
|
|
*/
|
|
|
|
hda_dsp_update_d0i3c_register(sdev, value);
|
2019-10-26 06:41:12 +08:00
|
|
|
|
|
|
|
return ret;
|
2019-10-26 06:41:00 +08:00
|
|
|
}
|
|
|
|
|
2020-03-26 05:12:29 +08:00
|
|
|
/* helper to log DSP state */
|
|
|
|
static void hda_dsp_state_log(struct snd_sof_dev *sdev)
|
|
|
|
{
|
|
|
|
switch (sdev->dsp_power_state.state) {
|
|
|
|
case SOF_DSP_PM_D0:
|
|
|
|
switch (sdev->dsp_power_state.substate) {
|
|
|
|
case SOF_HDA_DSP_PM_D0I0:
|
|
|
|
dev_dbg(sdev->dev, "Current DSP power state: D0I0\n");
|
|
|
|
break;
|
|
|
|
case SOF_HDA_DSP_PM_D0I3:
|
|
|
|
dev_dbg(sdev->dev, "Current DSP power state: D0I3\n");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n",
|
|
|
|
sdev->dsp_power_state.substate);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SOF_DSP_PM_D1:
|
|
|
|
dev_dbg(sdev->dev, "Current DSP power state: D1\n");
|
|
|
|
break;
|
|
|
|
case SOF_DSP_PM_D2:
|
|
|
|
dev_dbg(sdev->dev, "Current DSP power state: D2\n");
|
|
|
|
break;
|
|
|
|
case SOF_DSP_PM_D3:
|
|
|
|
dev_dbg(sdev->dev, "Current DSP power state: D3\n");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_dbg(sdev->dev, "Unknown DSP power state: %d\n",
|
|
|
|
sdev->dsp_power_state.state);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-01-30 06:07:22 +08:00
|
|
|
/*
|
|
|
|
* All DSP power state transitions are initiated by the driver.
|
|
|
|
* If the requested state change fails, the error is simply returned.
|
|
|
|
* Further state transitions are attempted only when the set_power_save() op
|
|
|
|
* is called again either because of a new IPC sent to the DSP or
|
|
|
|
* during system suspend/resume.
|
|
|
|
*/
|
|
|
|
int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
|
|
|
|
const struct sof_dsp_power_state *target_state)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
2020-01-30 06:07:26 +08:00
|
|
|
/*
|
|
|
|
* When the DSP is already in D0I3 and the target state is D0I3,
|
|
|
|
* it could be the case that the DSP is in D0I3 during S0
|
|
|
|
* and the system is suspending to S0Ix. Therefore,
|
|
|
|
* hda_dsp_set_D0_state() must be called to disable trace DMA
|
|
|
|
* by sending the PM_GATE IPC to the FW.
|
|
|
|
*/
|
|
|
|
if (target_state->substate == SOF_HDA_DSP_PM_D0I3 &&
|
|
|
|
sdev->system_suspend_target == SOF_SUSPEND_S0IX)
|
|
|
|
goto set_state;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For all other cases, return without doing anything if
|
|
|
|
* the DSP is already in the target state.
|
|
|
|
*/
|
2020-01-30 06:07:22 +08:00
|
|
|
if (target_state->state == sdev->dsp_power_state.state &&
|
|
|
|
target_state->substate == sdev->dsp_power_state.substate)
|
|
|
|
return 0;
|
|
|
|
|
2020-01-30 06:07:26 +08:00
|
|
|
set_state:
|
2020-01-30 06:07:22 +08:00
|
|
|
switch (target_state->state) {
|
|
|
|
case SOF_DSP_PM_D0:
|
|
|
|
ret = hda_dsp_set_D0_state(sdev, target_state);
|
|
|
|
break;
|
|
|
|
case SOF_DSP_PM_D3:
|
|
|
|
/* The only allowed transition is: D0I0 -> D3 */
|
|
|
|
if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
|
|
|
|
sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
dev_err(sdev->dev,
|
|
|
|
"error: transition from %d to %d not allowed\n",
|
|
|
|
sdev->dsp_power_state.state, target_state->state);
|
|
|
|
return -EINVAL;
|
|
|
|
default:
|
|
|
|
dev_err(sdev->dev, "error: target state unsupported %d\n",
|
|
|
|
target_state->state);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(sdev->dev,
|
|
|
|
"failed to set requested target DSP state %d substate %d\n",
|
|
|
|
target_state->state, target_state->substate);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
sdev->dsp_power_state = *target_state;
|
2020-03-26 05:12:29 +08:00
|
|
|
hda_dsp_state_log(sdev);
|
2020-01-30 06:07:22 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Audio DSP states may transform as below:-
|
|
|
|
*
|
2020-01-30 06:07:24 +08:00
|
|
|
* Opportunistic D0I3 in S0
|
|
|
|
* Runtime +---------------------+ Delayed D0i3 work timeout
|
2020-01-30 06:07:22 +08:00
|
|
|
* suspend | +--------------------+
|
2020-01-30 06:07:24 +08:00
|
|
|
* +------------+ D0I0(active) | |
|
2020-01-30 06:07:22 +08:00
|
|
|
* | | <---------------+ |
|
2020-01-30 06:07:24 +08:00
|
|
|
* | +--------> | New IPC | |
|
|
|
|
* | |Runtime +--^--+---------^--+--+ (via mailbox) | |
|
|
|
|
* | |resume | | | | | |
|
|
|
|
* | | | | | | | |
|
|
|
|
* | | System| | | | | |
|
|
|
|
* | | resume| | S3/S0IX | | | |
|
|
|
|
* | | | | suspend | | S0IX | |
|
2020-01-30 06:07:22 +08:00
|
|
|
* | | | | | |suspend | |
|
|
|
|
* | | | | | | | |
|
|
|
|
* | | | | | | | |
|
|
|
|
* +-v---+-----------+--v-------+ | | +------+----v----+
|
|
|
|
* | | | +-----------> |
|
2020-01-30 06:07:24 +08:00
|
|
|
* | D3 (suspended) | | | D0I3 |
|
|
|
|
* | | +--------------+ |
|
|
|
|
* | | System resume | |
|
|
|
|
* +----------------------------+ +----------------+
|
2020-01-30 06:07:22 +08:00
|
|
|
*
|
2020-01-30 06:07:24 +08:00
|
|
|
* S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
|
|
|
|
* ignored the suspend trigger. Otherwise the DSP
|
|
|
|
* is in D3.
|
2020-01-30 06:07:22 +08:00
|
|
|
*/
|
|
|
|
|
2019-07-22 22:13:50 +08:00
|
|
|
static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
|
2019-04-13 00:08:49 +08:00
|
|
|
{
|
|
|
|
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
|
|
|
|
const struct sof_intel_dsp_desc *chip = hda->desc;
|
|
|
|
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
|
|
|
struct hdac_bus *bus = sof_to_bus(sdev);
|
|
|
|
#endif
|
2021-11-20 03:26:19 +08:00
|
|
|
int ret, j;
|
2019-04-13 00:08:49 +08:00
|
|
|
|
2022-07-12 20:09:35 +08:00
|
|
|
/*
|
|
|
|
* The memory used for IMR boot loses its content in deeper than S3 state
|
|
|
|
* We must not try IMR boot on next power up (as it will fail).
|
2022-08-23 20:43:59 +08:00
|
|
|
*
|
|
|
|
* In case of firmware crash or boot failure set the skip_imr_boot to true
|
|
|
|
* as well in order to try to re-load the firmware to do a 'cold' boot.
|
2022-07-12 20:09:35 +08:00
|
|
|
*/
|
2022-08-23 20:43:59 +08:00
|
|
|
if (sdev->system_suspend_target > SOF_SUSPEND_S3 ||
|
|
|
|
sdev->fw_state == SOF_FW_CRASHED ||
|
|
|
|
sdev->fw_state == SOF_FW_BOOT_FAILED)
|
2022-07-12 20:09:35 +08:00
|
|
|
hda->skip_imr_boot = true;
|
|
|
|
|
2020-03-26 05:50:22 +08:00
|
|
|
hda_sdw_int_enable(sdev, false);
|
|
|
|
|
2019-04-13 00:08:49 +08:00
|
|
|
/* disable IPC interrupts */
|
|
|
|
hda_dsp_ipc_int_disable(sdev);
|
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
2021-11-05 19:16:55 +08:00
|
|
|
hda_codec_jack_wake_enable(sdev, runtime_suspend);
|
2019-07-22 22:13:53 +08:00
|
|
|
|
2019-04-13 00:08:49 +08:00
|
|
|
/* power down all hda link */
|
|
|
|
snd_hdac_ext_bus_link_power_down_all(bus);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* power down DSP */
|
2021-11-20 03:26:19 +08:00
|
|
|
ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
|
2019-04-13 00:08:49 +08:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(sdev->dev,
|
|
|
|
"error: failed to power down core during suspend\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-11-20 03:26:19 +08:00
|
|
|
/* reset ref counts for all cores */
|
|
|
|
for (j = 0; j < chip->cores_num; j++)
|
|
|
|
sdev->dsp_core_ref_count[j] = 0;
|
|
|
|
|
2019-04-13 00:08:49 +08:00
|
|
|
/* disable ppcap interrupt */
|
2019-06-13 01:23:42 +08:00
|
|
|
hda_dsp_ctrl_ppcap_enable(sdev, false);
|
|
|
|
hda_dsp_ctrl_ppcap_int_enable(sdev, false);
|
2019-04-13 00:08:49 +08:00
|
|
|
|
2019-06-13 01:23:44 +08:00
|
|
|
/* disable hda bus irq and streams */
|
|
|
|
hda_dsp_ctrl_stop_chip(sdev);
|
2019-04-13 00:08:49 +08:00
|
|
|
|
|
|
|
/* disable LP retention mode */
|
|
|
|
snd_sof_pci_update_bits(sdev, PCI_PGCTL,
|
|
|
|
PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
|
|
|
|
|
|
|
|
/* reset controller */
|
|
|
|
ret = hda_dsp_ctrl_link_reset(sdev, true);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(sdev->dev,
|
|
|
|
"error: failed to reset controller during suspend\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-02-07 04:02:22 +08:00
|
|
|
/* display codec can powered off after link reset */
|
|
|
|
hda_codec_i915_display_power(sdev, false);
|
|
|
|
|
2019-04-13 00:08:49 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-07-22 22:13:53 +08:00
|
|
|
static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
|
2019-04-13 00:08:49 +08:00
|
|
|
{
|
|
|
|
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
|
|
|
struct hdac_bus *bus = sof_to_bus(sdev);
|
|
|
|
struct hdac_ext_link *hlink = NULL;
|
|
|
|
#endif
|
|
|
|
int ret;
|
|
|
|
|
2020-02-07 04:02:22 +08:00
|
|
|
/* display codec must be powered before link reset */
|
|
|
|
hda_codec_i915_display_power(sdev, true);
|
|
|
|
|
2019-04-13 00:08:49 +08:00
|
|
|
/*
|
|
|
|
* clear TCSEL to clear playback on some HD Audio
|
|
|
|
* codecs. PCI TCSEL is defined in the Intel manuals.
|
|
|
|
*/
|
|
|
|
snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
|
|
|
|
|
|
|
|
/* reset and start hda controller */
|
|
|
|
ret = hda_dsp_ctrl_init_chip(sdev, true);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(sdev->dev,
|
|
|
|
"error: failed to start controller after resume\n");
|
2021-02-24 22:15:41 +08:00
|
|
|
goto cleanup;
|
2019-04-13 00:08:49 +08:00
|
|
|
}
|
|
|
|
|
2019-07-22 22:13:53 +08:00
|
|
|
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
|
|
|
/* check jack status */
|
2021-01-13 02:11:24 +08:00
|
|
|
if (runtime_resume) {
|
|
|
|
hda_codec_jack_wake_enable(sdev, false);
|
ASoC: SOF: Intel: hda: Avoid checking jack on system suspend
System takes a very long time to suspend after commit 215a22ed31a1
("ALSA: hda: Refactor codec PM to use direct-complete optimization"):
[ 90.065964] PM: suspend entry (s2idle)
[ 90.067337] Filesystems sync: 0.001 seconds
[ 90.185758] Freezing user space processes ... (elapsed 0.002 seconds) done.
[ 90.188713] OOM killer disabled.
[ 90.188714] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
[ 90.190024] printk: Suspending console(s) (use no_console_suspend to debug)
[ 90.904912] intel_pch_thermal 0000:00:12.0: CPU-PCH is cool [49C], continue to suspend
[ 321.262505] snd_hda_codec_realtek ehdaudio0D0: Unable to sync register 0x2b8000. -5
[ 328.426919] snd_hda_codec_realtek ehdaudio0D0: Unable to sync register 0x2b8000. -5
[ 329.490933] ACPI: EC: interrupt blocked
That commit keeps the codec suspended during the system suspend. However,
mute/micmute LED will clear codec's direct-complete flag by
dpm_clear_superiors_direct_complete().
This doesn't play well with SOF driver. When its runtime resume is
called for system suspend, hda_codec_jack_check() schedules
jackpoll_work which uses snd_hdac_is_power_on() to check whether codec
is suspended. Because the direct-complete path isn't taken,
pm_runtime_disable() isn't called so snd_hdac_is_power_on() returns
false and jackpoll continues to run, and snd_hda_power_up_pm() cannot
power up an already suspended codec in multiple attempts, causes the
long delay on system suspend:
if (dev->power.direct_complete) {
if (pm_runtime_status_suspended(dev)) {
pm_runtime_disable(dev);
if (pm_runtime_status_suspended(dev)) {
pm_dev_dbg(dev, state, "direct-complete ");
goto Complete;
}
pm_runtime_enable(dev);
}
dev->power.direct_complete = false;
}
When direct-complete path is taken, snd_hdac_is_power_on() returns true
and hda_jackpoll_work() is skipped by accident. So this is still not
correct.
If we were to use snd_hdac_is_power_on() in system PM path,
pm_runtime_status_suspended() should be used instead of
pm_runtime_suspended(), otherwise pm_runtime_{enable,disable}() may
change the outcome of snd_hdac_is_power_on().
Because devices suspend in reverse order (i.e. child first), it doesn't
make much sense to resume an already suspended codec from audio
controller. So avoid the issue by making sure jackpoll isn't used in
system PM process.
Fixes: 215a22ed31a1 ("ALSA: hda: Refactor codec PM to use direct-complete optimization")
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Link: https://lore.kernel.org/r/20210112181128.1229827-3-kai.heng.feng@canonical.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13 02:11:25 +08:00
|
|
|
if (sdev->system_suspend_target == SOF_SUSPEND_NONE)
|
|
|
|
hda_codec_jack_check(sdev);
|
2021-01-13 02:11:24 +08:00
|
|
|
}
|
2019-07-22 22:13:52 +08:00
|
|
|
|
|
|
|
/* turn off the links that were off before suspend */
|
|
|
|
list_for_each_entry(hlink, &bus->hlink_list, list) {
|
|
|
|
if (!hlink->ref_count)
|
|
|
|
snd_hdac_ext_bus_link_power_down(hlink);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* check dma status and clean up CORB/RIRB buffers */
|
|
|
|
if (!bus->cmd_dma_state)
|
|
|
|
snd_hdac_bus_stop_cmd_io(bus);
|
2019-06-13 01:23:42 +08:00
|
|
|
#endif
|
2019-04-13 00:08:49 +08:00
|
|
|
|
|
|
|
/* enable ppcap interrupt */
|
|
|
|
hda_dsp_ctrl_ppcap_enable(sdev, true);
|
|
|
|
hda_dsp_ctrl_ppcap_int_enable(sdev, true);
|
|
|
|
|
2021-02-24 22:15:41 +08:00
|
|
|
cleanup:
|
|
|
|
/* display codec can powered off after controller init */
|
|
|
|
hda_codec_i915_display_power(sdev, false);
|
|
|
|
|
2019-04-13 00:08:49 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int hda_dsp_resume(struct snd_sof_dev *sdev)
|
|
|
|
{
|
2019-11-02 01:09:15 +08:00
|
|
|
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
|
2019-10-26 06:41:19 +08:00
|
|
|
struct pci_dev *pci = to_pci_dev(sdev->dev);
|
2020-01-30 06:07:22 +08:00
|
|
|
const struct sof_dsp_power_state target_state = {
|
|
|
|
.state = SOF_DSP_PM_D0,
|
|
|
|
.substate = SOF_HDA_DSP_PM_D0I0,
|
|
|
|
};
|
2020-07-28 02:36:12 +08:00
|
|
|
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
|
|
|
struct hdac_bus *bus = sof_to_bus(sdev);
|
|
|
|
struct hdac_ext_link *hlink = NULL;
|
|
|
|
#endif
|
2020-01-30 06:07:22 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* resume from D0I3 */
|
|
|
|
if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
|
2020-07-28 02:36:12 +08:00
|
|
|
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
|
|
|
/* power up links that were active before suspend */
|
|
|
|
list_for_each_entry(hlink, &bus->hlink_list, list) {
|
|
|
|
if (hlink->ref_count) {
|
|
|
|
ret = snd_hdac_ext_bus_link_power_up(hlink);
|
|
|
|
if (ret < 0) {
|
2022-06-17 05:53:39 +08:00
|
|
|
dev_err(sdev->dev,
|
2021-02-09 07:21:46 +08:00
|
|
|
"error %d in %s: failed to power up links",
|
2020-07-28 02:36:12 +08:00
|
|
|
ret, __func__);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set up CORB/RIRB buffers if was on before suspend */
|
|
|
|
if (bus->cmd_dma_state)
|
|
|
|
snd_hdac_bus_init_cmd_io(bus);
|
|
|
|
#endif
|
|
|
|
|
2020-01-30 06:07:22 +08:00
|
|
|
/* Set DSP power state */
|
2020-02-29 07:42:25 +08:00
|
|
|
ret = snd_sof_dsp_set_power_state(sdev, &target_state);
|
2020-01-30 06:07:22 +08:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
|
|
|
|
target_state.state, target_state.substate);
|
|
|
|
return ret;
|
|
|
|
}
|
2019-10-26 06:41:19 +08:00
|
|
|
|
2019-11-02 01:09:15 +08:00
|
|
|
/* restore L1SEN bit */
|
|
|
|
if (hda->l1_support_changed)
|
|
|
|
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
|
|
|
|
HDA_VS_INTEL_EM2,
|
|
|
|
HDA_VS_INTEL_EM2_L1SEN, 0);
|
|
|
|
|
2019-10-26 06:41:19 +08:00
|
|
|
/* restore and disable the system wakeup */
|
|
|
|
pci_restore_state(pci);
|
|
|
|
disable_irq_wake(pci->irq);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-04-13 00:08:49 +08:00
|
|
|
/* init hda controller. DSP cores will be powered up during fw boot */
|
2020-01-30 06:07:22 +08:00
|
|
|
ret = hda_resume(sdev, false);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2020-02-29 07:42:25 +08:00
|
|
|
return snd_sof_dsp_set_power_state(sdev, &target_state);
|
2019-04-13 00:08:49 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
|
|
|
|
{
|
2020-01-30 06:07:22 +08:00
|
|
|
const struct sof_dsp_power_state target_state = {
|
|
|
|
.state = SOF_DSP_PM_D0,
|
|
|
|
};
|
|
|
|
int ret;
|
|
|
|
|
2019-04-13 00:08:49 +08:00
|
|
|
/* init hda controller. DSP cores will be powered up during fw boot */
|
2020-01-30 06:07:22 +08:00
|
|
|
ret = hda_resume(sdev, true);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2020-02-29 07:42:25 +08:00
|
|
|
return snd_sof_dsp_set_power_state(sdev, &target_state);
|
2019-04-13 00:08:49 +08:00
|
|
|
}
|
|
|
|
|
2019-07-02 21:24:28 +08:00
|
|
|
int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
|
|
|
|
{
|
|
|
|
struct hdac_bus *hbus = sof_to_bus(sdev);
|
|
|
|
|
|
|
|
if (hbus->codec_powered) {
|
|
|
|
dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
|
|
|
|
(unsigned int)hbus->codec_powered);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-07-22 22:13:50 +08:00
|
|
|
int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
|
2019-04-13 00:08:49 +08:00
|
|
|
{
|
2021-01-28 17:23:45 +08:00
|
|
|
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
|
2020-01-30 06:07:22 +08:00
|
|
|
const struct sof_dsp_power_state target_state = {
|
|
|
|
.state = SOF_DSP_PM_D3,
|
|
|
|
};
|
|
|
|
int ret;
|
|
|
|
|
2021-01-28 17:23:45 +08:00
|
|
|
/* cancel any attempt for DSP D0I3 */
|
|
|
|
cancel_delayed_work_sync(&hda->d0i3_work);
|
|
|
|
|
2019-04-13 00:08:49 +08:00
|
|
|
/* stop hda controller and power dsp off */
|
2020-01-30 06:07:22 +08:00
|
|
|
ret = hda_suspend(sdev, true);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2020-02-29 07:42:25 +08:00
|
|
|
return snd_sof_dsp_set_power_state(sdev, &target_state);
|
2019-04-13 00:08:49 +08:00
|
|
|
}
|
|
|
|
|
2020-01-30 06:07:22 +08:00
|
|
|
int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
|
2019-04-13 00:08:49 +08:00
|
|
|
{
|
2019-11-02 01:09:15 +08:00
|
|
|
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
|
2019-04-13 00:08:49 +08:00
|
|
|
struct hdac_bus *bus = sof_to_bus(sdev);
|
2019-10-26 06:41:19 +08:00
|
|
|
struct pci_dev *pci = to_pci_dev(sdev->dev);
|
2020-01-30 06:07:22 +08:00
|
|
|
const struct sof_dsp_power_state target_dsp_state = {
|
|
|
|
.state = target_state,
|
|
|
|
.substate = target_state == SOF_DSP_PM_D0 ?
|
|
|
|
SOF_HDA_DSP_PM_D0I3 : 0,
|
|
|
|
};
|
2019-04-13 00:08:49 +08:00
|
|
|
int ret;
|
|
|
|
|
2020-01-30 06:07:25 +08:00
|
|
|
/* cancel any attempt for DSP D0I3 */
|
|
|
|
cancel_delayed_work_sync(&hda->d0i3_work);
|
|
|
|
|
2020-01-30 06:07:22 +08:00
|
|
|
if (target_state == SOF_DSP_PM_D0) {
|
|
|
|
/* Set DSP power state */
|
2020-02-29 07:42:25 +08:00
|
|
|
ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
|
2020-01-30 06:07:22 +08:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
|
|
|
|
target_dsp_state.state,
|
|
|
|
target_dsp_state.substate);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-11-02 01:09:15 +08:00
|
|
|
/* enable L1SEN to make sure the system can enter S0Ix */
|
|
|
|
hda->l1_support_changed =
|
|
|
|
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
|
|
|
|
HDA_VS_INTEL_EM2,
|
|
|
|
HDA_VS_INTEL_EM2_L1SEN,
|
|
|
|
HDA_VS_INTEL_EM2_L1SEN);
|
|
|
|
|
2020-07-28 02:36:12 +08:00
|
|
|
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
|
|
|
/* stop the CORB/RIRB DMA if it is On */
|
|
|
|
if (bus->cmd_dma_state)
|
|
|
|
snd_hdac_bus_stop_cmd_io(bus);
|
|
|
|
|
|
|
|
/* no link can be powered in s0ix state */
|
|
|
|
ret = snd_hdac_ext_bus_link_power_down_all(bus);
|
|
|
|
if (ret < 0) {
|
2022-06-17 05:53:39 +08:00
|
|
|
dev_err(sdev->dev,
|
2020-07-28 02:36:12 +08:00
|
|
|
"error %d in %s: failed to power down links",
|
|
|
|
ret, __func__);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2019-10-26 06:41:19 +08:00
|
|
|
/* enable the system waking up via IPC IRQ */
|
|
|
|
enable_irq_wake(pci->irq);
|
|
|
|
pci_save_state(pci);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-04-13 00:08:49 +08:00
|
|
|
/* stop hda controller and power dsp off */
|
2019-07-22 22:13:50 +08:00
|
|
|
ret = hda_suspend(sdev, false);
|
2019-04-13 00:08:49 +08:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(bus->dev, "error: suspending dsp\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-02-29 07:42:25 +08:00
|
|
|
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
|
2019-04-13 00:08:49 +08:00
|
|
|
}
|
2019-05-01 07:09:31 +08:00
|
|
|
|
2021-03-23 00:37:24 +08:00
|
|
|
int hda_dsp_shutdown(struct snd_sof_dev *sdev)
|
|
|
|
{
|
|
|
|
sdev->system_suspend_target = SOF_SUSPEND_S3;
|
|
|
|
return snd_sof_suspend(sdev->dev);
|
|
|
|
}
|
|
|
|
|
2019-06-13 01:23:38 +08:00
|
|
|
int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
|
2019-05-01 07:09:31 +08:00
|
|
|
{
|
2022-04-22 04:31:57 +08:00
|
|
|
int ret;
|
2019-07-22 22:14:00 +08:00
|
|
|
|
2022-04-22 04:31:57 +08:00
|
|
|
/* make sure all DAI resources are freed */
|
|
|
|
ret = hda_dsp_dais_suspend(sdev);
|
|
|
|
if (ret < 0)
|
|
|
|
dev_warn(sdev->dev, "%s: failure in hda_dsp_dais_suspend\n", __func__);
|
2019-07-22 22:14:00 +08:00
|
|
|
|
2022-04-22 04:31:57 +08:00
|
|
|
return ret;
|
2019-05-01 07:09:31 +08:00
|
|
|
}
|
2020-01-30 06:07:25 +08:00
|
|
|
|
|
|
|
void hda_dsp_d0i3_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct sof_intel_hda_dev *hdev = container_of(work,
|
|
|
|
struct sof_intel_hda_dev,
|
|
|
|
d0i3_work.work);
|
|
|
|
struct hdac_bus *bus = &hdev->hbus.core;
|
|
|
|
struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
|
2021-02-09 07:21:48 +08:00
|
|
|
struct sof_dsp_power_state target_state = {
|
|
|
|
.state = SOF_DSP_PM_D0,
|
|
|
|
.substate = SOF_HDA_DSP_PM_D0I3,
|
|
|
|
};
|
2020-01-30 06:07:25 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* DSP can enter D0I3 iff only D0I3-compatible streams are active */
|
2021-02-09 07:21:48 +08:00
|
|
|
if (!snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
|
|
|
|
/* remain in D0I0 */
|
2020-01-30 06:07:25 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
/* This can fail but error cannot be propagated */
|
2020-02-29 07:42:25 +08:00
|
|
|
ret = snd_sof_dsp_set_power_state(sdev, &target_state);
|
2020-01-30 06:07:25 +08:00
|
|
|
if (ret < 0)
|
|
|
|
dev_err_ratelimited(sdev->dev,
|
|
|
|
"error: failed to set DSP state %d substate %d\n",
|
|
|
|
target_state.state, target_state.substate);
|
|
|
|
}
|
2021-11-20 03:26:16 +08:00
|
|
|
|
|
|
|
int hda_dsp_core_get(struct snd_sof_dev *sdev, int core)
|
|
|
|
{
|
2022-06-10 16:35:48 +08:00
|
|
|
const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
|
2021-11-20 03:26:16 +08:00
|
|
|
int ret, ret1;
|
|
|
|
|
|
|
|
/* power up core */
|
|
|
|
ret = hda_dsp_enable_core(sdev, BIT(core));
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(sdev->dev, "failed to power up core %d with err: %d\n",
|
|
|
|
core, ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* No need to send IPC for primary core or if FW boot is not complete */
|
|
|
|
if (sdev->fw_state != SOF_FW_BOOT_COMPLETE || core == SOF_DSP_PRIMARY_CORE)
|
|
|
|
return 0;
|
|
|
|
|
2022-06-10 16:35:48 +08:00
|
|
|
/* No need to continue the set_core_state ops is not available */
|
|
|
|
if (!pm_ops->set_core_state)
|
|
|
|
return 0;
|
|
|
|
|
2021-11-20 03:26:16 +08:00
|
|
|
/* Now notify DSP for secondary cores */
|
2022-06-10 16:35:48 +08:00
|
|
|
ret = pm_ops->set_core_state(sdev, core, true);
|
2021-11-20 03:26:16 +08:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(sdev->dev, "failed to enable secondary core '%d' failed with %d\n",
|
|
|
|
core, ret);
|
|
|
|
goto power_down;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
power_down:
|
|
|
|
/* power down core if it is host managed and return the original error if this fails too */
|
|
|
|
ret1 = hda_dsp_core_reset_power_down(sdev, BIT(core));
|
|
|
|
if (ret1 < 0)
|
|
|
|
dev_err(sdev->dev, "failed to power down core: %d with err: %d\n", core, ret1);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|