License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2007-03-01 15:35:04 +08:00
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/* pci.c: UltraSparc PCI controller support.
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2005-04-17 06:20:36 +08:00
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*
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* Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
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* Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
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* Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
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2007-03-01 15:35:04 +08:00
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*
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* OF tree based PCI bus probing taken from the PowerPC port
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* with minor modifications, see there for credits.
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2005-04-17 06:20:36 +08:00
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*/
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2011-07-23 01:18:16 +08:00
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#include <linux/export.h>
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2005-04-17 06:20:36 +08:00
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/sched.h>
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#include <linux/capability.h>
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#include <linux/errno.h>
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2007-05-08 15:43:56 +08:00
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#include <linux/pci.h>
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[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 09:41:02 +08:00
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#include <linux/msi.h>
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#include <linux/irq.h>
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2005-04-17 06:20:36 +08:00
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#include <linux/init.h>
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2008-08-30 15:36:11 +08:00
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#include <linux/of.h>
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#include <linux/of_device.h>
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2020-06-09 12:32:42 +08:00
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#include <linux/pgtable.h>
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2005-04-17 06:20:36 +08:00
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2016-12-25 03:46:01 +08:00
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#include <linux/uaccess.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/irq.h>
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2006-06-22 09:18:47 +08:00
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#include <asm/prom.h>
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2007-03-05 04:53:19 +08:00
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#include <asm/apb.h>
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2005-04-17 06:20:36 +08:00
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2007-03-01 15:38:38 +08:00
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#include "pci_impl.h"
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2014-05-17 05:25:58 +08:00
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#include "kernel.h"
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2007-03-01 15:38:38 +08:00
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2005-04-17 06:20:36 +08:00
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/* List of all PCI controllers found in the system. */
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2007-05-08 14:06:27 +08:00
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struct pci_pbm_info *pci_pbm_root = NULL;
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2005-04-17 06:20:36 +08:00
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2007-05-08 14:49:01 +08:00
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/* Each PBM found gets a unique index. */
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int pci_num_pbms = 0;
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2005-04-17 06:20:36 +08:00
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volatile int pci_poke_in_progress;
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volatile int pci_poke_cpu = -1;
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volatile int pci_poke_faulted;
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static DEFINE_SPINLOCK(pci_poke_lock);
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void pci_config_read8(u8 *addr, u8 *ret)
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{
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unsigned long flags;
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u8 byte;
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spin_lock_irqsave(&pci_poke_lock, flags);
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pci_poke_cpu = smp_processor_id();
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pci_poke_in_progress = 1;
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pci_poke_faulted = 0;
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__asm__ __volatile__("membar #Sync\n\t"
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"lduba [%1] %2, %0\n\t"
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"membar #Sync"
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: "=r" (byte)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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pci_poke_in_progress = 0;
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pci_poke_cpu = -1;
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if (!pci_poke_faulted)
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*ret = byte;
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spin_unlock_irqrestore(&pci_poke_lock, flags);
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}
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void pci_config_read16(u16 *addr, u16 *ret)
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{
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unsigned long flags;
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u16 word;
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spin_lock_irqsave(&pci_poke_lock, flags);
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pci_poke_cpu = smp_processor_id();
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pci_poke_in_progress = 1;
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pci_poke_faulted = 0;
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__asm__ __volatile__("membar #Sync\n\t"
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"lduha [%1] %2, %0\n\t"
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"membar #Sync"
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: "=r" (word)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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pci_poke_in_progress = 0;
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pci_poke_cpu = -1;
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if (!pci_poke_faulted)
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*ret = word;
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spin_unlock_irqrestore(&pci_poke_lock, flags);
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}
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void pci_config_read32(u32 *addr, u32 *ret)
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{
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unsigned long flags;
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u32 dword;
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spin_lock_irqsave(&pci_poke_lock, flags);
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pci_poke_cpu = smp_processor_id();
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pci_poke_in_progress = 1;
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pci_poke_faulted = 0;
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__asm__ __volatile__("membar #Sync\n\t"
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"lduwa [%1] %2, %0\n\t"
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"membar #Sync"
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: "=r" (dword)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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pci_poke_in_progress = 0;
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pci_poke_cpu = -1;
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if (!pci_poke_faulted)
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*ret = dword;
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spin_unlock_irqrestore(&pci_poke_lock, flags);
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}
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void pci_config_write8(u8 *addr, u8 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&pci_poke_lock, flags);
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pci_poke_cpu = smp_processor_id();
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pci_poke_in_progress = 1;
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pci_poke_faulted = 0;
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__asm__ __volatile__("membar #Sync\n\t"
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"stba %0, [%1] %2\n\t"
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"membar #Sync"
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: /* no outputs */
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: "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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pci_poke_in_progress = 0;
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pci_poke_cpu = -1;
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spin_unlock_irqrestore(&pci_poke_lock, flags);
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}
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void pci_config_write16(u16 *addr, u16 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&pci_poke_lock, flags);
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pci_poke_cpu = smp_processor_id();
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pci_poke_in_progress = 1;
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pci_poke_faulted = 0;
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__asm__ __volatile__("membar #Sync\n\t"
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"stha %0, [%1] %2\n\t"
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"membar #Sync"
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: /* no outputs */
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: "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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pci_poke_in_progress = 0;
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pci_poke_cpu = -1;
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spin_unlock_irqrestore(&pci_poke_lock, flags);
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}
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void pci_config_write32(u32 *addr, u32 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&pci_poke_lock, flags);
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pci_poke_cpu = smp_processor_id();
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pci_poke_in_progress = 1;
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pci_poke_faulted = 0;
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__asm__ __volatile__("membar #Sync\n\t"
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"stwa %0, [%1] %2\n\t"
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"membar #Sync"
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: /* no outputs */
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: "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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pci_poke_in_progress = 0;
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pci_poke_cpu = -1;
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spin_unlock_irqrestore(&pci_poke_lock, flags);
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}
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2007-05-22 16:24:14 +08:00
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static int ofpci_verbose;
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static int __init ofpci_debug(char *str)
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{
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int val = 0;
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get_option(&str, &val);
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if (val)
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ofpci_verbose = 1;
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return 1;
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}
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__setup("ofpci_debug=", ofpci_debug);
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2007-03-01 15:35:04 +08:00
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static unsigned long pci_parse_of_flags(u32 addr0)
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{
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unsigned long flags = 0;
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if (addr0 & 0x02000000) {
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flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
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flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
|
2015-10-21 00:36:53 +08:00
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if (addr0 & 0x01000000)
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flags |= IORESOURCE_MEM_64
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| PCI_BASE_ADDRESS_MEM_TYPE_64;
|
2007-03-01 15:35:04 +08:00
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if (addr0 & 0x40000000)
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flags |= IORESOURCE_PREFETCH
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| PCI_BASE_ADDRESS_MEM_PREFETCH;
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} else if (addr0 & 0x01000000)
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flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
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return flags;
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}
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/* The of_device layer has translated all of the assigned-address properties
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* into physical address resources, we only have to figure out the register
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* mapping.
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*/
|
2010-07-23 06:04:30 +08:00
|
|
|
static void pci_parse_of_addrs(struct platform_device *op,
|
2007-03-01 15:35:04 +08:00
|
|
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struct device_node *node,
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struct pci_dev *dev)
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{
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struct resource *op_res;
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const u32 *addrs;
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int proplen;
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addrs = of_get_property(node, "assigned-addresses", &proplen);
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if (!addrs)
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return;
|
2007-05-22 16:24:14 +08:00
|
|
|
if (ofpci_verbose)
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(dev, " parse addresses (%d bytes) @ %p\n",
|
|
|
|
|
proplen, addrs);
|
2007-03-01 15:35:04 +08:00
|
|
|
op_res = &op->resource[0];
|
|
|
|
|
for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
|
|
|
|
|
struct resource *res;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
flags = pci_parse_of_flags(addrs[0]);
|
|
|
|
|
if (!flags)
|
|
|
|
|
continue;
|
|
|
|
|
i = addrs[0] & 0xff;
|
2007-05-22 16:24:14 +08:00
|
|
|
if (ofpci_verbose)
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(dev, " start: %llx, end: %llx, i: %x\n",
|
|
|
|
|
op_res->start, op_res->end, i);
|
2007-03-01 15:35:04 +08:00
|
|
|
|
|
|
|
|
if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
|
|
|
|
|
res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
|
|
|
|
|
} else if (i == dev->rom_base_reg) {
|
|
|
|
|
res = &dev->resource[PCI_ROM_RESOURCE];
|
2015-08-11 11:07:06 +08:00
|
|
|
flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
|
2007-03-01 15:35:04 +08:00
|
|
|
} else {
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_err(dev, "bad cfg reg num 0x%x\n", i);
|
2007-03-01 15:35:04 +08:00
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
res->start = op_res->start;
|
|
|
|
|
res->end = op_res->end;
|
|
|
|
|
res->flags = flags;
|
|
|
|
|
res->name = pci_name(dev);
|
2018-04-22 03:35:42 +08:00
|
|
|
|
|
|
|
|
pci_info(dev, "reg 0x%x: %pR\n", i, res);
|
2007-03-01 15:35:04 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-12 08:57:05 +08:00
|
|
|
static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
|
|
|
|
|
void *stc, void *host_controller,
|
|
|
|
|
struct platform_device *op,
|
|
|
|
|
int numa_node)
|
|
|
|
|
{
|
|
|
|
|
sd->iommu = iommu;
|
|
|
|
|
sd->stc = stc;
|
|
|
|
|
sd->host_controller = host_controller;
|
|
|
|
|
sd->op = op;
|
|
|
|
|
sd->numa_node = numa_node;
|
|
|
|
|
}
|
|
|
|
|
|
2008-09-12 14:57:40 +08:00
|
|
|
static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
|
|
|
|
|
struct device_node *node,
|
|
|
|
|
struct pci_bus *bus, int devfn)
|
2007-03-01 15:35:04 +08:00
|
|
|
{
|
|
|
|
|
struct dev_archdata *sd;
|
2010-07-23 06:04:30 +08:00
|
|
|
struct platform_device *op;
|
2007-03-01 15:35:04 +08:00
|
|
|
struct pci_dev *dev;
|
2007-03-05 04:53:19 +08:00
|
|
|
u32 class;
|
2007-03-01 15:35:04 +08:00
|
|
|
|
2013-05-25 21:48:31 +08:00
|
|
|
dev = pci_alloc_dev(bus);
|
2007-03-01 15:35:04 +08:00
|
|
|
if (!dev)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
2016-04-12 08:57:05 +08:00
|
|
|
op = of_find_device_by_node(node);
|
2007-03-01 15:35:04 +08:00
|
|
|
sd = &dev->dev.archdata;
|
2016-04-12 08:57:05 +08:00
|
|
|
pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
|
|
|
|
|
pbm->numa_node);
|
2008-08-30 13:42:34 +08:00
|
|
|
sd = &op->dev.archdata;
|
2007-07-28 13:39:14 +08:00
|
|
|
sd->iommu = pbm->iommu;
|
|
|
|
|
sd->stc = &pbm->stc;
|
2008-03-19 19:52:48 +08:00
|
|
|
sd->numa_node = pbm->numa_node;
|
2007-07-28 13:39:14 +08:00
|
|
|
|
2018-11-17 05:06:58 +08:00
|
|
|
if (of_node_name_eq(node, "ebus"))
|
2008-08-30 13:42:34 +08:00
|
|
|
of_propagate_archdata(op);
|
|
|
|
|
|
2007-05-22 16:24:14 +08:00
|
|
|
if (ofpci_verbose)
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(bus," create device, devfn: %x, type: %s\n",
|
2018-11-17 05:06:59 +08:00
|
|
|
devfn, of_node_get_device_type(node));
|
2007-03-01 15:35:04 +08:00
|
|
|
|
|
|
|
|
dev->sysdata = node;
|
|
|
|
|
dev->dev.parent = bus->bridge;
|
|
|
|
|
dev->dev.bus = &pci_bus_type;
|
2011-04-11 09:37:07 +08:00
|
|
|
dev->dev.of_node = of_node_get(node);
|
2007-03-01 15:35:04 +08:00
|
|
|
dev->devfn = devfn;
|
|
|
|
|
dev->multifunction = 0; /* maybe a lie? */
|
2010-02-18 08:42:08 +08:00
|
|
|
set_pcie_port_type(dev);
|
|
|
|
|
|
2015-07-17 17:16:32 +08:00
|
|
|
pci_dev_assign_slot(dev);
|
2008-05-01 16:12:40 +08:00
|
|
|
dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
|
|
|
|
|
dev->device = of_getintprop_default(node, "device-id", 0xffff);
|
|
|
|
|
dev->subsystem_vendor =
|
|
|
|
|
of_getintprop_default(node, "subsystem-vendor-id", 0);
|
|
|
|
|
dev->subsystem_device =
|
|
|
|
|
of_getintprop_default(node, "subsystem-id", 0);
|
|
|
|
|
|
|
|
|
|
dev->cfg_size = pci_cfg_space_size(dev);
|
|
|
|
|
|
|
|
|
|
/* We can't actually use the firmware value, we have
|
|
|
|
|
* to read what is in the register right now. One
|
|
|
|
|
* reason is that in the case of IDE interfaces the
|
|
|
|
|
* firmware can sample the value before the the IDE
|
|
|
|
|
* interface is programmed into native mode.
|
|
|
|
|
*/
|
|
|
|
|
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
|
|
|
|
|
dev->class = class >> 8;
|
|
|
|
|
dev->revision = class & 0xff;
|
|
|
|
|
|
2008-05-02 12:02:41 +08:00
|
|
|
dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
|
2008-05-01 16:12:40 +08:00
|
|
|
dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
|
2007-03-13 10:40:26 +08:00
|
|
|
|
2007-05-03 08:31:36 +08:00
|
|
|
/* I have seen IDE devices which will not respond to
|
|
|
|
|
* the bmdma simplex check reads if bus mastering is
|
|
|
|
|
* disabled.
|
|
|
|
|
*/
|
|
|
|
|
if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
|
|
|
|
|
pci_set_master(dev);
|
|
|
|
|
|
2013-05-21 07:15:20 +08:00
|
|
|
dev->current_state = PCI_UNKNOWN; /* unknown power state */
|
2007-03-01 15:35:04 +08:00
|
|
|
dev->error_state = pci_channel_io_normal;
|
2010-02-18 08:42:08 +08:00
|
|
|
dev->dma_mask = 0xffffffff;
|
2007-03-01 15:35:04 +08:00
|
|
|
|
2018-11-17 05:06:58 +08:00
|
|
|
if (of_node_name_eq(node, "pci")) {
|
2008-05-01 16:12:40 +08:00
|
|
|
/* a PCI-PCI bridge */
|
2007-03-01 15:35:04 +08:00
|
|
|
dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
|
|
|
|
|
dev->rom_base_reg = PCI_ROM_ADDRESS1;
|
2018-11-17 05:06:59 +08:00
|
|
|
} else if (of_node_is_type(node, "cardbus")) {
|
2008-05-01 16:12:40 +08:00
|
|
|
dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
|
2007-03-01 15:35:04 +08:00
|
|
|
} else {
|
2008-05-01 16:12:40 +08:00
|
|
|
dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
|
|
|
|
|
dev->rom_base_reg = PCI_ROM_ADDRESS;
|
2007-03-01 15:35:04 +08:00
|
|
|
|
2010-06-19 01:09:58 +08:00
|
|
|
dev->irq = sd->op->archdata.irqs[0];
|
2008-05-01 16:12:40 +08:00
|
|
|
if (dev->irq == 0xffffffff)
|
|
|
|
|
dev->irq = PCI_IRQ_NONE;
|
2007-03-01 15:35:04 +08:00
|
|
|
}
|
2008-05-01 16:12:40 +08:00
|
|
|
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
|
|
|
|
|
dev->vendor, dev->device, dev->hdr_type, dev->class);
|
|
|
|
|
|
2007-03-01 15:35:04 +08:00
|
|
|
pci_parse_of_addrs(sd->op, node, dev);
|
|
|
|
|
|
2007-05-22 16:24:14 +08:00
|
|
|
if (ofpci_verbose)
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(dev, " adding to system ...\n");
|
2007-03-01 15:35:04 +08:00
|
|
|
|
|
|
|
|
pci_device_add(dev, bus);
|
|
|
|
|
|
|
|
|
|
return dev;
|
|
|
|
|
}
|
|
|
|
|
|
2013-01-01 23:02:33 +08:00
|
|
|
static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
|
2007-03-05 04:53:19 +08:00
|
|
|
{
|
|
|
|
|
u32 idx, first, last;
|
|
|
|
|
|
|
|
|
|
first = 8;
|
|
|
|
|
last = 0;
|
|
|
|
|
for (idx = 0; idx < 8; idx++) {
|
|
|
|
|
if ((map & (1 << idx)) != 0) {
|
|
|
|
|
if (first > idx)
|
|
|
|
|
first = idx;
|
|
|
|
|
if (last < idx)
|
|
|
|
|
last = idx;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*first_p = first;
|
|
|
|
|
*last_p = last;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
|
|
|
|
|
* a proper 'ranges' property.
|
|
|
|
|
*/
|
2013-01-01 23:02:33 +08:00
|
|
|
static void apb_fake_ranges(struct pci_dev *dev,
|
|
|
|
|
struct pci_bus *bus,
|
|
|
|
|
struct pci_pbm_info *pbm)
|
2007-03-05 04:53:19 +08:00
|
|
|
{
|
2012-03-17 07:48:24 +08:00
|
|
|
struct pci_bus_region region;
|
2007-03-05 04:53:19 +08:00
|
|
|
struct resource *res;
|
|
|
|
|
u32 first, last;
|
|
|
|
|
u8 map;
|
|
|
|
|
|
|
|
|
|
pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
|
|
|
|
|
apb_calc_first_last(map, &first, &last);
|
|
|
|
|
res = bus->resource[0];
|
|
|
|
|
res->flags = IORESOURCE_IO;
|
2012-03-17 07:48:24 +08:00
|
|
|
region.start = (first << 21);
|
|
|
|
|
region.end = (last << 21) + ((1 << 21) - 1);
|
PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev
These interfaces:
pcibios_resource_to_bus(struct pci_dev *dev, *bus_region, *resource)
pcibios_bus_to_resource(struct pci_dev *dev, *resource, *bus_region)
took a pci_dev, but they really depend only on the pci_bus. And we want to
use them in resource allocation paths where we have the bus but not a
device, so this patch converts them to take the pci_bus instead of the
pci_dev:
pcibios_resource_to_bus(struct pci_bus *bus, *bus_region, *resource)
pcibios_bus_to_resource(struct pci_bus *bus, *resource, *bus_region)
In fact, with standard PCI-PCI bridges, they only depend on the host
bridge, because that's the only place address translation occurs, but
we aren't going that far yet.
[bhelgaas: changelog]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-10 14:54:40 +08:00
|
|
|
pcibios_bus_to_resource(dev->bus, res, ®ion);
|
2007-03-05 04:53:19 +08:00
|
|
|
|
|
|
|
|
pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
|
|
|
|
|
apb_calc_first_last(map, &first, &last);
|
|
|
|
|
res = bus->resource[1];
|
|
|
|
|
res->flags = IORESOURCE_MEM;
|
2013-10-19 04:28:29 +08:00
|
|
|
region.start = (first << 29);
|
|
|
|
|
region.end = (last << 29) + ((1 << 29) - 1);
|
PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev
These interfaces:
pcibios_resource_to_bus(struct pci_dev *dev, *bus_region, *resource)
pcibios_bus_to_resource(struct pci_dev *dev, *resource, *bus_region)
took a pci_dev, but they really depend only on the pci_bus. And we want to
use them in resource allocation paths where we have the bus but not a
device, so this patch converts them to take the pci_bus instead of the
pci_dev:
pcibios_resource_to_bus(struct pci_bus *bus, *bus_region, *resource)
pcibios_bus_to_resource(struct pci_bus *bus, *resource, *bus_region)
In fact, with standard PCI-PCI bridges, they only depend on the host
bridge, because that's the only place address translation occurs, but
we aren't going that far yet.
[bhelgaas: changelog]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-10 14:54:40 +08:00
|
|
|
pcibios_bus_to_resource(dev->bus, res, ®ion);
|
2007-03-05 04:53:19 +08:00
|
|
|
}
|
|
|
|
|
|
2013-01-01 23:02:33 +08:00
|
|
|
static void pci_of_scan_bus(struct pci_pbm_info *pbm,
|
|
|
|
|
struct device_node *node,
|
|
|
|
|
struct pci_bus *bus);
|
2007-03-01 15:35:04 +08:00
|
|
|
|
|
|
|
|
#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
|
|
|
|
|
|
2013-01-01 23:02:33 +08:00
|
|
|
static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
|
|
|
|
|
struct device_node *node,
|
|
|
|
|
struct pci_dev *dev)
|
2007-03-01 15:35:04 +08:00
|
|
|
{
|
|
|
|
|
struct pci_bus *bus;
|
|
|
|
|
const u32 *busrange, *ranges;
|
2007-03-05 04:53:19 +08:00
|
|
|
int len, i, simba;
|
2012-03-17 07:48:24 +08:00
|
|
|
struct pci_bus_region region;
|
2007-03-01 15:35:04 +08:00
|
|
|
struct resource *res;
|
|
|
|
|
unsigned int flags;
|
|
|
|
|
u64 size;
|
|
|
|
|
|
2007-05-22 16:24:14 +08:00
|
|
|
if (ofpci_verbose)
|
2018-11-17 05:06:54 +08:00
|
|
|
pci_info(dev, "of_scan_pci_bridge(%pOF)\n", node);
|
2007-03-01 15:35:04 +08:00
|
|
|
|
|
|
|
|
/* parse bus-range property */
|
|
|
|
|
busrange = of_get_property(node, "bus-range", &len);
|
|
|
|
|
if (busrange == NULL || len != 8) {
|
2018-11-17 05:06:54 +08:00
|
|
|
pci_info(dev, "Can't get bus-range for PCI-PCI bridge %pOF\n",
|
|
|
|
|
node);
|
2007-03-01 15:35:04 +08:00
|
|
|
return;
|
|
|
|
|
}
|
2014-08-13 14:22:39 +08:00
|
|
|
|
|
|
|
|
if (ofpci_verbose)
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(dev, " Bridge bus range [%u --> %u]\n",
|
|
|
|
|
busrange[0], busrange[1]);
|
2014-08-13 14:22:39 +08:00
|
|
|
|
2007-03-01 15:35:04 +08:00
|
|
|
ranges = of_get_property(node, "ranges", &len);
|
2007-03-05 04:53:19 +08:00
|
|
|
simba = 0;
|
2007-03-01 15:35:04 +08:00
|
|
|
if (ranges == NULL) {
|
2007-03-29 16:50:16 +08:00
|
|
|
const char *model = of_get_property(node, "model", NULL);
|
2007-06-08 12:59:44 +08:00
|
|
|
if (model && !strcmp(model, "SUNW,simba"))
|
2007-03-05 04:53:19 +08:00
|
|
|
simba = 1;
|
2007-03-01 15:35:04 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
|
|
|
|
|
if (!bus) {
|
2018-11-17 05:06:54 +08:00
|
|
|
pci_err(dev, "Failed to create pci bus for %pOF\n",
|
|
|
|
|
node);
|
2007-03-01 15:35:04 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bus->primary = dev->bus->number;
|
2012-05-18 09:51:12 +08:00
|
|
|
pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
|
2007-03-01 15:35:04 +08:00
|
|
|
bus->bridge_ctl = 0;
|
|
|
|
|
|
2014-08-13 14:22:39 +08:00
|
|
|
if (ofpci_verbose)
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(dev, " Bridge ranges[%p] simba[%d]\n",
|
|
|
|
|
ranges, simba);
|
2014-08-13 14:22:39 +08:00
|
|
|
|
2007-03-05 04:53:19 +08:00
|
|
|
/* parse ranges property, or cook one up by hand for Simba */
|
2007-03-01 15:35:04 +08:00
|
|
|
/* PCI #address-cells == 3 and #size-cells == 2 always */
|
|
|
|
|
res = &dev->resource[PCI_BRIDGE_RESOURCES];
|
|
|
|
|
for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
|
|
|
|
|
res->flags = 0;
|
|
|
|
|
bus->resource[i] = res;
|
|
|
|
|
++res;
|
|
|
|
|
}
|
2007-03-05 04:53:19 +08:00
|
|
|
if (simba) {
|
|
|
|
|
apb_fake_ranges(dev, bus, pbm);
|
2007-06-08 12:59:44 +08:00
|
|
|
goto after_ranges;
|
|
|
|
|
} else if (ranges == NULL) {
|
2012-07-10 03:39:52 +08:00
|
|
|
pci_read_bridge_bases(bus);
|
2007-06-08 12:59:44 +08:00
|
|
|
goto after_ranges;
|
2007-03-05 04:53:19 +08:00
|
|
|
}
|
2007-03-01 15:35:04 +08:00
|
|
|
i = 1;
|
|
|
|
|
for (; len >= 32; len -= 32, ranges += 8) {
|
2014-08-13 14:22:39 +08:00
|
|
|
u64 start;
|
|
|
|
|
|
|
|
|
|
if (ofpci_verbose)
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(dev, " RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:"
|
|
|
|
|
"%08x:%08x]\n",
|
|
|
|
|
ranges[0], ranges[1], ranges[2], ranges[3],
|
|
|
|
|
ranges[4], ranges[5], ranges[6], ranges[7]);
|
2014-08-13 14:22:39 +08:00
|
|
|
|
2007-03-01 15:35:04 +08:00
|
|
|
flags = pci_parse_of_flags(ranges[0]);
|
|
|
|
|
size = GET_64BIT(ranges, 6);
|
|
|
|
|
if (flags == 0 || size == 0)
|
|
|
|
|
continue;
|
2014-08-13 14:27:01 +08:00
|
|
|
|
|
|
|
|
/* On PCI-Express systems, PCI bridges that have no devices downstream
|
|
|
|
|
* have a bogus size value where the first 32-bit cell is 0xffffffff.
|
|
|
|
|
* This results in a bogus range where start + size overflows.
|
|
|
|
|
*
|
|
|
|
|
* Just skip these otherwise the kernel will complain when the resource
|
|
|
|
|
* tries to be claimed.
|
|
|
|
|
*/
|
|
|
|
|
if (size >> 32 == 0xffffffff)
|
|
|
|
|
continue;
|
|
|
|
|
|
2007-03-01 15:35:04 +08:00
|
|
|
if (flags & IORESOURCE_IO) {
|
|
|
|
|
res = bus->resource[0];
|
|
|
|
|
if (res->flags) {
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_err(dev, "ignoring extra I/O range"
|
2018-11-17 05:06:54 +08:00
|
|
|
" for bridge %pOF\n", node);
|
2007-03-01 15:35:04 +08:00
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_err(dev, "too many memory ranges"
|
2018-11-17 05:06:54 +08:00
|
|
|
" for bridge %pOF\n", node);
|
2007-03-01 15:35:04 +08:00
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
res = bus->resource[i];
|
|
|
|
|
++i;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
res->flags = flags;
|
2014-08-13 14:22:39 +08:00
|
|
|
region.start = start = GET_64BIT(ranges, 1);
|
2012-03-17 07:48:24 +08:00
|
|
|
region.end = region.start + size - 1;
|
2014-08-13 14:22:39 +08:00
|
|
|
|
|
|
|
|
if (ofpci_verbose)
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(dev, " Using flags[%08x] start[%016llx] size[%016llx]\n",
|
|
|
|
|
flags, start, size);
|
2014-08-13 14:22:39 +08:00
|
|
|
|
PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev
These interfaces:
pcibios_resource_to_bus(struct pci_dev *dev, *bus_region, *resource)
pcibios_bus_to_resource(struct pci_dev *dev, *resource, *bus_region)
took a pci_dev, but they really depend only on the pci_bus. And we want to
use them in resource allocation paths where we have the bus but not a
device, so this patch converts them to take the pci_bus instead of the
pci_dev:
pcibios_resource_to_bus(struct pci_bus *bus, *bus_region, *resource)
pcibios_bus_to_resource(struct pci_bus *bus, *resource, *bus_region)
In fact, with standard PCI-PCI bridges, they only depend on the host
bridge, because that's the only place address translation occurs, but
we aren't going that far yet.
[bhelgaas: changelog]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-10 14:54:40 +08:00
|
|
|
pcibios_bus_to_resource(dev->bus, res, ®ion);
|
2007-03-01 15:35:04 +08:00
|
|
|
}
|
2007-06-08 12:59:44 +08:00
|
|
|
after_ranges:
|
2007-03-01 15:35:04 +08:00
|
|
|
sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
|
|
|
|
|
bus->number);
|
2007-05-22 16:24:14 +08:00
|
|
|
if (ofpci_verbose)
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(dev, " bus name: %s\n", bus->name);
|
2007-03-01 15:35:04 +08:00
|
|
|
|
|
|
|
|
pci_of_scan_bus(pbm, node, bus);
|
|
|
|
|
}
|
|
|
|
|
|
2013-01-01 23:02:33 +08:00
|
|
|
static void pci_of_scan_bus(struct pci_pbm_info *pbm,
|
|
|
|
|
struct device_node *node,
|
|
|
|
|
struct pci_bus *bus)
|
2007-03-01 15:35:04 +08:00
|
|
|
{
|
|
|
|
|
struct device_node *child;
|
|
|
|
|
const u32 *reg;
|
2007-09-12 16:15:59 +08:00
|
|
|
int reglen, devfn, prev_devfn;
|
2007-03-01 15:35:04 +08:00
|
|
|
struct pci_dev *dev;
|
|
|
|
|
|
2007-05-22 16:24:14 +08:00
|
|
|
if (ofpci_verbose)
|
2018-11-17 05:06:54 +08:00
|
|
|
pci_info(bus, "scan_bus[%pOF] bus no %d\n",
|
|
|
|
|
node, bus->number);
|
2007-03-01 15:35:04 +08:00
|
|
|
|
2007-09-12 16:15:59 +08:00
|
|
|
prev_devfn = -1;
|
2020-07-28 10:28:17 +08:00
|
|
|
for_each_child_of_node(node, child) {
|
2007-05-22 16:24:14 +08:00
|
|
|
if (ofpci_verbose)
|
2018-11-17 05:06:54 +08:00
|
|
|
pci_info(bus, " * %pOF\n", child);
|
2007-03-01 15:35:04 +08:00
|
|
|
reg = of_get_property(child, "reg", ®len);
|
|
|
|
|
if (reg == NULL || reglen < 20)
|
|
|
|
|
continue;
|
2007-09-12 16:15:59 +08:00
|
|
|
|
2007-03-01 15:35:04 +08:00
|
|
|
devfn = (reg[0] >> 8) & 0xff;
|
|
|
|
|
|
2007-09-12 16:15:59 +08:00
|
|
|
/* This is a workaround for some device trees
|
|
|
|
|
* which list PCI devices twice. On the V100
|
|
|
|
|
* for example, device number 3 is listed twice.
|
|
|
|
|
* Once as "pm" and once again as "lomp".
|
|
|
|
|
*/
|
|
|
|
|
if (devfn == prev_devfn)
|
|
|
|
|
continue;
|
|
|
|
|
prev_devfn = devfn;
|
|
|
|
|
|
2007-03-01 15:35:04 +08:00
|
|
|
/* create a new pci_dev for this device */
|
2008-05-01 16:12:40 +08:00
|
|
|
dev = of_create_pci_dev(pbm, child, bus, devfn);
|
2007-03-01 15:35:04 +08:00
|
|
|
if (!dev)
|
|
|
|
|
continue;
|
2007-05-22 16:24:14 +08:00
|
|
|
if (ofpci_verbose)
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(dev, "dev header type: %x\n", dev->hdr_type);
|
2007-03-01 15:35:04 +08:00
|
|
|
|
2014-05-04 12:23:42 +08:00
|
|
|
if (pci_is_bridge(dev))
|
2007-03-01 15:35:04 +08:00
|
|
|
of_scan_pci_bridge(pbm, child, dev);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static ssize_t
|
|
|
|
|
show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
|
|
|
|
|
{
|
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
|
struct device_node *dp;
|
|
|
|
|
|
|
|
|
|
pdev = to_pci_dev(dev);
|
2010-04-14 07:12:29 +08:00
|
|
|
dp = pdev->dev.of_node;
|
2007-03-01 15:35:04 +08:00
|
|
|
|
2020-05-09 17:18:48 +08:00
|
|
|
return scnprintf(buf, PAGE_SIZE, "%pOF\n", dp);
|
2007-03-01 15:35:04 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
|
|
|
|
|
|
2013-01-01 23:02:33 +08:00
|
|
|
static void pci_bus_register_of_sysfs(struct pci_bus *bus)
|
2007-03-01 15:35:04 +08:00
|
|
|
{
|
|
|
|
|
struct pci_dev *dev;
|
2007-03-02 03:46:13 +08:00
|
|
|
struct pci_bus *child_bus;
|
2007-03-01 15:35:04 +08:00
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
|
|
|
|
/* we don't really care if we can create this file or
|
|
|
|
|
* not, but we need to assign the result of the call
|
|
|
|
|
* or the world will fall under alien invasion and
|
|
|
|
|
* everybody will be frozen on a spaceship ready to be
|
|
|
|
|
* eaten on alpha centauri by some green and jelly
|
|
|
|
|
* humanoid.
|
|
|
|
|
*/
|
|
|
|
|
err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
|
2011-02-27 15:40:02 +08:00
|
|
|
(void) err;
|
2007-03-01 15:35:04 +08:00
|
|
|
}
|
2007-03-02 03:46:13 +08:00
|
|
|
list_for_each_entry(child_bus, &bus->children, node)
|
|
|
|
|
pci_bus_register_of_sysfs(child_bus);
|
2007-03-01 15:35:04 +08:00
|
|
|
}
|
|
|
|
|
|
sparc/PCI: Request legacy VGA framebuffer only for VGA devices
Previously we unconditionally requested the legacy VGA framebuffer (bus
address 0xa0000-0xbffff) before we even know what PCI devices are present,
in these paths:
pci_fire_pbm_init, schizo_pbm_init, pci_sun4v_pbm_init, psycho_pbm_init_common
pci_determine_mem_io_space
pci_register_legacy_regions
p->start = mem_res->start + 0xa0000
request_resource(mem_res, p) # claim VGA framebuffer
pci_scan_one_pbm
pci_of_scan_bus # scan DT for PCI devices
pci_claim_bus_resources # claim PCI device BARs
If we found a PCI device with a BAR or bridge window that overlapped the
framebuffer area, we complained about not being able to claim the BAR,
e.g.,
pci 0000:00:01.0: can't claim BAR 8 [mem 0x1ff00000000-0x1ffbfffffff]: address conflict with Video RAM area [??? 0x1ff000a0000-0x1ff000bffff flags 0x80000000]
pci 0000:02:01.0: can't claim BAR 8 [mem 0x1ff00100000-0x1ff028fffff]: no compatible bridge window
pci 0000:03:0f.0: can't claim BAR 8 [mem 0x1ff00100000-0x1ff028fffff]: no compatible bridge window
pci 0000:04:04.0: can't claim BAR 1 [mem 0x1ff02808000-0x1ff02808fff]: no compatible bridge window
This may make the conflicting device unusable because we try not to enable
devices that have unassigned or conflicting BARs, e.g.,
qla1280 0000:04:04.0: can't ioremap BAR 1: [mem size 0x00001000]
qla1280: Unable to map I/O memory
If there is no VGA device in the same PCI segment, there's no reason to
reserve the framebuffer and there's no conflict. If there *is* a VGA
device in the same segment, both the VGA device and the device with an
overlapping BAR may respond to the framebuffer addresses, which may cause
bus errors.
Request the legacy framebuffer area only when we actually find a VGA
device. The fact that VGA devices use the legacy framebuffer even though
it's not reported in a BAR is not sparc-specific, so the reservation of
that area could be made more generic in the PCI core eventually.
Note that on some systems, e.g., Blade 100, we still report a conflict
between an ISA bridge (00:07.0) and a VGA device (00:13.0):
pci_bus 0000:00: root bus resource [mem 0x1ff00000000-0x1ffffffffff] (bus address [0x00000000-0xffffffff])
pci 0000:00:07.0: reg 0x14: [mem 0x1ff00000000-0x1ff000fffff]
pci 0000:00:13.0: can't claim VGA legacy [mem 0x1ff000a0000-0x1ff000bffff]: address conflict with 0000:00:07.0 [mem 0x1ff00000000-0x1ff000fffff]
This is probably harmless, but if the VGA device and something behind the
ISA bridge both responded to reads of the framebuffer, it would cause a bus
error.
Link: https://lkml.kernel.org/r/alpine.LRH.2.21.1804112323170.25495@math.ut.ee
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=117191#c35
Reported-by: Meelis Roos <mroos@linux.ee>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-04-10 21:47:34 +08:00
|
|
|
static void pci_claim_legacy_resources(struct pci_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
struct pci_bus_region region;
|
|
|
|
|
struct resource *p, *root, *conflict;
|
|
|
|
|
|
|
|
|
|
if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
p = kzalloc(sizeof(*p), GFP_KERNEL);
|
|
|
|
|
if (!p)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
p->name = "Video RAM area";
|
|
|
|
|
p->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
|
|
|
|
|
|
|
|
|
region.start = 0xa0000UL;
|
|
|
|
|
region.end = region.start + 0x1ffffUL;
|
|
|
|
|
pcibios_bus_to_resource(dev->bus, p, ®ion);
|
|
|
|
|
|
|
|
|
|
root = pci_find_parent_resource(dev, p);
|
|
|
|
|
if (!root) {
|
|
|
|
|
pci_info(dev, "can't claim VGA legacy %pR: no compatible bridge window\n", p);
|
|
|
|
|
goto err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
conflict = request_resource_conflict(root, p);
|
|
|
|
|
if (conflict) {
|
|
|
|
|
pci_info(dev, "can't claim VGA legacy %pR: address conflict with %s %pR\n",
|
|
|
|
|
p, conflict->name, conflict);
|
|
|
|
|
goto err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
pci_info(dev, "VGA legacy framebuffer %pR\n", p);
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
err:
|
|
|
|
|
kfree(p);
|
|
|
|
|
}
|
|
|
|
|
|
2014-08-13 14:29:09 +08:00
|
|
|
static void pci_claim_bus_resources(struct pci_bus *bus)
|
|
|
|
|
{
|
|
|
|
|
struct pci_bus *child_bus;
|
|
|
|
|
struct pci_dev *dev;
|
|
|
|
|
|
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
|
|
|
|
|
struct resource *r = &dev->resource[i];
|
|
|
|
|
|
|
|
|
|
if (r->parent || !r->start || !r->flags)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (ofpci_verbose)
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(dev, "Claiming Resource %d: %pR\n",
|
|
|
|
|
i, r);
|
2014-08-13 14:29:09 +08:00
|
|
|
|
2015-04-08 23:04:55 +08:00
|
|
|
pci_claim_resource(dev, i);
|
2014-08-13 14:29:09 +08:00
|
|
|
}
|
sparc/PCI: Request legacy VGA framebuffer only for VGA devices
Previously we unconditionally requested the legacy VGA framebuffer (bus
address 0xa0000-0xbffff) before we even know what PCI devices are present,
in these paths:
pci_fire_pbm_init, schizo_pbm_init, pci_sun4v_pbm_init, psycho_pbm_init_common
pci_determine_mem_io_space
pci_register_legacy_regions
p->start = mem_res->start + 0xa0000
request_resource(mem_res, p) # claim VGA framebuffer
pci_scan_one_pbm
pci_of_scan_bus # scan DT for PCI devices
pci_claim_bus_resources # claim PCI device BARs
If we found a PCI device with a BAR or bridge window that overlapped the
framebuffer area, we complained about not being able to claim the BAR,
e.g.,
pci 0000:00:01.0: can't claim BAR 8 [mem 0x1ff00000000-0x1ffbfffffff]: address conflict with Video RAM area [??? 0x1ff000a0000-0x1ff000bffff flags 0x80000000]
pci 0000:02:01.0: can't claim BAR 8 [mem 0x1ff00100000-0x1ff028fffff]: no compatible bridge window
pci 0000:03:0f.0: can't claim BAR 8 [mem 0x1ff00100000-0x1ff028fffff]: no compatible bridge window
pci 0000:04:04.0: can't claim BAR 1 [mem 0x1ff02808000-0x1ff02808fff]: no compatible bridge window
This may make the conflicting device unusable because we try not to enable
devices that have unassigned or conflicting BARs, e.g.,
qla1280 0000:04:04.0: can't ioremap BAR 1: [mem size 0x00001000]
qla1280: Unable to map I/O memory
If there is no VGA device in the same PCI segment, there's no reason to
reserve the framebuffer and there's no conflict. If there *is* a VGA
device in the same segment, both the VGA device and the device with an
overlapping BAR may respond to the framebuffer addresses, which may cause
bus errors.
Request the legacy framebuffer area only when we actually find a VGA
device. The fact that VGA devices use the legacy framebuffer even though
it's not reported in a BAR is not sparc-specific, so the reservation of
that area could be made more generic in the PCI core eventually.
Note that on some systems, e.g., Blade 100, we still report a conflict
between an ISA bridge (00:07.0) and a VGA device (00:13.0):
pci_bus 0000:00: root bus resource [mem 0x1ff00000000-0x1ffffffffff] (bus address [0x00000000-0xffffffff])
pci 0000:00:07.0: reg 0x14: [mem 0x1ff00000000-0x1ff000fffff]
pci 0000:00:13.0: can't claim VGA legacy [mem 0x1ff000a0000-0x1ff000bffff]: address conflict with 0000:00:07.0 [mem 0x1ff00000000-0x1ff000fffff]
This is probably harmless, but if the VGA device and something behind the
ISA bridge both responded to reads of the framebuffer, it would cause a bus
error.
Link: https://lkml.kernel.org/r/alpine.LRH.2.21.1804112323170.25495@math.ut.ee
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=117191#c35
Reported-by: Meelis Roos <mroos@linux.ee>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-04-10 21:47:34 +08:00
|
|
|
|
|
|
|
|
pci_claim_legacy_resources(dev);
|
2014-08-13 14:29:09 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
list_for_each_entry(child_bus, &bus->children, node)
|
|
|
|
|
pci_claim_bus_resources(child_bus);
|
|
|
|
|
}
|
|
|
|
|
|
2013-01-01 23:02:33 +08:00
|
|
|
struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
|
|
|
|
|
struct device *parent)
|
2007-03-01 15:35:04 +08:00
|
|
|
{
|
2011-10-29 06:27:53 +08:00
|
|
|
LIST_HEAD(resources);
|
2010-04-14 07:12:29 +08:00
|
|
|
struct device_node *node = pbm->op->dev.of_node;
|
2007-03-01 15:35:04 +08:00
|
|
|
struct pci_bus *bus;
|
|
|
|
|
|
2018-11-17 05:06:54 +08:00
|
|
|
printk("PCI: Scanning PBM %pOF\n", node);
|
2007-03-01 15:35:04 +08:00
|
|
|
|
2012-02-24 11:19:04 +08:00
|
|
|
pci_add_resource_offset(&resources, &pbm->io_space,
|
2017-04-21 13:04:48 +08:00
|
|
|
pbm->io_offset);
|
2012-02-24 11:19:04 +08:00
|
|
|
pci_add_resource_offset(&resources, &pbm->mem_space,
|
2017-04-21 13:04:48 +08:00
|
|
|
pbm->mem_offset);
|
2015-10-21 00:36:53 +08:00
|
|
|
if (pbm->mem64_space.flags)
|
|
|
|
|
pci_add_resource_offset(&resources, &pbm->mem64_space,
|
2017-04-21 13:04:48 +08:00
|
|
|
pbm->mem64_offset);
|
2012-05-18 09:51:12 +08:00
|
|
|
pbm->busn.start = pbm->pci_first_busno;
|
|
|
|
|
pbm->busn.end = pbm->pci_last_busno;
|
|
|
|
|
pbm->busn.flags = IORESOURCE_BUS;
|
|
|
|
|
pci_add_resource(&resources, &pbm->busn);
|
2011-10-29 06:27:53 +08:00
|
|
|
bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
|
|
|
|
|
pbm, &resources);
|
2007-03-01 15:35:04 +08:00
|
|
|
if (!bus) {
|
2018-11-17 05:06:54 +08:00
|
|
|
printk(KERN_ERR "Failed to create bus for %pOF\n", node);
|
2011-10-29 06:27:53 +08:00
|
|
|
pci_free_resource_list(&resources);
|
2007-03-01 15:35:04 +08:00
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
pci_of_scan_bus(pbm, node, bus);
|
|
|
|
|
pci_bus_register_of_sysfs(bus);
|
|
|
|
|
|
2014-08-13 14:29:09 +08:00
|
|
|
pci_claim_bus_resources(bus);
|
sparc/PCI: Request legacy VGA framebuffer only for VGA devices
Previously we unconditionally requested the legacy VGA framebuffer (bus
address 0xa0000-0xbffff) before we even know what PCI devices are present,
in these paths:
pci_fire_pbm_init, schizo_pbm_init, pci_sun4v_pbm_init, psycho_pbm_init_common
pci_determine_mem_io_space
pci_register_legacy_regions
p->start = mem_res->start + 0xa0000
request_resource(mem_res, p) # claim VGA framebuffer
pci_scan_one_pbm
pci_of_scan_bus # scan DT for PCI devices
pci_claim_bus_resources # claim PCI device BARs
If we found a PCI device with a BAR or bridge window that overlapped the
framebuffer area, we complained about not being able to claim the BAR,
e.g.,
pci 0000:00:01.0: can't claim BAR 8 [mem 0x1ff00000000-0x1ffbfffffff]: address conflict with Video RAM area [??? 0x1ff000a0000-0x1ff000bffff flags 0x80000000]
pci 0000:02:01.0: can't claim BAR 8 [mem 0x1ff00100000-0x1ff028fffff]: no compatible bridge window
pci 0000:03:0f.0: can't claim BAR 8 [mem 0x1ff00100000-0x1ff028fffff]: no compatible bridge window
pci 0000:04:04.0: can't claim BAR 1 [mem 0x1ff02808000-0x1ff02808fff]: no compatible bridge window
This may make the conflicting device unusable because we try not to enable
devices that have unassigned or conflicting BARs, e.g.,
qla1280 0000:04:04.0: can't ioremap BAR 1: [mem size 0x00001000]
qla1280: Unable to map I/O memory
If there is no VGA device in the same PCI segment, there's no reason to
reserve the framebuffer and there's no conflict. If there *is* a VGA
device in the same segment, both the VGA device and the device with an
overlapping BAR may respond to the framebuffer addresses, which may cause
bus errors.
Request the legacy framebuffer area only when we actually find a VGA
device. The fact that VGA devices use the legacy framebuffer even though
it's not reported in a BAR is not sparc-specific, so the reservation of
that area could be made more generic in the PCI core eventually.
Note that on some systems, e.g., Blade 100, we still report a conflict
between an ISA bridge (00:07.0) and a VGA device (00:13.0):
pci_bus 0000:00: root bus resource [mem 0x1ff00000000-0x1ffffffffff] (bus address [0x00000000-0xffffffff])
pci 0000:00:07.0: reg 0x14: [mem 0x1ff00000000-0x1ff000fffff]
pci 0000:00:13.0: can't claim VGA legacy [mem 0x1ff000a0000-0x1ff000bffff]: address conflict with 0000:00:07.0 [mem 0x1ff00000000-0x1ff000fffff]
This is probably harmless, but if the VGA device and something behind the
ISA bridge both responded to reads of the framebuffer, it would cause a bus
error.
Link: https://lkml.kernel.org/r/alpine.LRH.2.21.1804112323170.25495@math.ut.ee
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=117191#c35
Reported-by: Meelis Roos <mroos@linux.ee>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-04-10 21:47:34 +08:00
|
|
|
|
2015-03-13 04:05:56 +08:00
|
|
|
pci_bus_add_devices(bus);
|
2007-03-01 15:35:04 +08:00
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int pcibios_enable_device(struct pci_dev *dev, int mask)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2007-03-01 15:35:04 +08:00
|
|
|
u16 cmd, oldcmd;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
|
|
|
oldcmd = cmd;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
|
|
|
|
|
struct resource *res = &dev->resource[i];
|
|
|
|
|
|
|
|
|
|
/* Only set up the requested stuff */
|
|
|
|
|
if (!(mask & (1<<i)))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (res->flags & IORESOURCE_IO)
|
|
|
|
|
cmd |= PCI_COMMAND_IO;
|
|
|
|
|
if (res->flags & IORESOURCE_MEM)
|
|
|
|
|
cmd |= PCI_COMMAND_MEMORY;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cmd != oldcmd) {
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
|
2007-03-01 15:35:04 +08:00
|
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Platform support for /proc/bus/pci/X/Y mmap()s. */
|
|
|
|
|
|
|
|
|
|
/* If the user uses a host-bridge as the PCI device, he may use
|
|
|
|
|
* this to perform a raw mmap() of the I/O or MEM space behind
|
|
|
|
|
* that controller.
|
|
|
|
|
*
|
|
|
|
|
* This can be useful for execution of x86 PCI bios initialization code
|
|
|
|
|
* on a PCI card, like the xfree86 int10 stuff does.
|
|
|
|
|
*/
|
|
|
|
|
static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
|
|
|
|
|
enum pci_mmap_state mmap_state)
|
|
|
|
|
{
|
2007-03-01 15:35:04 +08:00
|
|
|
struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned long space_size, user_offset, user_size;
|
|
|
|
|
|
2007-03-09 14:52:11 +08:00
|
|
|
if (mmap_state == pci_mmap_io) {
|
2011-06-10 00:13:32 +08:00
|
|
|
space_size = resource_size(&pbm->io_space);
|
2005-04-17 06:20:36 +08:00
|
|
|
} else {
|
2011-06-10 00:13:32 +08:00
|
|
|
space_size = resource_size(&pbm->mem_space);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Make sure the request is in range. */
|
|
|
|
|
user_offset = vma->vm_pgoff << PAGE_SHIFT;
|
|
|
|
|
user_size = vma->vm_end - vma->vm_start;
|
|
|
|
|
|
|
|
|
|
if (user_offset >= space_size ||
|
|
|
|
|
(user_offset + user_size) > space_size)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
2007-03-09 14:52:11 +08:00
|
|
|
if (mmap_state == pci_mmap_io) {
|
|
|
|
|
vma->vm_pgoff = (pbm->io_space.start +
|
|
|
|
|
user_offset) >> PAGE_SHIFT;
|
2005-04-17 06:20:36 +08:00
|
|
|
} else {
|
2007-03-09 14:52:11 +08:00
|
|
|
vma->vm_pgoff = (pbm->mem_space.start +
|
|
|
|
|
user_offset) >> PAGE_SHIFT;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2007-10-12 06:41:01 +08:00
|
|
|
/* Adjust vm_pgoff of VMA such that it is the physical page offset
|
|
|
|
|
* corresponding to the 32-bit pci bus offset for DEV requested by the user.
|
2005-04-17 06:20:36 +08:00
|
|
|
*
|
|
|
|
|
* Basically, the user finds the base address for his device which he wishes
|
|
|
|
|
* to mmap. They read the 32-bit value from the config space base register,
|
|
|
|
|
* add whatever PAGE_SIZE multiple offset they wish, and feed this into the
|
|
|
|
|
* offset parameter of mmap on /proc/bus/pci/XXX for that device.
|
|
|
|
|
*
|
|
|
|
|
* Returns negative error code on failure, zero on success.
|
|
|
|
|
*/
|
2007-10-12 06:41:01 +08:00
|
|
|
static int __pci_mmap_make_offset(struct pci_dev *pdev,
|
|
|
|
|
struct vm_area_struct *vma,
|
2005-04-17 06:20:36 +08:00
|
|
|
enum pci_mmap_state mmap_state)
|
|
|
|
|
{
|
2007-10-12 06:41:01 +08:00
|
|
|
unsigned long user_paddr, user_size;
|
|
|
|
|
int i, err;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2007-10-12 06:41:01 +08:00
|
|
|
/* First compute the physical address in vma->vm_pgoff,
|
|
|
|
|
* making sure the user offset is within range in the
|
|
|
|
|
* appropriate PCI space.
|
|
|
|
|
*/
|
|
|
|
|
err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
/* If this is a mapping on a host bridge, any address
|
|
|
|
|
* is OK.
|
|
|
|
|
*/
|
|
|
|
|
if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
/* Otherwise make sure it's in the range for one of the
|
|
|
|
|
* device's resources.
|
|
|
|
|
*/
|
|
|
|
|
user_paddr = vma->vm_pgoff << PAGE_SHIFT;
|
|
|
|
|
user_size = vma->vm_end - vma->vm_start;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
|
2007-10-12 06:41:01 +08:00
|
|
|
struct resource *rp = &pdev->resource[i];
|
2008-11-02 15:34:10 +08:00
|
|
|
resource_size_t aligned_end;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/* Active? */
|
|
|
|
|
if (!rp->flags)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
/* Same type? */
|
|
|
|
|
if (i == PCI_ROM_RESOURCE) {
|
|
|
|
|
if (mmap_state != pci_mmap_mem)
|
|
|
|
|
continue;
|
|
|
|
|
} else {
|
|
|
|
|
if ((mmap_state == pci_mmap_io &&
|
|
|
|
|
(rp->flags & IORESOURCE_IO) == 0) ||
|
|
|
|
|
(mmap_state == pci_mmap_mem &&
|
|
|
|
|
(rp->flags & IORESOURCE_MEM) == 0))
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
2008-11-02 15:34:10 +08:00
|
|
|
/* Align the resource end to the next page address.
|
|
|
|
|
* PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
|
|
|
|
|
* because actually we need the address of the next byte
|
|
|
|
|
* after rp->end.
|
|
|
|
|
*/
|
|
|
|
|
aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
|
|
|
|
|
|
2007-10-12 06:41:01 +08:00
|
|
|
if ((rp->start <= user_paddr) &&
|
2008-11-02 15:34:10 +08:00
|
|
|
(user_paddr + user_size) <= aligned_end)
|
2007-10-12 06:41:01 +08:00
|
|
|
break;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2007-10-12 06:41:01 +08:00
|
|
|
if (i > PCI_ROM_RESOURCE)
|
2005-04-17 06:20:36 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
|
|
|
|
|
* device mapping.
|
|
|
|
|
*/
|
|
|
|
|
static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
|
|
|
|
|
enum pci_mmap_state mmap_state)
|
|
|
|
|
{
|
2005-09-02 12:51:26 +08:00
|
|
|
/* Our io_remap_pfn_range takes care of this, do nothing. */
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
|
|
|
|
|
* for this architecture. The region in the process to map is described by vm_start
|
|
|
|
|
* and vm_end members of VMA, the base physical address is found in vm_pgoff.
|
|
|
|
|
* The pci device structure is provided so that architectures may make mapping
|
|
|
|
|
* decisions on a per-device or per-bus basis.
|
|
|
|
|
*
|
|
|
|
|
* Returns a negative error code on failure, zero on success.
|
|
|
|
|
*/
|
2017-04-12 20:25:58 +08:00
|
|
|
int pci_mmap_page_range(struct pci_dev *dev, int bar,
|
|
|
|
|
struct vm_area_struct *vma,
|
|
|
|
|
enum pci_mmap_state mmap_state, int write_combine)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = __pci_mmap_make_offset(dev, vma, mmap_state);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
__pci_mmap_set_pgprot(dev, vma, mmap_state);
|
|
|
|
|
|
2006-03-21 18:29:39 +08:00
|
|
|
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
2005-04-17 06:20:36 +08:00
|
|
|
ret = io_remap_pfn_range(vma, vma->vm_start,
|
|
|
|
|
vma->vm_pgoff,
|
|
|
|
|
vma->vm_end - vma->vm_start,
|
|
|
|
|
vma->vm_page_prot);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2008-03-19 19:52:48 +08:00
|
|
|
#ifdef CONFIG_NUMA
|
|
|
|
|
int pcibus_to_node(struct pci_bus *pbus)
|
|
|
|
|
{
|
|
|
|
|
struct pci_pbm_info *pbm = pbus->sysdata;
|
|
|
|
|
|
|
|
|
|
return pbm->numa_node;
|
|
|
|
|
}
|
|
|
|
|
EXPORT_SYMBOL(pcibus_to_node);
|
|
|
|
|
#endif
|
|
|
|
|
|
2008-09-10 14:54:02 +08:00
|
|
|
/* Return the domain number for this pci bus */
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
int pci_domain_nr(struct pci_bus *pbus)
|
|
|
|
|
{
|
|
|
|
|
struct pci_pbm_info *pbm = pbus->sysdata;
|
|
|
|
|
int ret;
|
|
|
|
|
|
2008-09-10 14:54:02 +08:00
|
|
|
if (!pbm) {
|
2005-04-17 06:20:36 +08:00
|
|
|
ret = -ENXIO;
|
|
|
|
|
} else {
|
2007-05-08 14:49:01 +08:00
|
|
|
ret = pbm->index;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
EXPORT_SYMBOL(pci_domain_nr);
|
|
|
|
|
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 09:41:02 +08:00
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
|
int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
|
|
|
|
|
{
|
2007-03-01 15:35:04 +08:00
|
|
|
struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
|
2011-01-22 19:32:20 +08:00
|
|
|
unsigned int irq;
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 09:41:02 +08:00
|
|
|
|
2007-05-08 14:28:50 +08:00
|
|
|
if (!pbm->setup_msi_irq)
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 09:41:02 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
2011-01-22 19:32:20 +08:00
|
|
|
return pbm->setup_msi_irq(&irq, pdev, desc);
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 09:41:02 +08:00
|
|
|
}
|
|
|
|
|
|
2011-01-22 19:32:20 +08:00
|
|
|
void arch_teardown_msi_irq(unsigned int irq)
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 09:41:02 +08:00
|
|
|
{
|
2011-03-25 00:52:54 +08:00
|
|
|
struct msi_desc *entry = irq_get_msi_desc(irq);
|
2015-07-09 16:00:42 +08:00
|
|
|
struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
|
2007-03-01 15:35:04 +08:00
|
|
|
struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 09:41:02 +08:00
|
|
|
|
2008-09-12 14:57:40 +08:00
|
|
|
if (pbm->teardown_msi_irq)
|
2011-01-22 19:32:20 +08:00
|
|
|
pbm->teardown_msi_irq(irq, pdev);
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 09:41:02 +08:00
|
|
|
}
|
|
|
|
|
#endif /* !(CONFIG_PCI_MSI) */
|
|
|
|
|
|
2019-02-15 16:06:31 +08:00
|
|
|
/* ALI sound chips generate 31-bits of DMA, a special register
|
|
|
|
|
* determines what bit 31 is emitted as.
|
|
|
|
|
*/
|
|
|
|
|
int ali_sound_dma_hack(struct device *dev, u64 device_mask)
|
2007-07-28 13:39:14 +08:00
|
|
|
{
|
2019-02-15 16:06:31 +08:00
|
|
|
struct iommu *iommu = dev->archdata.iommu;
|
2007-07-28 13:39:14 +08:00
|
|
|
struct pci_dev *ali_isa_bridge;
|
|
|
|
|
u8 val;
|
|
|
|
|
|
2019-02-15 16:06:31 +08:00
|
|
|
if (!dev_is_pci(dev))
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
if (to_pci_dev(dev)->vendor != PCI_VENDOR_ID_AL ||
|
|
|
|
|
to_pci_dev(dev)->device != PCI_DEVICE_ID_AL_M5451 ||
|
|
|
|
|
device_mask != 0x7fffffff)
|
|
|
|
|
return 0;
|
|
|
|
|
|
2007-07-28 13:39:14 +08:00
|
|
|
ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
|
|
|
|
|
PCI_DEVICE_ID_AL_M1533,
|
|
|
|
|
NULL);
|
|
|
|
|
|
|
|
|
|
pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
|
2019-02-15 16:06:31 +08:00
|
|
|
if (iommu->dma_addr_mask & 0x80000000)
|
2007-07-28 13:39:14 +08:00
|
|
|
val |= 0x01;
|
|
|
|
|
else
|
|
|
|
|
val &= ~0x01;
|
|
|
|
|
pci_write_config_byte(ali_isa_bridge, 0x7e, val);
|
|
|
|
|
pci_dev_put(ali_isa_bridge);
|
2019-02-15 16:06:31 +08:00
|
|
|
return 1;
|
2007-07-28 13:39:14 +08:00
|
|
|
}
|
|
|
|
|
|
2007-12-25 18:20:33 +08:00
|
|
|
void pci_resource_to_user(const struct pci_dev *pdev, int bar,
|
|
|
|
|
const struct resource *rp, resource_size_t *start,
|
|
|
|
|
resource_size_t *end)
|
|
|
|
|
{
|
2016-06-18 03:43:34 +08:00
|
|
|
struct pci_bus_region region;
|
2007-12-25 18:20:33 +08:00
|
|
|
|
2016-06-18 03:43:34 +08:00
|
|
|
/*
|
|
|
|
|
* "User" addresses are shown in /sys/devices/pci.../.../resource
|
|
|
|
|
* and /proc/bus/pci/devices and used as mmap offsets for
|
|
|
|
|
* /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()).
|
|
|
|
|
*
|
|
|
|
|
* On sparc, these are PCI bus addresses, i.e., raw BAR values.
|
|
|
|
|
*/
|
|
|
|
|
pcibios_resource_to_bus(pdev->bus, ®ion, (struct resource *) rp);
|
|
|
|
|
*start = region.start;
|
|
|
|
|
*end = region.end;
|
2007-12-25 18:20:33 +08:00
|
|
|
}
|
2009-09-22 16:34:17 +08:00
|
|
|
|
2011-10-29 05:48:10 +08:00
|
|
|
void pcibios_set_master(struct pci_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
/* No special bus mastering setup handling */
|
|
|
|
|
}
|
|
|
|
|
|
2016-03-25 04:02:22 +08:00
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
|
|
|
int pcibios_add_device(struct pci_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
|
|
|
|
|
|
/* Add sriov arch specific initialization here.
|
|
|
|
|
* Copy dev_archdata from PF to VF
|
|
|
|
|
*/
|
|
|
|
|
if (dev->is_virtfn) {
|
2016-04-12 08:57:05 +08:00
|
|
|
struct dev_archdata *psd;
|
|
|
|
|
|
2016-03-25 04:02:22 +08:00
|
|
|
pdev = dev->physfn;
|
2016-04-12 08:57:05 +08:00
|
|
|
psd = &pdev->dev.archdata;
|
|
|
|
|
pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
|
|
|
|
|
psd->stc, psd->host_controller, NULL,
|
|
|
|
|
psd->numa_node);
|
2016-03-25 04:02:22 +08:00
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_PCI_IOV */
|
|
|
|
|
|
2009-09-22 16:34:17 +08:00
|
|
|
static int __init pcibios_init(void)
|
|
|
|
|
{
|
|
|
|
|
pci_dfl_cache_line_size = 64 >> 2;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
subsys_initcall(pcibios_init);
|
2010-02-21 11:53:55 +08:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_SYSFS
|
2015-05-27 23:59:19 +08:00
|
|
|
|
|
|
|
|
#define SLOT_NAME_SIZE 11 /* Max decimal digits + null in u32 */
|
|
|
|
|
|
|
|
|
|
static void pcie_bus_slot_names(struct pci_bus *pbus)
|
|
|
|
|
{
|
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
|
struct pci_bus *bus;
|
|
|
|
|
|
|
|
|
|
list_for_each_entry(pdev, &pbus->devices, bus_list) {
|
|
|
|
|
char name[SLOT_NAME_SIZE];
|
|
|
|
|
struct pci_slot *pci_slot;
|
|
|
|
|
const u32 *slot_num;
|
|
|
|
|
int len;
|
|
|
|
|
|
|
|
|
|
slot_num = of_get_property(pdev->dev.of_node,
|
|
|
|
|
"physical-slot#", &len);
|
|
|
|
|
|
|
|
|
|
if (slot_num == NULL || len != 4)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
snprintf(name, sizeof(name), "%u", slot_num[0]);
|
|
|
|
|
pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL);
|
|
|
|
|
|
|
|
|
|
if (IS_ERR(pci_slot))
|
|
|
|
|
pr_err("PCI: pci_create_slot returned %ld.\n",
|
|
|
|
|
PTR_ERR(pci_slot));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
list_for_each_entry(bus, &pbus->children, node)
|
|
|
|
|
pcie_bus_slot_names(bus);
|
|
|
|
|
}
|
|
|
|
|
|
2013-01-01 23:02:33 +08:00
|
|
|
static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
|
2010-02-21 11:53:55 +08:00
|
|
|
{
|
|
|
|
|
const struct pci_slot_names {
|
|
|
|
|
u32 slot_mask;
|
|
|
|
|
char names[0];
|
|
|
|
|
} *prop;
|
|
|
|
|
const char *sp;
|
|
|
|
|
int len, i;
|
|
|
|
|
u32 mask;
|
|
|
|
|
|
|
|
|
|
prop = of_get_property(node, "slot-names", &len);
|
|
|
|
|
if (!prop)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
mask = prop->slot_mask;
|
|
|
|
|
sp = prop->names;
|
|
|
|
|
|
|
|
|
|
if (ofpci_verbose)
|
2018-11-17 05:06:54 +08:00
|
|
|
pci_info(bus, "Making slots for [%pOF] mask[0x%02x]\n",
|
|
|
|
|
node, mask);
|
2010-02-21 11:53:55 +08:00
|
|
|
|
|
|
|
|
i = 0;
|
|
|
|
|
while (mask) {
|
|
|
|
|
struct pci_slot *pci_slot;
|
|
|
|
|
u32 this_bit = 1 << i;
|
|
|
|
|
|
|
|
|
|
if (!(mask & this_bit)) {
|
|
|
|
|
i++;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (ofpci_verbose)
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_info(bus, "Making slot [%s]\n", sp);
|
2010-02-21 11:53:55 +08:00
|
|
|
|
|
|
|
|
pci_slot = pci_create_slot(bus, i, sp, NULL);
|
|
|
|
|
if (IS_ERR(pci_slot))
|
2018-04-22 03:35:42 +08:00
|
|
|
pci_err(bus, "pci_create_slot returned %ld\n",
|
|
|
|
|
PTR_ERR(pci_slot));
|
2010-02-21 11:53:55 +08:00
|
|
|
|
|
|
|
|
sp += strlen(sp) + 1;
|
|
|
|
|
mask &= ~this_bit;
|
|
|
|
|
i++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int __init of_pci_slot_init(void)
|
|
|
|
|
{
|
|
|
|
|
struct pci_bus *pbus = NULL;
|
|
|
|
|
|
|
|
|
|
while ((pbus = pci_find_next_bus(pbus)) != NULL) {
|
|
|
|
|
struct device_node *node;
|
2015-05-27 23:59:19 +08:00
|
|
|
struct pci_dev *pdev;
|
|
|
|
|
|
|
|
|
|
pdev = list_first_entry(&pbus->devices, struct pci_dev,
|
|
|
|
|
bus_list);
|
2010-02-21 11:53:55 +08:00
|
|
|
|
2015-05-27 23:59:19 +08:00
|
|
|
if (pdev && pci_is_pcie(pdev)) {
|
|
|
|
|
pcie_bus_slot_names(pbus);
|
2010-02-21 11:53:55 +08:00
|
|
|
} else {
|
|
|
|
|
|
2015-05-27 23:59:19 +08:00
|
|
|
if (pbus->self) {
|
|
|
|
|
|
|
|
|
|
/* PCI->PCI bridge */
|
|
|
|
|
node = pbus->self->dev.of_node;
|
|
|
|
|
|
|
|
|
|
} else {
|
|
|
|
|
struct pci_pbm_info *pbm = pbus->sysdata;
|
2010-02-21 11:53:55 +08:00
|
|
|
|
2015-05-27 23:59:19 +08:00
|
|
|
/* Host PCI controller */
|
|
|
|
|
node = pbm->op->dev.of_node;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
pci_bus_slot_names(node, pbus);
|
|
|
|
|
}
|
2010-02-21 11:53:55 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2014-01-13 02:07:30 +08:00
|
|
|
device_initcall(of_pci_slot_init);
|
2010-02-21 11:53:55 +08:00
|
|
|
#endif
|
