2017-07-11 09:08:08 +08:00
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# This file is included by the global makefile so that you can add your own
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# architecture-specific flags and dependencies. Remember to do have actions
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# for "archclean" and "archdep" for cleaning up and making dependencies for
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# this architecture
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#
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# This file is subject to the terms and conditions of the GNU General Public
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# License. See the file "COPYING" in the main directory of this archive
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# for more details.
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#
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OBJCOPYFLAGS := -O binary
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LDFLAGS_vmlinux :=
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2018-02-13 13:13:16 +08:00
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ifeq ($(CONFIG_DYNAMIC_FTRACE),y)
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LDFLAGS_vmlinux := --no-relax
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riscv: Using PATCHABLE_FUNCTION_ENTRY instead of MCOUNT
This patch changes the current detour mechanism of dynamic ftrace
which has been discussed during LPC 2020 RISCV-MC [1].
Before the patch, we used mcount for detour:
<funca>:
addi sp,sp,-16
sd ra,8(sp)
sd s0,0(sp)
addi s0,sp,16
mv a5,ra
mv a0,a5
auipc ra,0x0 -> nop
jalr -296(ra) <_mcount@plt> ->nop
...
After the patch, we use nop call site area for detour:
<funca>:
nop -> REG_S ra, -SZREG(sp)
nop -> auipc ra, 0x?
nop -> jalr ?(ra)
nop -> REG_L ra, -SZREG(sp)
...
The mcount mechanism is mixed with gcc function prologue which is
not very clear. The patchable function entry just put 16 bytes nop
before the front of the function prologue which could be filled
with a separated detour mechanism.
[1] https://www.linuxplumbersconf.org/event/7/contributions/807/
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-12-18 00:01:41 +08:00
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KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
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CC_FLAGS_FTRACE := -fpatchable-function-entry=8
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2018-02-13 13:13:16 +08:00
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endif
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2020-02-21 10:47:55 +08:00
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2021-06-07 06:09:40 +08:00
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ifeq ($(CONFIG_CMODEL_MEDLOW),y)
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2020-02-21 10:47:55 +08:00
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KBUILD_CFLAGS_MODULE += -mcmodel=medany
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endif
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2017-07-11 09:08:08 +08:00
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export BITS
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ifeq ($(CONFIG_ARCH_RV64I),y)
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BITS := 64
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UTS_MACHINE := riscv64
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KBUILD_CFLAGS += -mabi=lp64
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KBUILD_AFLAGS += -mabi=lp64
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2018-07-29 09:14:47 +08:00
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2018-08-24 07:20:39 +08:00
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KBUILD_LDFLAGS += -melf64lriscv
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2017-07-11 09:08:08 +08:00
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else
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BITS := 32
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UTS_MACHINE := riscv32
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KBUILD_CFLAGS += -mabi=ilp32
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KBUILD_AFLAGS += -mabi=ilp32
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2018-08-24 07:20:39 +08:00
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KBUILD_LDFLAGS += -melf32lriscv
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2017-07-11 09:08:08 +08:00
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endif
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2021-05-15 05:37:41 +08:00
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ifeq ($(CONFIG_LD_IS_LLD),y)
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KBUILD_CFLAGS += -mno-relax
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KBUILD_AFLAGS += -mno-relax
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ifneq ($(LLVM_IAS),1)
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KBUILD_CFLAGS += -Wa,-mno-relax
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KBUILD_AFLAGS += -Wa,-mno-relax
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endif
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endif
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2018-10-09 10:18:32 +08:00
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# ISA string setting
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2019-04-15 17:14:35 +08:00
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riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
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riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
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2018-10-09 10:18:33 +08:00
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riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
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2018-10-09 10:18:32 +08:00
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riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
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KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
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KBUILD_AFLAGS += -march=$(riscv-march-y)
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2017-07-11 09:08:08 +08:00
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KBUILD_CFLAGS += -mno-save-restore
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KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)
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ifeq ($(CONFIG_CMODEL_MEDLOW),y)
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KBUILD_CFLAGS += -mcmodel=medlow
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endif
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ifeq ($(CONFIG_CMODEL_MEDANY),y)
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KBUILD_CFLAGS += -mcmodel=medany
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endif
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2019-08-29 14:57:00 +08:00
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ifeq ($(CONFIG_PERF_EVENTS),y)
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KBUILD_CFLAGS += -fno-omit-frame-pointer
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endif
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2018-03-15 16:50:41 +08:00
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KBUILD_CFLAGS_MODULE += $(call cc-option,-mno-relax)
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2017-07-11 09:08:08 +08:00
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# GCC versions that support the "-mstrict-align" option default to allowing
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# unaligned accesses. While unaligned accesses are explicitly allowed in the
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# RISC-V ISA, they're emulated by machine mode traps on all extant
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# architectures. It's faster to have GCC emit only aligned accesses.
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KBUILD_CFLAGS += $(call cc-option,-mstrict-align)
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riscv: Enable per-task stack canaries
This enables the use of per-task stack canary values if GCC has
support for emitting the stack canary reference relative to the
value of tp, which holds the task struct pointer in the riscv
kernel.
After compare arm64 and x86 implementations, seems arm64's is more
flexible and readable. The key point is how gcc get the offset of
stack_canary from gs/el0_sp.
x86: Use a fix offset from gs, not flexible.
struct fixed_percpu_data {
/*
* GCC hardcodes the stack canary as %gs:40. Since the
* irq_stack is the object at %gs:0, we reserve the bottom
* 48 bytes of the irq stack for the canary.
*/
char gs_base[40]; // :(
unsigned long stack_canary;
};
arm64: Use -mstack-protector-guard-offset & guard-reg
gcc options:
-mstack-protector-guard=sysreg
-mstack-protector-guard-reg=sp_el0
-mstack-protector-guard-offset=xxx
riscv: Use -mstack-protector-guard-offset & guard-reg
gcc options:
-mstack-protector-guard=tls
-mstack-protector-guard-reg=tp
-mstack-protector-guard-offset=xxx
GCC's implementation has been merged:
commit c931e8d5a96463427040b0d11f9c4352ac22b2b0
Author: Cooper Qu <cooper.qu@linux.alibaba.com>
Date: Mon Jul 13 16:15:08 2020 +0800
RISC-V: Add support for TLS stack protector canary access
In the end, these codes are inserted by gcc before return:
* 0xffffffe00020b396 <+120>: ld a5,1008(tp) # 0x3f0
* 0xffffffe00020b39a <+124>: xor a5,a5,a4
* 0xffffffe00020b39c <+126>: mv a0,s5
* 0xffffffe00020b39e <+128>: bnez a5,0xffffffe00020b61c <_do_fork+766>
0xffffffe00020b3a2 <+132>: ld ra,136(sp)
0xffffffe00020b3a4 <+134>: ld s0,128(sp)
0xffffffe00020b3a6 <+136>: ld s1,120(sp)
0xffffffe00020b3a8 <+138>: ld s2,112(sp)
0xffffffe00020b3aa <+140>: ld s3,104(sp)
0xffffffe00020b3ac <+142>: ld s4,96(sp)
0xffffffe00020b3ae <+144>: ld s5,88(sp)
0xffffffe00020b3b0 <+146>: ld s6,80(sp)
0xffffffe00020b3b2 <+148>: ld s7,72(sp)
0xffffffe00020b3b4 <+150>: addi sp,sp,144
0xffffffe00020b3b6 <+152>: ret
...
* 0xffffffe00020b61c <+766>: auipc ra,0x7f8
* 0xffffffe00020b620 <+770>: jalr -1764(ra) # 0xffffffe000a02f38 <__stack_chk_fail>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Cooper Qu <cooper.qu@linux.alibaba.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-12-18 00:29:18 +08:00
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ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y)
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prepare: stack_protector_prepare
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stack_protector_prepare: prepare0
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$(eval KBUILD_CFLAGS += -mstack-protector-guard=tls \
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-mstack-protector-guard-reg=tp \
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-mstack-protector-guard-offset=$(shell \
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awk '{if ($$2 == "TSK_STACK_CANARY") print $$3;}' \
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include/generated/asm-offsets.h))
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endif
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2018-05-31 23:42:01 +08:00
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# arch specific predefines for sparse
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CHECKFLAGS += -D__riscv -D__riscv_xlen=$(BITS)
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2018-11-12 13:55:15 +08:00
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# Default target when executing plain make
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boot := arch/riscv/boot
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2021-04-13 14:35:14 +08:00
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ifeq ($(CONFIG_XIP_KERNEL),y)
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KBUILD_IMAGE := $(boot)/xipImage
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else
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2018-11-12 13:55:15 +08:00
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KBUILD_IMAGE := $(boot)/Image.gz
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2021-04-13 14:35:14 +08:00
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endif
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2018-11-12 13:55:15 +08:00
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2017-07-11 09:08:08 +08:00
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head-y := arch/riscv/kernel/head.o
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riscv: Introduce alternative mechanism to apply errata solution
Introduce the "alternative" mechanism from ARM64 and x86 to apply the CPU
vendors' errata solution at runtime. The main purpose of this patch is
to provide a framework. Therefore, the implementation is quite basic for
now so that some scenarios could not use this schemei, such as patching
code to a module, relocating the patching code and heterogeneous CPU
topology.
Users could use the macro ALTERNATIVE to apply an errata to the existing
code flow. In the macro ALTERNATIVE, users need to specify the manufacturer
information(vendorid, archid, and impid) for this errata. Therefore, kernel
will know this errata is suitable for which CPU core. During the booting
procedure, kernel will select the errata required by the CPU core and then
patch it. It means that the kernel only applies the errata to the specified
CPU core. In this case, the vendor's errata does not affect each other at
runtime. The above patching procedure only occurs during the booting phase,
so we only take the overhead of the "alternative" mechanism once.
This "alternative" mechanism is enabled by default to ensure that all
required errata will be applied. However, users can disable this feature by
the Kconfig "CONFIG_RISCV_ERRATA_ALTERNATIVE".
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-03-22 22:26:03 +08:00
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core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/
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2017-07-11 09:08:08 +08:00
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libs-y += arch/riscv/lib/
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2020-09-18 06:37:14 +08:00
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libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a
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2017-07-11 09:08:08 +08:00
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2018-11-05 22:35:37 +08:00
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PHONY += vdso_install
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vdso_install:
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$(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@
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2021-04-13 14:35:14 +08:00
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ifneq ($(CONFIG_XIP_KERNEL),y)
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2020-12-13 21:50:38 +08:00
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ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN),yy)
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2020-03-16 08:47:43 +08:00
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KBUILD_IMAGE := $(boot)/loader.bin
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2019-10-28 20:10:42 +08:00
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else
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KBUILD_IMAGE := $(boot)/Image.gz
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endif
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2021-04-13 14:35:14 +08:00
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endif
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BOOT_TARGETS := Image Image.gz loader loader.bin xipImage
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2018-11-12 13:55:15 +08:00
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2019-10-28 20:10:42 +08:00
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all: $(notdir $(KBUILD_IMAGE))
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2018-11-12 13:55:15 +08:00
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2019-10-28 20:10:42 +08:00
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$(BOOT_TARGETS): vmlinux
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2018-11-12 13:55:15 +08:00
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$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
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2019-10-28 20:10:42 +08:00
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@$(kecho) ' Kernel: $(boot)/$@ is ready'
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2018-11-12 13:55:15 +08:00
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2020-11-04 14:14:59 +08:00
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Image.%: Image
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$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
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2018-11-12 13:55:15 +08:00
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zinstall install:
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$(Q)$(MAKE) $(build)=$(boot) $@
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2020-11-04 14:15:00 +08:00
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archclean:
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$(Q)$(MAKE) $(clean)=$(boot)
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