2020-01-10 10:18:21 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* rt715.h -- RT715 ALSA SoC audio driver header
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*
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* Copyright(c) 2019 Realtek Semiconductor Corp.
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*/
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#ifndef __RT715_H__
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#define __RT715_H__
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#include <linux/regulator/consumer.h>
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struct rt715_priv {
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struct regmap *regmap;
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struct regmap *sdw_regmap;
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struct snd_soc_codec *codec;
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struct sdw_slave *slave;
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int dbg_nid;
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int dbg_vid;
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int dbg_payload;
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struct sdw_bus_params params;
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bool hw_init;
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bool first_hw_init;
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2021-03-29 14:54:00 +08:00
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unsigned int kctl_2ch_vol_ori[2];
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2021-03-29 14:53:54 +08:00
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unsigned int kctl_8ch_switch_ori[8];
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unsigned int kctl_8ch_vol_ori[8];
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2020-01-10 10:18:21 +08:00
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};
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/* NID */
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#define RT715_AUDIO_FUNCTION_GROUP 0x01
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#define RT715_MIC_ADC 0x07
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#define RT715_LINE_ADC 0x08
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#define RT715_MIX_ADC 0x09
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#define RT715_DMIC1 0x12
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#define RT715_DMIC2 0x13
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#define RT715_MIC1 0x18
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#define RT715_MIC2 0x19
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#define RT715_LINE1 0x1a
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#define RT715_LINE2 0x1b
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#define RT715_DMIC3 0x1d
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#define RT715_DMIC4 0x29
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#define RT715_VENDOR_REGISTERS 0x20
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#define RT715_MUX_IN1 0x22
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#define RT715_MUX_IN2 0x23
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#define RT715_MUX_IN3 0x24
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#define RT715_MUX_IN4 0x25
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#define RT715_MIX_ADC2 0x27
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#define RT715_INLINE_CMD 0x55
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/* Index (NID:20h) */
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2023-08-10 17:27:45 +08:00
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#define RT715_VD_CLEAR_CTRL 0x01
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2020-01-10 10:18:21 +08:00
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#define RT715_SDW_INPUT_SEL 0x39
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#define RT715_EXT_DMIC_CLK_CTRL2 0x54
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/* Verb */
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#define RT715_VERB_SET_CONNECT_SEL 0x3100
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#define RT715_VERB_GET_CONNECT_SEL 0xb100
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#define RT715_VERB_SET_EAPD_BTLENABLE 0x3c00
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#define RT715_VERB_SET_POWER_STATE 0x3500
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#define RT715_VERB_SET_CHANNEL_STREAMID 0x3600
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#define RT715_VERB_SET_PIN_WIDGET_CONTROL 0x3700
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#define RT715_VERB_SET_CONFIG_DEFAULT1 0x4c00
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#define RT715_VERB_SET_CONFIG_DEFAULT2 0x4d00
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#define RT715_VERB_SET_CONFIG_DEFAULT3 0x4e00
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#define RT715_VERB_SET_CONFIG_DEFAULT4 0x4f00
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#define RT715_VERB_SET_UNSOLICITED_ENABLE 0x3800
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#define RT715_SET_AMP_GAIN_MUTE_H 0x7300
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#define RT715_SET_AMP_GAIN_MUTE_L 0x8380
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#define RT715_READ_HDA_3 0x2012
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#define RT715_READ_HDA_2 0x2013
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#define RT715_READ_HDA_1 0x2014
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#define RT715_READ_HDA_0 0x2015
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#define RT715_PRIV_INDEX_W_H 0x7520
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#define RT715_PRIV_INDEX_W_L 0x85a0
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2023-08-10 17:27:45 +08:00
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#define RT715_PRIV_INDEX_W_H_2 0x7500
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#define RT715_PRIV_INDEX_W_L_2 0x8580
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2020-01-10 10:18:21 +08:00
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#define RT715_PRIV_DATA_W_H 0x7420
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#define RT715_PRIV_DATA_W_L 0x84a0
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#define RT715_PRIV_INDEX_R_H 0x9d20
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#define RT715_PRIV_INDEX_R_L 0xada0
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#define RT715_PRIV_DATA_R_H 0x9c20
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#define RT715_PRIV_DATA_R_L 0xaca0
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#define RT715_MIC_ADC_FORMAT_H 0x7207
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#define RT715_MIC_ADC_FORMAT_L 0x8287
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#define RT715_MIC_LINE_FORMAT_H 0x7208
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#define RT715_MIC_LINE_FORMAT_L 0x8288
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#define RT715_MIX_ADC_FORMAT_H 0x7209
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#define RT715_MIX_ADC_FORMAT_L 0x8289
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#define RT715_MIX_ADC2_FORMAT_H 0x7227
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#define RT715_MIX_ADC2_FORMAT_L 0x82a7
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#define RT715_FUNC_RESET 0xff01
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#define RT715_SET_AUDIO_POWER_STATE\
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(RT715_VERB_SET_POWER_STATE | RT715_AUDIO_FUNCTION_GROUP)
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#define RT715_SET_PIN_DMIC1\
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(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_DMIC1)
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#define RT715_SET_PIN_DMIC2\
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(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_DMIC2)
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#define RT715_SET_PIN_DMIC3\
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(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_DMIC3)
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#define RT715_SET_PIN_DMIC4\
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(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_DMIC4)
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#define RT715_SET_PIN_MIC1\
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(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_MIC1)
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#define RT715_SET_PIN_MIC2\
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(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_MIC2)
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#define RT715_SET_PIN_LINE1\
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(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_LINE1)
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#define RT715_SET_PIN_LINE2\
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(RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_LINE2)
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#define RT715_SET_MIC1_UNSOLICITED_ENABLE\
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(RT715_VERB_SET_UNSOLICITED_ENABLE | RT715_MIC1)
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#define RT715_SET_MIC2_UNSOLICITED_ENABLE\
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(RT715_VERB_SET_UNSOLICITED_ENABLE | RT715_MIC2)
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#define RT715_SET_STREAMID_MIC_ADC\
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(RT715_VERB_SET_CHANNEL_STREAMID | RT715_MIC_ADC)
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#define RT715_SET_STREAMID_LINE_ADC\
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(RT715_VERB_SET_CHANNEL_STREAMID | RT715_LINE_ADC)
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#define RT715_SET_STREAMID_MIX_ADC\
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(RT715_VERB_SET_CHANNEL_STREAMID | RT715_MIX_ADC)
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#define RT715_SET_STREAMID_MIX_ADC2\
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(RT715_VERB_SET_CHANNEL_STREAMID | RT715_MIX_ADC2)
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#define RT715_SET_GAIN_MIC_ADC_L\
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(RT715_SET_AMP_GAIN_MUTE_L | RT715_MIC_ADC)
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#define RT715_SET_GAIN_MIC_ADC_H\
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(RT715_SET_AMP_GAIN_MUTE_H | RT715_MIC_ADC)
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#define RT715_SET_GAIN_LINE_ADC_L\
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(RT715_SET_AMP_GAIN_MUTE_L | RT715_LINE_ADC)
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#define RT715_SET_GAIN_LINE_ADC_H\
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(RT715_SET_AMP_GAIN_MUTE_H | RT715_LINE_ADC)
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#define RT715_SET_GAIN_MIX_ADC_L\
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(RT715_SET_AMP_GAIN_MUTE_L | RT715_MIX_ADC)
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#define RT715_SET_GAIN_MIX_ADC_H\
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(RT715_SET_AMP_GAIN_MUTE_H | RT715_MIX_ADC)
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#define RT715_SET_GAIN_MIX_ADC2_L\
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(RT715_SET_AMP_GAIN_MUTE_L | RT715_MIX_ADC2)
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#define RT715_SET_GAIN_MIX_ADC2_H\
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(RT715_SET_AMP_GAIN_MUTE_H | RT715_MIX_ADC2)
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#define RT715_SET_GAIN_DMIC1_L\
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(RT715_SET_AMP_GAIN_MUTE_L | RT715_DMIC1)
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#define RT715_SET_GAIN_DMIC1_H\
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(RT715_SET_AMP_GAIN_MUTE_H | RT715_DMIC1)
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#define RT715_SET_GAIN_DMIC2_L\
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(RT715_SET_AMP_GAIN_MUTE_L | RT715_DMIC2)
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#define RT715_SET_GAIN_DMIC2_H\
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(RT715_SET_AMP_GAIN_MUTE_H | RT715_DMIC2)
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#define RT715_SET_GAIN_DMIC3_L\
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(RT715_SET_AMP_GAIN_MUTE_L | RT715_DMIC3)
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#define RT715_SET_GAIN_DMIC3_H\
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(RT715_SET_AMP_GAIN_MUTE_H | RT715_DMIC3)
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#define RT715_SET_GAIN_DMIC4_L\
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(RT715_SET_AMP_GAIN_MUTE_L | RT715_DMIC4)
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#define RT715_SET_GAIN_DMIC4_H\
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(RT715_SET_AMP_GAIN_MUTE_H | RT715_DMIC4)
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#define RT715_SET_GAIN_MIC1_L\
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(RT715_SET_AMP_GAIN_MUTE_L | RT715_MIC1)
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#define RT715_SET_GAIN_MIC1_H\
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(RT715_SET_AMP_GAIN_MUTE_H | RT715_MIC1)
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#define RT715_SET_GAIN_MIC2_L\
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(RT715_SET_AMP_GAIN_MUTE_L | RT715_MIC2)
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#define RT715_SET_GAIN_MIC2_H\
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(RT715_SET_AMP_GAIN_MUTE_H | RT715_MIC2)
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#define RT715_SET_GAIN_LINE1_L\
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(RT715_SET_AMP_GAIN_MUTE_L | RT715_LINE1)
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#define RT715_SET_GAIN_LINE1_H\
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(RT715_SET_AMP_GAIN_MUTE_H | RT715_LINE1)
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#define RT715_SET_GAIN_LINE2_L\
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(RT715_SET_AMP_GAIN_MUTE_L | RT715_LINE2)
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#define RT715_SET_GAIN_LINE2_H\
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(RT715_SET_AMP_GAIN_MUTE_H | RT715_LINE2)
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#define RT715_SET_DMIC1_CONFIG_DEFAULT1\
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(RT715_VERB_SET_CONFIG_DEFAULT1 | RT715_DMIC1)
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#define RT715_SET_DMIC2_CONFIG_DEFAULT1\
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(RT715_VERB_SET_CONFIG_DEFAULT1 | RT715_DMIC2)
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#define RT715_SET_DMIC1_CONFIG_DEFAULT2\
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(RT715_VERB_SET_CONFIG_DEFAULT2 | RT715_DMIC1)
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#define RT715_SET_DMIC2_CONFIG_DEFAULT2\
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(RT715_VERB_SET_CONFIG_DEFAULT2 | RT715_DMIC2)
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#define RT715_SET_DMIC1_CONFIG_DEFAULT3\
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(RT715_VERB_SET_CONFIG_DEFAULT3 | RT715_DMIC1)
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#define RT715_SET_DMIC2_CONFIG_DEFAULT3\
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(RT715_VERB_SET_CONFIG_DEFAULT3 | RT715_DMIC2)
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#define RT715_SET_DMIC1_CONFIG_DEFAULT4\
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(RT715_VERB_SET_CONFIG_DEFAULT4 | RT715_DMIC1)
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#define RT715_SET_DMIC2_CONFIG_DEFAULT4\
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(RT715_VERB_SET_CONFIG_DEFAULT4 | RT715_DMIC2)
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#define RT715_SET_DMIC3_CONFIG_DEFAULT1\
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(RT715_VERB_SET_CONFIG_DEFAULT1 | RT715_DMIC3)
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#define RT715_SET_DMIC4_CONFIG_DEFAULT1\
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(RT715_VERB_SET_CONFIG_DEFAULT1 | RT715_DMIC4)
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#define RT715_SET_DMIC3_CONFIG_DEFAULT2\
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(RT715_VERB_SET_CONFIG_DEFAULT2 | RT715_DMIC3)
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#define RT715_SET_DMIC4_CONFIG_DEFAULT2\
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(RT715_VERB_SET_CONFIG_DEFAULT2 | RT715_DMIC4)
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#define RT715_SET_DMIC3_CONFIG_DEFAULT3\
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(RT715_VERB_SET_CONFIG_DEFAULT3 | RT715_DMIC3)
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#define RT715_SET_DMIC4_CONFIG_DEFAULT3\
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(RT715_VERB_SET_CONFIG_DEFAULT3 | RT715_DMIC4)
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#define RT715_SET_DMIC3_CONFIG_DEFAULT4\
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(RT715_VERB_SET_CONFIG_DEFAULT4 | RT715_DMIC3)
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#define RT715_SET_DMIC4_CONFIG_DEFAULT4\
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(RT715_VERB_SET_CONFIG_DEFAULT4 | RT715_DMIC4)
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2023-08-10 17:27:45 +08:00
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/* vendor register clear ctrl-1 (0x01)(NID:20h) */
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#define RT715_CLEAR_HIDDEN_REG (0x1 << 15)
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2020-01-10 10:18:21 +08:00
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#define RT715_MUTE_SFT 7
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#define RT715_DIR_IN_SFT 6
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#define RT715_DIR_OUT_SFT 7
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enum {
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RT715_AIF1,
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RT715_AIF2,
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};
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2020-09-26 05:05:09 +08:00
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#define RT715_POWER_UP_DELAY_MS 400
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2020-01-10 10:18:21 +08:00
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int rt715_io_init(struct device *dev, struct sdw_slave *slave);
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int rt715_init(struct device *dev, struct regmap *sdw_regmap,
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struct regmap *regmap, struct sdw_slave *slave);
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int hda_to_sdw(unsigned int nid, unsigned int verb, unsigned int payload,
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unsigned int *sdw_addr_h, unsigned int *sdw_data_h,
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unsigned int *sdw_addr_l, unsigned int *sdw_data_l);
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int rt715_clock_config(struct device *dev);
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#endif /* __RT715_H__ */
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