2021-02-17 12:09:50 +08:00
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# SPDX-License-Identifier: GPL-2.0-only
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menuconfig CXL_BUS
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tristate "CXL (Compute Express Link) Devices Support"
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depends on PCI
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2023-07-03 19:29:13 +08:00
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select FW_LOADER
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select FW_UPLOAD
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2022-07-20 04:52:47 +08:00
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select PCI_DOE
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2021-02-17 12:09:50 +08:00
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help
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CXL is a bus that is electrically compatible with PCI Express, but
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layers three protocols on that signalling (CXL.io, CXL.cache, and
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CXL.mem). The CXL.cache protocol allows devices to hold cachelines
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locally, the CXL.mem protocol allows devices to be fully coherent
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memory targets, the CXL.io protocol is equivalent to PCI Express.
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Say 'y' to enable support for the configuration and management of
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devices supporting these protocols.
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if CXL_BUS
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2022-01-24 08:28:44 +08:00
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config CXL_PCI
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tristate "PCI manageability"
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2021-06-10 00:01:41 +08:00
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default CXL_BUS
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2021-02-17 12:09:50 +08:00
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help
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2022-01-24 08:28:44 +08:00
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The CXL specification defines a "CXL memory device" sub-class in the
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PCI "memory controller" base class of devices. Device's identified by
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this class code provide support for volatile and / or persistent
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memory to be mapped into the system address map (Host-managed Device
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Memory (HDM)).
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2021-02-17 12:09:50 +08:00
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2022-01-24 08:28:44 +08:00
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Say 'y/m' to enable a driver that will attach to CXL memory expander
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devices enumerated by the memory device class code for configuration
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and management primarily via the mailbox interface. See Chapter 2.3
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Type 3 CXL Device in the CXL 2.0 specification for more details.
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2021-02-17 12:09:50 +08:00
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If unsure say 'm'.
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2021-02-17 12:09:54 +08:00
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config CXL_MEM_RAW_COMMANDS
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bool "RAW Command Interface for Memory Devices"
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2022-01-24 08:28:44 +08:00
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depends on CXL_PCI
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2021-02-17 12:09:54 +08:00
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help
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Enable CXL RAW command interface.
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The CXL driver ioctl interface may assign a kernel ioctl command
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number for each specification defined opcode. At any given point in
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time the number of opcodes that the specification defines and a device
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may implement may exceed the kernel's set of associated ioctl function
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numbers. The mismatch is either by omission, specification is too new,
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or by design. When prototyping new hardware, or developing / debugging
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the driver it is useful to be able to submit any possible command to
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the hardware, even commands that may crash the kernel due to their
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potential impact to memory currently in use by the kernel.
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If developing CXL hardware or the driver say Y, otherwise say N.
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2021-06-10 00:01:35 +08:00
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config CXL_ACPI
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tristate "CXL ACPI: Platform Support"
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depends on ACPI
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2021-06-10 00:01:41 +08:00
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default CXL_BUS
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2021-10-30 03:51:48 +08:00
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select ACPI_TABLE_LIB
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2021-06-10 00:01:35 +08:00
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help
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Enable support for host managed device memory (HDM) resources
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published by a platform's ACPI CXL memory layout description. See
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Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
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specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
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(https://www.computeexpresslink.org/spec-landing). The CXL core
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consumes these resource to publish the root of a cxl_port decode
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hierarchy to map regions that represent System RAM, or Persistent
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Memory regions to be managed by LIBNVDIMM.
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2021-06-16 07:18:17 +08:00
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If unsure say 'm'.
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config CXL_PMEM
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tristate "CXL PMEM: Persistent Memory Support"
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depends on LIBNVDIMM
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default CXL_BUS
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help
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In addition to typical memory resources a platform may also advertise
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support for persistent memory attached via CXL. This support is
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managed via a bridge driver from CXL to the LIBNVDIMM system
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subsystem. Say 'y/m' to enable support for enumerating and
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provisioning the persistent memory capacity of CXL memory expanders.
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2021-06-10 00:01:35 +08:00
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If unsure say 'm'.
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2022-02-02 05:07:51 +08:00
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2022-02-04 23:18:31 +08:00
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config CXL_MEM
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tristate "CXL: Memory Expansion"
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depends on CXL_PCI
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default CXL_BUS
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help
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The CXL.mem protocol allows a device to act as a provider of "System
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RAM" and/or "Persistent Memory" that is fully coherent as if the
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memory were attached to the typical CPU memory controller. This is
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known as HDM "Host-managed Device Memory".
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Say 'y/m' to enable a driver that will attach to CXL.mem devices for
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memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
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specification for a detailed description of HDM.
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If unsure say 'm'.
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2022-02-02 05:07:51 +08:00
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config CXL_PORT
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default CXL_BUS
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tristate
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2022-04-23 06:58:11 +08:00
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config CXL_SUSPEND
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def_bool y
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depends on SUSPEND && CXL_MEM
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cxl/region: Add region creation support
CXL 2.0 allows for dynamic provisioning of new memory regions (system
physical address resources like "System RAM" and "Persistent Memory").
Whereas DDR and PMEM resources are conveyed statically at boot, CXL
allows for assembling and instantiating new regions from the available
capacity of CXL memory expanders in the system.
Sysfs with an "echo $region_name > $create_region_attribute" interface
is chosen as the mechanism to initiate the provisioning process. This
was chosen over ioctl() and netlink() to keep the configuration
interface entirely in a pseudo-fs interface, and it was chosen over
configfs since, aside from this one creation event, the interface is
read-mostly. I.e. configfs supports cases where an object is designed to
be provisioned each boot, like an iSCSI storage target, and CXL region
creation is mostly for PMEM regions which are created usually once
per-lifetime of a server instance. This is an improvement over nvdimm
that pre-created "seed" devices that tended to confuse users looking to
determine which devices are active and which are idle.
Recall that the major change that CXL brings over previous persistent
memory architectures is the ability to dynamically define new regions.
Compare that to drivers like 'nfit' where the region configuration is
statically defined by platform firmware.
Regions are created as a child of a root decoder that encompasses an
address space with constraints. When created through sysfs, the root
decoder is explicit. When created from an LSA's region structure a root
decoder will possibly need to be inferred by the driver.
Upon region creation through sysfs, a vacant region is created with a
unique name. Regions have a number of attributes that must be configured
before the region can be bound to the driver where HDM decoder program
is completed.
An example of creating a new region:
- Allocate a new region name:
region=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)
- Create a new region by name:
while
region=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)
! echo $region > /sys/bus/cxl/devices/decoder0.0/create_pmem_region
do true; done
- Region now exists in sysfs:
stat -t /sys/bus/cxl/devices/decoder0.0/$region
- Delete the region, and name:
echo $region > /sys/bus/cxl/devices/decoder0.0/delete_region
Signed-off-by: Ben Widawsky <bwidawsk@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165784333909.1758207.794374602146306032.stgit@dwillia2-xfh.jf.intel.com
[djbw: simplify locking, reword changelog]
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-06-09 01:28:34 +08:00
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config CXL_REGION
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2023-02-10 17:06:27 +08:00
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bool "CXL: Region Support"
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cxl/region: Add region creation support
CXL 2.0 allows for dynamic provisioning of new memory regions (system
physical address resources like "System RAM" and "Persistent Memory").
Whereas DDR and PMEM resources are conveyed statically at boot, CXL
allows for assembling and instantiating new regions from the available
capacity of CXL memory expanders in the system.
Sysfs with an "echo $region_name > $create_region_attribute" interface
is chosen as the mechanism to initiate the provisioning process. This
was chosen over ioctl() and netlink() to keep the configuration
interface entirely in a pseudo-fs interface, and it was chosen over
configfs since, aside from this one creation event, the interface is
read-mostly. I.e. configfs supports cases where an object is designed to
be provisioned each boot, like an iSCSI storage target, and CXL region
creation is mostly for PMEM regions which are created usually once
per-lifetime of a server instance. This is an improvement over nvdimm
that pre-created "seed" devices that tended to confuse users looking to
determine which devices are active and which are idle.
Recall that the major change that CXL brings over previous persistent
memory architectures is the ability to dynamically define new regions.
Compare that to drivers like 'nfit' where the region configuration is
statically defined by platform firmware.
Regions are created as a child of a root decoder that encompasses an
address space with constraints. When created through sysfs, the root
decoder is explicit. When created from an LSA's region structure a root
decoder will possibly need to be inferred by the driver.
Upon region creation through sysfs, a vacant region is created with a
unique name. Regions have a number of attributes that must be configured
before the region can be bound to the driver where HDM decoder program
is completed.
An example of creating a new region:
- Allocate a new region name:
region=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)
- Create a new region by name:
while
region=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)
! echo $region > /sys/bus/cxl/devices/decoder0.0/create_pmem_region
do true; done
- Region now exists in sysfs:
stat -t /sys/bus/cxl/devices/decoder0.0/$region
- Delete the region, and name:
echo $region > /sys/bus/cxl/devices/decoder0.0/delete_region
Signed-off-by: Ben Widawsky <bwidawsk@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165784333909.1758207.794374602146306032.stgit@dwillia2-xfh.jf.intel.com
[djbw: simplify locking, reword changelog]
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-06-09 01:28:34 +08:00
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default CXL_BUS
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2022-04-26 02:43:44 +08:00
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# For MAX_PHYSMEM_BITS
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depends on SPARSEMEM
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cxl/region: Add region creation support
CXL 2.0 allows for dynamic provisioning of new memory regions (system
physical address resources like "System RAM" and "Persistent Memory").
Whereas DDR and PMEM resources are conveyed statically at boot, CXL
allows for assembling and instantiating new regions from the available
capacity of CXL memory expanders in the system.
Sysfs with an "echo $region_name > $create_region_attribute" interface
is chosen as the mechanism to initiate the provisioning process. This
was chosen over ioctl() and netlink() to keep the configuration
interface entirely in a pseudo-fs interface, and it was chosen over
configfs since, aside from this one creation event, the interface is
read-mostly. I.e. configfs supports cases where an object is designed to
be provisioned each boot, like an iSCSI storage target, and CXL region
creation is mostly for PMEM regions which are created usually once
per-lifetime of a server instance. This is an improvement over nvdimm
that pre-created "seed" devices that tended to confuse users looking to
determine which devices are active and which are idle.
Recall that the major change that CXL brings over previous persistent
memory architectures is the ability to dynamically define new regions.
Compare that to drivers like 'nfit' where the region configuration is
statically defined by platform firmware.
Regions are created as a child of a root decoder that encompasses an
address space with constraints. When created through sysfs, the root
decoder is explicit. When created from an LSA's region structure a root
decoder will possibly need to be inferred by the driver.
Upon region creation through sysfs, a vacant region is created with a
unique name. Regions have a number of attributes that must be configured
before the region can be bound to the driver where HDM decoder program
is completed.
An example of creating a new region:
- Allocate a new region name:
region=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)
- Create a new region by name:
while
region=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)
! echo $region > /sys/bus/cxl/devices/decoder0.0/create_pmem_region
do true; done
- Region now exists in sysfs:
stat -t /sys/bus/cxl/devices/decoder0.0/$region
- Delete the region, and name:
echo $region > /sys/bus/cxl/devices/decoder0.0/delete_region
Signed-off-by: Ben Widawsky <bwidawsk@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165784333909.1758207.794374602146306032.stgit@dwillia2-xfh.jf.intel.com
[djbw: simplify locking, reword changelog]
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-06-09 01:28:34 +08:00
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select MEMREGION
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2022-04-26 02:43:44 +08:00
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select GET_FREE_REGION
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2023-02-10 17:06:27 +08:00
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help
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Enable the CXL core to enumerate and provision CXL regions. A CXL
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region is defined by one or more CXL expanders that decode a given
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system-physical address range. For CXL regions established by
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platform-firmware this option enables memory error handling to
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identify the devices participating in a given interleaved memory
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range. Otherwise, platform-firmware managed CXL is enabled by being
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placed in the system address map and does not need a driver.
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If unsure say 'y'
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cxl/region: Add region creation support
CXL 2.0 allows for dynamic provisioning of new memory regions (system
physical address resources like "System RAM" and "Persistent Memory").
Whereas DDR and PMEM resources are conveyed statically at boot, CXL
allows for assembling and instantiating new regions from the available
capacity of CXL memory expanders in the system.
Sysfs with an "echo $region_name > $create_region_attribute" interface
is chosen as the mechanism to initiate the provisioning process. This
was chosen over ioctl() and netlink() to keep the configuration
interface entirely in a pseudo-fs interface, and it was chosen over
configfs since, aside from this one creation event, the interface is
read-mostly. I.e. configfs supports cases where an object is designed to
be provisioned each boot, like an iSCSI storage target, and CXL region
creation is mostly for PMEM regions which are created usually once
per-lifetime of a server instance. This is an improvement over nvdimm
that pre-created "seed" devices that tended to confuse users looking to
determine which devices are active and which are idle.
Recall that the major change that CXL brings over previous persistent
memory architectures is the ability to dynamically define new regions.
Compare that to drivers like 'nfit' where the region configuration is
statically defined by platform firmware.
Regions are created as a child of a root decoder that encompasses an
address space with constraints. When created through sysfs, the root
decoder is explicit. When created from an LSA's region structure a root
decoder will possibly need to be inferred by the driver.
Upon region creation through sysfs, a vacant region is created with a
unique name. Regions have a number of attributes that must be configured
before the region can be bound to the driver where HDM decoder program
is completed.
An example of creating a new region:
- Allocate a new region name:
region=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)
- Create a new region by name:
while
region=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)
! echo $region > /sys/bus/cxl/devices/decoder0.0/create_pmem_region
do true; done
- Region now exists in sysfs:
stat -t /sys/bus/cxl/devices/decoder0.0/$region
- Delete the region, and name:
echo $region > /sys/bus/cxl/devices/decoder0.0/delete_region
Signed-off-by: Ben Widawsky <bwidawsk@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165784333909.1758207.794374602146306032.stgit@dwillia2-xfh.jf.intel.com
[djbw: simplify locking, reword changelog]
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-06-09 01:28:34 +08:00
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2022-12-02 06:03:41 +08:00
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config CXL_REGION_INVALIDATION_TEST
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bool "CXL: Region Cache Management Bypass (TEST)"
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depends on CXL_REGION
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help
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CXL Region management and security operations potentially invalidate
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2023-01-25 11:22:21 +08:00
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the content of CPU caches without notifying those caches to
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2022-12-02 06:03:41 +08:00
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invalidate the affected cachelines. The CXL Region driver attempts
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to invalidate caches when those events occur. If that invalidation
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fails the region will fail to enable. Reasons for cache
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invalidation failure are due to the CPU not providing a cache
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invalidation mechanism. For example usage of wbinvd is restricted to
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bare metal x86. However, for testing purposes toggling this option
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can disable that data integrity safety and proceed with enabling
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regions when there might be conflicting contents in the CPU cache.
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If unsure, or if this kernel is meant for production environments,
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say N.
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perf: CXL Performance Monitoring Unit driver
CXL rev 3.0 introduces a standard performance monitoring hardware
block to CXL. Instances are discovered using CXL Register Locator DVSEC
entries. Each CXL component may have multiple PMUs.
This initial driver supports a subset of types of counter.
It supports counters that are either fixed or configurable, but requires
that they support the ability to freeze and write value whilst frozen.
Development done with QEMU model which will be posted shortly.
Example:
$ perf stat -a -e cxl_pmu_mem0.0/h2d_req_snpcur/ -e cxl_pmu_mem0.0/h2d_req_snpdata/ -e cxl_pmu_mem0.0/clock_ticks/ sleep 1
Performance counter stats for 'system wide':
96,757,023,244,321 cxl_pmu_mem0.0/h2d_req_snpcur/
96,757,023,244,365 cxl_pmu_mem0.0/h2d_req_snpdata/
193,514,046,488,653 cxl_pmu_mem0.0/clock_ticks/
1.090539600 seconds time elapsed
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230526095824.16336-5-Jonathan.Cameron@huawei.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2023-05-26 17:58:23 +08:00
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config CXL_PMU
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tristate "CXL Performance Monitoring Unit"
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default CXL_BUS
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depends on PERF_EVENTS
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help
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Support performance monitoring as defined in CXL rev 3.0
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section 13.2: Performance Monitoring. CXL components may have
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one or more CXL Performance Monitoring Units (CPMUs).
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Say 'y/m' to enable a driver that will attach to performance
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monitoring units and provide standard perf based interfaces.
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If unsure say 'm'.
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2021-02-17 12:09:50 +08:00
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endif
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