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74 lines
1.8 KiB
YAML
74 lines
1.8 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic A1 Peripherals Clock Control Unit
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Jerome Brunet <jbrunet@baylibre.com>
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- Jian Hu <jian.hu@jian.hu.com>
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- Dmitry Rokosov <ddrokosov@sberdevices.ru>
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properties:
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compatible:
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const: amlogic,a1-peripherals-clkc
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'#clock-cells':
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const: 1
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reg:
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maxItems: 1
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clocks:
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items:
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- description: input fixed pll div2
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- description: input fixed pll div3
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- description: input fixed pll div5
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- description: input fixed pll div7
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- description: input hifi pll
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- description: input oscillator (usually at 24MHz)
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clock-names:
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items:
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- const: fclk_div2
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- const: fclk_div3
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- const: fclk_div5
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- const: fclk_div7
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- const: hifi_pll
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- const: xtal
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required:
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- compatible
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- '#clock-cells'
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- reg
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
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apb {
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#address-cells = <2>;
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#size-cells = <2>;
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clock-controller@800 {
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compatible = "amlogic,a1-peripherals-clkc";
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reg = <0 0x800 0 0x104>;
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#clock-cells = <1>;
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clocks = <&clkc_pll CLKID_FCLK_DIV2>,
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<&clkc_pll CLKID_FCLK_DIV3>,
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<&clkc_pll CLKID_FCLK_DIV5>,
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<&clkc_pll CLKID_FCLK_DIV7>,
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<&clkc_pll CLKID_HIFI_PLL>,
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<&xtal>;
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clock-names = "fclk_div2", "fclk_div3",
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"fclk_div5", "fclk_div7",
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"hifi_pll", "xtal";
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};
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};
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