2017-11-03 18:28:30 +08:00
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// SPDX-License-Identifier: GPL-2.0
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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/**
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* dwc3-pci.c - PCI Specific glue layer
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*/
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#include <linux/kernel.h>
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2011-08-23 13:08:54 +08:00
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#include <linux/module.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#include <linux/slab.h>
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#include <linux/pci.h>
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2017-09-27 19:19:21 +08:00
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#include <linux/workqueue.h>
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2016-05-17 15:15:02 +08:00
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#include <linux/pm_runtime.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#include <linux/platform_device.h>
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2015-05-13 20:26:50 +08:00
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#include <linux/gpio/consumer.h>
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#include <linux/acpi.h>
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2016-04-22 16:17:39 +08:00
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#include <linux/delay.h>
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2014-10-28 19:54:24 +08:00
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2015-09-26 14:47:53 +08:00
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#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
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#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
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#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
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#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
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#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
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#define PCI_DEVICE_ID_INTEL_BSW 0x22b7
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#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
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#define PCI_DEVICE_ID_INTEL_SPTH 0xa130
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2015-10-21 19:37:04 +08:00
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#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
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2016-04-01 22:13:10 +08:00
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#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
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2015-10-21 19:37:04 +08:00
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#define PCI_DEVICE_ID_INTEL_APL 0x5aaa
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2016-04-01 22:13:11 +08:00
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#define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
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2016-04-01 22:13:12 +08:00
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#define PCI_DEVICE_ID_INTEL_GLK 0x31aa
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2016-04-01 22:13:13 +08:00
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#define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
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#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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2017-06-06 00:40:46 +08:00
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#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
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2016-10-24 15:40:18 +08:00
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#define PCI_INTEL_BXT_FUNC_PMU_PWR 4
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#define PCI_INTEL_BXT_STATE_D0 0
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#define PCI_INTEL_BXT_STATE_D3 3
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2016-10-24 15:29:01 +08:00
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/**
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* struct dwc3_pci - Driver private structure
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* @dwc3: child dwc3 platform_device
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* @pci: our link to PCI bus
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2017-06-06 00:40:46 +08:00
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* @guid: _DSM GUID
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2016-10-24 15:40:18 +08:00
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* @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
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2016-10-24 15:29:01 +08:00
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*/
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struct dwc3_pci {
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struct platform_device *dwc3;
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struct pci_dev *pci;
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2016-10-24 15:40:18 +08:00
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2017-06-06 00:40:46 +08:00
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guid_t guid;
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2016-10-24 15:40:18 +08:00
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unsigned int has_dsm_for_pm:1;
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2017-09-27 19:19:21 +08:00
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struct work_struct wakeup_work;
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2016-10-24 15:29:01 +08:00
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};
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2015-05-13 20:26:50 +08:00
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static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
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static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
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static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
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{ "reset-gpios", &reset_gpios, 1 },
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{ "cs-gpios", &cs_gpios, 1 },
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{ },
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};
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2016-10-24 15:29:01 +08:00
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static int dwc3_pci_quirks(struct dwc3_pci *dwc)
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2015-01-12 20:20:14 +08:00
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{
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2016-10-24 15:29:01 +08:00
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struct platform_device *dwc3 = dwc->dwc3;
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struct pci_dev *pdev = dwc->pci;
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2015-01-12 20:20:14 +08:00
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if (pdev->vendor == PCI_VENDOR_ID_AMD &&
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pdev->device == PCI_DEVICE_ID_AMD_NL_USB) {
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2016-04-22 16:17:39 +08:00
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struct property_entry properties[] = {
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PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
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PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
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PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
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PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
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PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
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PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
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PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
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PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
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PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
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PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
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PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
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/*
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* FIXME these quirks should be removed when AMD NL
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* tapes out
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*/
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PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
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PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
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PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
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2016-11-29 08:30:58 +08:00
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PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
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2016-04-22 16:17:39 +08:00
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{ },
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};
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return platform_device_add_properties(dwc3, properties);
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2015-01-12 20:20:14 +08:00
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}
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2016-06-07 17:49:52 +08:00
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if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
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int ret;
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struct property_entry properties[] = {
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2016-12-27 19:13:42 +08:00
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PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
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2016-11-29 08:30:58 +08:00
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PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
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2016-06-07 17:49:52 +08:00
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{ }
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};
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ret = platform_device_add_properties(dwc3, properties);
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if (ret < 0)
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return ret;
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2016-10-24 15:40:18 +08:00
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if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
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pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
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2017-06-06 00:40:46 +08:00
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guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
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2016-10-24 15:40:18 +08:00
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dwc->has_dsm_for_pm = true;
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}
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2016-06-07 17:49:52 +08:00
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if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
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struct gpio_desc *gpio;
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2017-03-22 22:08:07 +08:00
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ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
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2016-06-07 17:49:52 +08:00
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acpi_dwc3_byt_gpios);
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2017-03-22 22:08:07 +08:00
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if (ret)
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dev_dbg(&pdev->dev, "failed to add mapping table\n");
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2016-06-07 17:49:52 +08:00
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/*
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* These GPIOs will turn on the USB2 PHY. Note that we have to
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* put the gpio descriptors again here because the phy driver
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* might want to grab them, too.
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*/
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gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
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if (IS_ERR(gpio))
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return PTR_ERR(gpio);
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2015-05-13 20:26:50 +08:00
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gpiod_set_value_cansleep(gpio, 1);
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gpiod_put(gpio);
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2016-06-07 17:49:52 +08:00
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gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
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if (IS_ERR(gpio))
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return PTR_ERR(gpio);
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if (gpio) {
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gpiod_set_value_cansleep(gpio, 1);
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gpiod_put(gpio);
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usleep_range(10000, 11000);
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}
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2015-05-13 20:26:50 +08:00
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}
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}
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2015-09-26 15:11:15 +08:00
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if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS &&
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(pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 ||
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pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI ||
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pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31)) {
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2016-04-22 16:17:39 +08:00
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struct property_entry properties[] = {
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PROPERTY_ENTRY_BOOL("snps,usb3_lpm_capable"),
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PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
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PROPERTY_ENTRY_BOOL("snps,dis_enblslpm_quirk"),
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2016-11-29 08:30:58 +08:00
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PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
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2016-04-22 16:17:39 +08:00
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{ },
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};
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return platform_device_add_properties(dwc3, properties);
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2015-09-26 15:11:15 +08:00
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}
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2015-01-12 20:20:14 +08:00
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return 0;
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}
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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2017-09-27 19:19:21 +08:00
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#ifdef CONFIG_PM
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static void dwc3_pci_resume_work(struct work_struct *work)
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{
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struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
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struct platform_device *dwc3 = dwc->dwc3;
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int ret;
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ret = pm_runtime_get_sync(&dwc3->dev);
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if (ret)
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return;
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pm_runtime_mark_last_busy(&dwc3->dev);
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pm_runtime_put_sync_autosuspend(&dwc3->dev);
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}
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#endif
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2012-11-20 02:21:48 +08:00
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static int dwc3_pci_probe(struct pci_dev *pci,
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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const struct pci_device_id *id)
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{
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2016-10-24 15:29:01 +08:00
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struct dwc3_pci *dwc;
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
struct resource res[2];
|
2014-05-15 20:53:32 +08:00
|
|
|
int ret;
|
2012-02-15 17:27:55 +08:00
|
|
|
struct device *dev = &pci->dev;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2014-05-15 20:53:33 +08:00
|
|
|
ret = pcim_enable_device(pci);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (ret) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "failed to enable pci device\n");
|
|
|
|
return -ENODEV;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
pci_set_master(pci);
|
|
|
|
|
2016-10-24 15:29:01 +08:00
|
|
|
dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
|
|
|
|
if (!dwc)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
|
|
|
|
if (!dwc->dwc3)
|
2014-05-15 20:53:33 +08:00
|
|
|
return -ENOMEM;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
|
|
|
|
|
|
|
|
res[0].start = pci_resource_start(pci, 0);
|
|
|
|
res[0].end = pci_resource_end(pci, 0);
|
|
|
|
res[0].name = "dwc_usb3";
|
|
|
|
res[0].flags = IORESOURCE_MEM;
|
|
|
|
|
|
|
|
res[1].start = pci->irq;
|
|
|
|
res[1].name = "dwc_usb3";
|
|
|
|
res[1].flags = IORESOURCE_IRQ;
|
|
|
|
|
2016-10-24 15:29:01 +08:00
|
|
|
ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (ret) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "couldn't add resources to dwc3 device\n");
|
2018-03-20 04:07:35 +08:00
|
|
|
goto err;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
2016-10-24 15:29:01 +08:00
|
|
|
dwc->pci = pci;
|
|
|
|
dwc->dwc3->dev.parent = dev;
|
|
|
|
ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2016-10-24 15:29:01 +08:00
|
|
|
ret = dwc3_pci_quirks(dwc);
|
2016-04-22 16:17:37 +08:00
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
2016-10-24 15:29:01 +08:00
|
|
|
ret = platform_device_add(dwc->dwc3);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (ret) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "failed to register dwc3 device\n");
|
2015-01-12 20:20:14 +08:00
|
|
|
goto err;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
2016-05-17 15:15:02 +08:00
|
|
|
device_init_wakeup(dev, true);
|
2016-10-24 15:29:01 +08:00
|
|
|
pci_set_drvdata(pci, dwc);
|
2016-05-17 15:15:02 +08:00
|
|
|
pm_runtime_put(dev);
|
2017-09-27 19:19:21 +08:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
|
|
|
|
#endif
|
2016-05-17 15:15:02 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
return 0;
|
2015-01-12 20:20:14 +08:00
|
|
|
err:
|
2016-10-24 15:29:01 +08:00
|
|
|
platform_device_put(dwc->dwc3);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-11-20 02:26:20 +08:00
|
|
|
static void dwc3_pci_remove(struct pci_dev *pci)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
2016-10-24 15:29:01 +08:00
|
|
|
struct dwc3_pci *dwc = pci_get_drvdata(pci);
|
|
|
|
|
2017-09-27 19:19:21 +08:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
cancel_work_sync(&dwc->wakeup_work);
|
|
|
|
#endif
|
2016-05-17 15:15:02 +08:00
|
|
|
device_init_wakeup(&pci->dev, false);
|
|
|
|
pm_runtime_get(&pci->dev);
|
2016-10-24 15:29:01 +08:00
|
|
|
platform_device_unregister(dwc->dwc3);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
2013-11-28 13:15:46 +08:00
|
|
|
static const struct pci_device_id dwc3_pci_id_table[] = {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
|
|
|
|
PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
|
|
|
|
},
|
2015-08-08 02:04:14 +08:00
|
|
|
{
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
|
|
|
|
PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI),
|
|
|
|
},
|
2015-08-08 02:47:25 +08:00
|
|
|
{
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
|
|
|
|
PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31),
|
|
|
|
},
|
2014-09-24 15:40:25 +08:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
|
2013-09-17 15:38:13 +08:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
|
2013-09-27 04:01:44 +08:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
|
2014-12-18 22:39:14 +08:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), },
|
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), },
|
2015-10-21 19:37:04 +08:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT), },
|
2016-04-01 22:13:10 +08:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT_M), },
|
2015-10-21 19:37:04 +08:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL), },
|
2016-04-01 22:13:11 +08:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBP), },
|
2016-04-01 22:13:12 +08:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK), },
|
2016-04-01 22:13:13 +08:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CNPLP), },
|
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CNPH), },
|
2014-10-31 11:11:17 +08:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), },
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{ } /* Terminating Entry */
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
|
|
|
|
|
2016-11-16 19:16:22 +08:00
|
|
|
#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
|
|
|
|
static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
|
|
|
|
{
|
|
|
|
union acpi_object *obj;
|
|
|
|
union acpi_object tmp;
|
|
|
|
union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
|
|
|
|
|
|
|
|
if (!dwc->has_dsm_for_pm)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
tmp.type = ACPI_TYPE_INTEGER;
|
|
|
|
tmp.integer.value = param;
|
|
|
|
|
2017-06-06 00:40:46 +08:00
|
|
|
obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
|
2016-11-16 19:16:22 +08:00
|
|
|
1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
|
|
|
|
if (!obj) {
|
|
|
|
dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
ACPI_FREE(obj);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PM || CONFIG_PM_SLEEP */
|
|
|
|
|
2016-05-17 15:15:02 +08:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int dwc3_pci_runtime_suspend(struct device *dev)
|
|
|
|
{
|
2016-10-24 15:40:18 +08:00
|
|
|
struct dwc3_pci *dwc = dev_get_drvdata(dev);
|
|
|
|
|
2017-06-24 07:58:53 +08:00
|
|
|
if (device_can_wakeup(dev))
|
2016-10-24 15:40:18 +08:00
|
|
|
return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
|
2016-05-17 15:15:02 +08:00
|
|
|
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2016-07-28 15:16:12 +08:00
|
|
|
static int dwc3_pci_runtime_resume(struct device *dev)
|
|
|
|
{
|
2016-10-24 15:29:01 +08:00
|
|
|
struct dwc3_pci *dwc = dev_get_drvdata(dev);
|
2016-10-24 15:40:18 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2016-07-28 15:16:12 +08:00
|
|
|
|
2017-09-27 19:19:21 +08:00
|
|
|
queue_work(pm_wq, &dwc->wakeup_work);
|
|
|
|
|
|
|
|
return 0;
|
2016-07-28 15:16:12 +08:00
|
|
|
}
|
2016-09-07 18:39:37 +08:00
|
|
|
#endif /* CONFIG_PM */
|
2016-07-28 15:16:12 +08:00
|
|
|
|
2016-09-07 18:39:37 +08:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2016-10-24 15:40:18 +08:00
|
|
|
static int dwc3_pci_suspend(struct device *dev)
|
2016-05-17 15:15:02 +08:00
|
|
|
{
|
2016-10-24 15:40:18 +08:00
|
|
|
struct dwc3_pci *dwc = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_pci_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct dwc3_pci *dwc = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
|
2016-05-17 15:15:02 +08:00
|
|
|
}
|
2016-09-07 18:39:37 +08:00
|
|
|
#endif /* CONFIG_PM_SLEEP */
|
2016-05-17 15:15:02 +08:00
|
|
|
|
2017-08-08 19:20:16 +08:00
|
|
|
static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
|
2016-10-24 15:40:18 +08:00
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
|
2016-07-28 15:16:12 +08:00
|
|
|
SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
|
2016-05-17 15:15:02 +08:00
|
|
|
NULL)
|
|
|
|
};
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
static struct pci_driver dwc3_pci_driver = {
|
2011-10-12 15:44:56 +08:00
|
|
|
.name = "dwc3-pci",
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
.id_table = dwc3_pci_id_table,
|
|
|
|
.probe = dwc3_pci_probe,
|
2012-11-20 02:21:08 +08:00
|
|
|
.remove = dwc3_pci_remove,
|
2016-05-17 15:15:02 +08:00
|
|
|
.driver = {
|
|
|
|
.pm = &dwc3_pci_dev_pm_ops,
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
|
2013-06-30 19:15:11 +08:00
|
|
|
MODULE_LICENSE("GPL v2");
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
|
|
|
|
|
2011-11-19 02:14:24 +08:00
|
|
|
module_pci_driver(dwc3_pci_driver);
|