2013-03-27 23:49:34 +08:00
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/*
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* Device Tree Source for the r8a7790 SoC
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/ {
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compatible = "renesas,r8a7790";
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interrupt-parent = <&gic>;
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2013-03-29 15:49:17 +08:00
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#address-cells = <2>;
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#size-cells = <2>;
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2013-03-27 23:49:34 +08:00
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1300000000>;
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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2013-03-29 15:49:17 +08:00
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x1000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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2013-03-27 23:49:34 +08:00
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interrupts = <1 9 0xf04>;
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gic-cpuif@4 {
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compatible = "arm,gic-cpuif";
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cpuif-id = <4>;
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cpu = <&cpu0>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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2013-03-27 23:49:54 +08:00
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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2013-03-29 15:49:17 +08:00
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reg = <0 0xe61c0000 0 0x200>;
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2013-03-27 23:49:54 +08:00
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interrupt-parent = <&gic>;
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interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
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};
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2013-03-27 23:49:34 +08:00
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};
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