2018-03-15 19:03:52 +08:00
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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2015-12-07 05:52:06 +08:00
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/*
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2017-01-02 22:58:52 +08:00
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* Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
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2015-12-07 05:52:06 +08:00
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*
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* Copyright (C) 2015 Russell King
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*
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* This board is in development; the contents of this file work with
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* the A1 rev 2.0 of the board, which does not represent final
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* production board. Things will change, don't expect this file to
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* remain compatible info the future.
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*/
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/dts-v1/;
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2017-01-02 22:58:52 +08:00
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#include "armada-388-clearfog.dtsi"
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2015-12-07 05:52:06 +08:00
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/ {
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model = "SolidRun Clearfog A1";
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compatible = "solidrun,clearfog-a1", "marvell,armada388",
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"marvell,armada385", "marvell,armada380";
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2017-01-02 22:58:57 +08:00
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2017-01-02 22:59:02 +08:00
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soc {
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internal-regs {
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usb3@f0000 {
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/* CON2, nearest CPU, USB2 only. */
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status = "okay";
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};
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};
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2017-07-27 05:09:37 +08:00
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pcie {
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2017-01-02 22:59:02 +08:00
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pcie@3,0 {
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/* Port 2, Lane 0. CON2, nearest CPU. */
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reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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};
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};
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2017-01-02 22:58:57 +08:00
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dsa@0 {
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2017-01-18 02:22:19 +08:00
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status = "disabled";
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2017-01-02 22:58:57 +08:00
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compatible = "marvell,dsa";
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dsa,ethernet = <ð1>;
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dsa,mii-bus = <&mdio>;
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pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
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pinctrl-names = "default";
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#address-cells = <2>;
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#size-cells = <0>;
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switch@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4 0>;
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port@0 {
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reg = <0>;
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label = "lan5";
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan2";
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};
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port@4 {
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reg = <4>;
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label = "lan1";
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};
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port@5 {
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reg = <5>;
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label = "cpu";
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};
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port@6 {
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/* 88E1512 external phy */
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reg = <6>;
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label = "lan6";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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2017-01-02 22:59:12 +08:00
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&rear_button_pins>;
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pinctrl-names = "default";
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button_0 {
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/* The rear SW3 button */
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label = "Rear Button";
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gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <BTN_0>;
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};
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};
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2017-01-02 22:58:57 +08:00
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};
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ð1 {
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/* ethernet@30000 */
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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2017-01-02 22:59:02 +08:00
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&expander0 {
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/*
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* PCA9655 GPIO expander:
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* 0-CON3 CLKREQ#
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* 1-CON3 PERST#
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* 2-CON2 PERST#
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* 3-CON3 W_DISABLE
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* 4-CON2 CLKREQ#
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* 5-USB3 overcurrent
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* 6-USB3 power
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* 7-CON2 W_DISABLE
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* 8-JP4 P1
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* 9-JP4 P4
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* 10-JP4 P5
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* 11-m.2 DEVSLP
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* 12-SFP_LOS
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* 13-SFP_TX_FAULT
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* 14-SFP_TX_DISABLE
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* 15-SFP_MOD_DEF0
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*/
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pcie2_0_clkreq {
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gpio-hog;
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gpios = <4 GPIO_ACTIVE_LOW>;
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input;
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line-name = "pcie2.0-clkreq";
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};
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pcie2_0_w_disable {
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gpio-hog;
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gpios = <7 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "pcie2.0-w-disable";
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};
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};
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2017-01-18 02:22:19 +08:00
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&mdio {
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status = "okay";
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switch@4 {
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
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pinctrl-names = "default";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan5";
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan2";
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};
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port@4 {
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reg = <4>;
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label = "lan1";
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};
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port@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <ð1>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@6 {
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/* 88E1512 external phy */
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reg = <6>;
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label = "lan6";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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2017-03-25 20:53:10 +08:00
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&pinctrl {
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clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
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marvell,pins = "mpp46";
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marvell,function = "ref";
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};
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clearfog_dsa0_pins: clearfog-dsa0-pins {
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marvell,pins = "mpp23", "mpp41";
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marvell,function = "gpio";
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};
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clearfog_spi1_cs_pins: spi1-cs-pins {
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marvell,pins = "mpp55";
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marvell,function = "spi1";
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};
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rear_button_pins: rear-button-pins {
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marvell,pins = "mpp34";
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marvell,function = "gpio";
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};
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};
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2017-01-02 22:59:07 +08:00
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&spi1 {
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/*
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* Add SPI CS pins for clearfog:
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* CS0: W25Q32 (not populated on uSOM)
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* CS1:
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* CS2: mikrobus
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*/
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pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
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2016-07-13 17:55:18 +08:00
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};
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