usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/**
|
|
|
|
* gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
|
|
|
|
*
|
|
|
|
* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
|
|
|
|
*
|
|
|
|
* Authors: Felipe Balbi <balbi@ti.com>,
|
|
|
|
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions
|
|
|
|
* are met:
|
|
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions, and the following disclaimer,
|
|
|
|
* without modification.
|
|
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution.
|
|
|
|
* 3. The names of the above-listed copyright holders may not be used
|
|
|
|
* to endorse or promote products derived from this software without
|
|
|
|
* specific prior written permission.
|
|
|
|
*
|
|
|
|
* ALTERNATIVELY, this software may be distributed under the terms of the
|
|
|
|
* GNU General Public License ("GPL") version 2, as published by the Free
|
|
|
|
* Software Foundation.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
|
|
|
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
|
|
|
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
|
|
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
|
|
|
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
|
|
|
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
|
|
|
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
|
|
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
|
|
|
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
|
|
|
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
|
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/delay.h>
|
|
|
|
#include <linux/slab.h>
|
|
|
|
#include <linux/spinlock.h>
|
|
|
|
#include <linux/platform_device.h>
|
|
|
|
#include <linux/pm_runtime.h>
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
#include <linux/io.h>
|
|
|
|
#include <linux/list.h>
|
|
|
|
#include <linux/dma-mapping.h>
|
|
|
|
|
|
|
|
#include <linux/usb/ch9.h>
|
|
|
|
#include <linux/usb/gadget.h>
|
|
|
|
|
|
|
|
#include "core.h"
|
|
|
|
#include "gadget.h"
|
|
|
|
#include "io.h"
|
|
|
|
|
2012-01-03 00:25:43 +08:00
|
|
|
/**
|
|
|
|
* dwc3_gadget_set_test_mode - Enables USB2 Test Modes
|
|
|
|
* @dwc: pointer to our context structure
|
|
|
|
* @mode: the mode to set (J, K SE0 NAK, Force Enable)
|
|
|
|
*
|
|
|
|
* Caller should take care of locking. This function will
|
|
|
|
* return 0 on success or -EINVAL if wrong Test Selector
|
|
|
|
* is passed
|
|
|
|
*/
|
|
|
|
int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
reg &= ~DWC3_DCTL_TSTCTRL_MASK;
|
|
|
|
|
|
|
|
switch (mode) {
|
|
|
|
case TEST_J:
|
|
|
|
case TEST_K:
|
|
|
|
case TEST_SE0_NAK:
|
|
|
|
case TEST_PACKET:
|
|
|
|
case TEST_FORCE_EN:
|
|
|
|
reg |= mode << 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-01-03 00:55:57 +08:00
|
|
|
/**
|
|
|
|
* dwc3_gadget_set_link_state - Sets USB Link to a particular State
|
|
|
|
* @dwc: pointer to our context structure
|
|
|
|
* @state: the state to put link into
|
|
|
|
*
|
|
|
|
* Caller should take care of locking. This function will
|
2012-02-25 09:32:15 +08:00
|
|
|
* return 0 on success or -ETIMEDOUT.
|
2012-01-03 00:55:57 +08:00
|
|
|
*/
|
|
|
|
int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
|
|
|
|
{
|
2012-02-25 09:32:15 +08:00
|
|
|
int retries = 10000;
|
2012-01-03 00:55:57 +08:00
|
|
|
u32 reg;
|
|
|
|
|
2012-04-27 18:10:52 +08:00
|
|
|
/*
|
|
|
|
* Wait until device controller is ready. Only applies to 1.94a and
|
|
|
|
* later RTL.
|
|
|
|
*/
|
|
|
|
if (dwc->revision >= DWC3_REVISION_194A) {
|
|
|
|
while (--retries) {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
|
|
if (reg & DWC3_DSTS_DCNRD)
|
|
|
|
udelay(5);
|
|
|
|
else
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (retries <= 0)
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
2012-01-03 00:55:57 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
|
|
|
|
|
|
|
|
/* set requested state */
|
|
|
|
reg |= DWC3_DCTL_ULSTCHNGREQ(state);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
|
2012-04-27 18:10:52 +08:00
|
|
|
/*
|
|
|
|
* The following code is racy when called from dwc3_gadget_wakeup,
|
|
|
|
* and is not needed, at least on newer versions
|
|
|
|
*/
|
|
|
|
if (dwc->revision >= DWC3_REVISION_194A)
|
|
|
|
return 0;
|
|
|
|
|
2012-01-03 00:55:57 +08:00
|
|
|
/* wait for a change in DSTS */
|
2012-04-27 17:52:01 +08:00
|
|
|
retries = 10000;
|
2012-01-03 00:55:57 +08:00
|
|
|
while (--retries) {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
|
|
|
|
|
|
if (DWC3_DSTS_USBLNKST(reg) == state)
|
|
|
|
return 0;
|
|
|
|
|
2012-02-25 09:32:15 +08:00
|
|
|
udelay(5);
|
2012-01-03 00:55:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
dev_vdbg(dwc->dev, "link state change request timed out\n");
|
|
|
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
2012-01-19 00:04:09 +08:00
|
|
|
/**
|
|
|
|
* dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
|
|
|
|
* @dwc: pointer to our context structure
|
|
|
|
*
|
|
|
|
* This function will a best effort FIFO allocation in order
|
|
|
|
* to improve FIFO usage and throughput, while still allowing
|
|
|
|
* us to enable as many endpoints as possible.
|
|
|
|
*
|
|
|
|
* Keep in mind that this operation will be highly dependent
|
|
|
|
* on the configured size for RAM1 - which contains TxFifo -,
|
|
|
|
* the amount of endpoints enabled on coreConsultant tool, and
|
|
|
|
* the width of the Master Bus.
|
|
|
|
*
|
|
|
|
* In the ideal world, we would always be able to satisfy the
|
|
|
|
* following equation:
|
|
|
|
*
|
|
|
|
* ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
|
|
|
|
* (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
|
|
|
|
*
|
|
|
|
* Unfortunately, due to many variables that's not always the case.
|
|
|
|
*/
|
|
|
|
int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
int last_fifo_depth = 0;
|
|
|
|
int ram1_depth;
|
|
|
|
int fifo_size;
|
|
|
|
int mdwidth;
|
|
|
|
int num;
|
|
|
|
|
|
|
|
if (!dwc->needs_fifo_resize)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
|
|
|
|
mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
|
|
|
|
|
|
|
|
/* MDWIDTH is represented in bits, we need it in bytes */
|
|
|
|
mdwidth >>= 3;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME For now we will only allocate 1 wMaxPacketSize space
|
|
|
|
* for each enabled endpoint, later patches will come to
|
|
|
|
* improve this algorithm so that we better use the internal
|
|
|
|
* FIFO space
|
|
|
|
*/
|
|
|
|
for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
|
|
|
|
struct dwc3_ep *dep = dwc->eps[num];
|
|
|
|
int fifo_number = dep->number >> 1;
|
2012-02-02 19:01:12 +08:00
|
|
|
int mult = 1;
|
2012-01-19 00:04:09 +08:00
|
|
|
int tmp;
|
|
|
|
|
|
|
|
if (!(dep->number & 1))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!(dep->flags & DWC3_EP_ENABLED))
|
|
|
|
continue;
|
|
|
|
|
2012-03-13 02:25:24 +08:00
|
|
|
if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
|
|
|
|
|| usb_endpoint_xfer_isoc(dep->endpoint.desc))
|
2012-02-02 19:01:12 +08:00
|
|
|
mult = 3;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* REVISIT: the following assumes we will always have enough
|
|
|
|
* space available on the FIFO RAM for all possible use cases.
|
|
|
|
* Make sure that's true somehow and change FIFO allocation
|
|
|
|
* accordingly.
|
|
|
|
*
|
|
|
|
* If we have Bulk or Isochronous endpoints, we want
|
|
|
|
* them to be able to be very, very fast. So we're giving
|
|
|
|
* those endpoints a fifo_size which is enough for 3 full
|
|
|
|
* packets
|
|
|
|
*/
|
|
|
|
tmp = mult * (dep->endpoint.maxpacket + mdwidth);
|
2012-01-19 00:04:09 +08:00
|
|
|
tmp += mdwidth;
|
|
|
|
|
|
|
|
fifo_size = DIV_ROUND_UP(tmp, mdwidth);
|
2012-02-02 19:01:12 +08:00
|
|
|
|
2012-01-19 00:04:09 +08:00
|
|
|
fifo_size |= (last_fifo_depth << 16);
|
|
|
|
|
|
|
|
dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
|
|
|
|
dep->name, last_fifo_depth, fifo_size & 0xffff);
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
|
|
|
|
fifo_size);
|
|
|
|
|
|
|
|
last_fifo_depth += (fifo_size & 0xffff);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
|
|
|
|
int status)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
|
|
|
if (req->queued) {
|
2011-11-28 18:46:59 +08:00
|
|
|
if (req->request.num_mapped_sgs)
|
|
|
|
dep->busy_slot += req->request.num_mapped_sgs;
|
|
|
|
else
|
|
|
|
dep->busy_slot++;
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/*
|
|
|
|
* Skip LINK TRB. We can't use req->trb and check for
|
|
|
|
* DWC3_TRBCTL_LINK_TRB because it points the TRB we just
|
|
|
|
* completed (not the LINK TRB).
|
|
|
|
*/
|
|
|
|
if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
|
2012-03-13 02:25:24 +08:00
|
|
|
usb_endpoint_xfer_isoc(dep->endpoint.desc))
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dep->busy_slot++;
|
|
|
|
}
|
|
|
|
list_del(&req->list);
|
2011-11-28 18:46:59 +08:00
|
|
|
req->trb = NULL;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
if (req->request.status == -EINPROGRESS)
|
|
|
|
req->request.status = status;
|
|
|
|
|
2011-12-19 17:32:34 +08:00
|
|
|
usb_gadget_unmap_request(&dwc->gadget, &req->request,
|
|
|
|
req->direction);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
|
|
|
|
req, dep->name, req->request.actual,
|
|
|
|
req->request.length, status);
|
|
|
|
|
|
|
|
spin_unlock(&dwc->lock);
|
2011-12-19 17:32:34 +08:00
|
|
|
req->request.complete(&dep->endpoint, &req->request);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
spin_lock(&dwc->lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
|
|
|
|
{
|
|
|
|
switch (cmd) {
|
|
|
|
case DWC3_DEPCMD_DEPSTARTCFG:
|
|
|
|
return "Start New Configuration";
|
|
|
|
case DWC3_DEPCMD_ENDTRANSFER:
|
|
|
|
return "End Transfer";
|
|
|
|
case DWC3_DEPCMD_UPDATETRANSFER:
|
|
|
|
return "Update Transfer";
|
|
|
|
case DWC3_DEPCMD_STARTTRANSFER:
|
|
|
|
return "Start Transfer";
|
|
|
|
case DWC3_DEPCMD_CLEARSTALL:
|
|
|
|
return "Clear Stall";
|
|
|
|
case DWC3_DEPCMD_SETSTALL:
|
|
|
|
return "Set Stall";
|
2012-04-27 18:10:52 +08:00
|
|
|
case DWC3_DEPCMD_GETEPSTATE:
|
|
|
|
return "Get Endpoint State";
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
case DWC3_DEPCMD_SETTRANSFRESOURCE:
|
|
|
|
return "Set Endpoint Transfer Resource";
|
|
|
|
case DWC3_DEPCMD_SETEPCONFIG:
|
|
|
|
return "Set Endpoint Configuration";
|
|
|
|
default:
|
|
|
|
return "UNKNOWN command";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-04-24 21:19:11 +08:00
|
|
|
int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
|
|
|
|
{
|
|
|
|
u32 timeout = 500;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
|
|
|
|
|
|
|
|
do {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
|
|
|
|
if (!(reg & DWC3_DGCMD_CMDACT)) {
|
|
|
|
dev_vdbg(dwc->dev, "Command Complete --> %d\n",
|
|
|
|
DWC3_DGCMD_STATUS(reg));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We can't sleep here, because it's also called from
|
|
|
|
* interrupt context.
|
|
|
|
*/
|
|
|
|
timeout--;
|
|
|
|
if (!timeout)
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
udelay(1);
|
|
|
|
} while (1);
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
|
|
|
|
unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
|
|
|
|
{
|
|
|
|
struct dwc3_ep *dep = dwc->eps[ep];
|
2011-08-29 22:46:38 +08:00
|
|
|
u32 timeout = 500;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
|
|
|
|
dep->name,
|
2011-09-30 15:58:51 +08:00
|
|
|
dwc3_gadget_ep_cmd_string(cmd), params->param0,
|
|
|
|
params->param1, params->param2);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-09-30 15:58:51 +08:00
|
|
|
dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
|
|
|
|
do {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
|
|
|
|
if (!(reg & DWC3_DEPCMD_CMDACT)) {
|
2011-08-28 01:29:58 +08:00
|
|
|
dev_vdbg(dwc->dev, "Command Complete --> %d\n",
|
|
|
|
DWC3_DEPCMD_STATUS(reg));
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We can't sleep here, because it is also called from
|
|
|
|
* interrupt context.
|
|
|
|
*/
|
|
|
|
timeout--;
|
|
|
|
if (!timeout)
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
2011-08-29 22:46:38 +08:00
|
|
|
udelay(1);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
} while (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
|
2012-02-06 17:04:53 +08:00
|
|
|
struct dwc3_trb *trb)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
2011-09-30 15:58:45 +08:00
|
|
|
u32 offset = (char *) trb - (char *) dep->trb_pool;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
return dep->trb_pool_dma + offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
|
|
|
if (dep->trb_pool)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (dep->number == 0 || dep->number == 1)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
dep->trb_pool = dma_alloc_coherent(dwc->dev,
|
|
|
|
sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
|
|
|
|
&dep->trb_pool_dma, GFP_KERNEL);
|
|
|
|
if (!dep->trb_pool) {
|
|
|
|
dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
|
|
|
|
dep->name);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_free_trb_pool(struct dwc3_ep *dep)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
|
|
|
dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
|
|
|
|
dep->trb_pool, dep->trb_pool_dma);
|
|
|
|
|
|
|
|
dep->trb_pool = NULL;
|
|
|
|
dep->trb_pool_dma = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
|
|
|
|
{
|
|
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
|
|
u32 cmd;
|
|
|
|
|
|
|
|
memset(¶ms, 0x00, sizeof(params));
|
|
|
|
|
|
|
|
if (dep->number != 1) {
|
|
|
|
cmd = DWC3_DEPCMD_DEPSTARTCFG;
|
|
|
|
/* XferRscIdx == 0 for ep0 and 2 for the remaining */
|
2011-09-30 15:58:42 +08:00
|
|
|
if (dep->number > 1) {
|
|
|
|
if (dwc->start_config_issued)
|
|
|
|
return 0;
|
|
|
|
dwc->start_config_issued = true;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
cmd |= DWC3_DEPCMD_PARAM(2);
|
2011-09-30 15:58:42 +08:00
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
|
2011-11-29 19:11:21 +08:00
|
|
|
const struct usb_endpoint_descriptor *desc,
|
|
|
|
const struct usb_ss_ep_comp_descriptor *comp_desc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
|
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
|
|
|
|
|
|
memset(¶ms, 0x00, sizeof(params));
|
|
|
|
|
2011-09-30 15:58:51 +08:00
|
|
|
params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
|
|
|
|
| DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
|
|
|
|
| DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-09-30 15:58:51 +08:00
|
|
|
params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
|
|
|
|
| DWC3_DEPCFG_XFER_NOT_READY_EN;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-01-02 19:35:41 +08:00
|
|
|
if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
|
2011-09-30 15:58:51 +08:00
|
|
|
params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
|
|
|
|
| DWC3_DEPCFG_STREAM_EVENT_EN;
|
2011-09-30 15:58:47 +08:00
|
|
|
dep->stream_capable = true;
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (usb_endpoint_xfer_isoc(desc))
|
2011-09-30 15:58:51 +08:00
|
|
|
params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* We are doing 1:1 mapping for endpoints, meaning
|
|
|
|
* Physical Endpoints 2 maps to Logical Endpoint 2 and
|
|
|
|
* so on. We consider the direction bit as part of the physical
|
|
|
|
* endpoint number. So USB endpoint 0x81 is 0x03.
|
|
|
|
*/
|
2011-09-30 15:58:51 +08:00
|
|
|
params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* We must use the lower 16 TX FIFOs even though
|
|
|
|
* HW might have more
|
|
|
|
*/
|
|
|
|
if (dep->direction)
|
2011-09-30 15:58:51 +08:00
|
|
|
params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
if (desc->bInterval) {
|
2011-09-30 15:58:51 +08:00
|
|
|
params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dep->interval = 1 << (desc->bInterval - 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return dwc3_send_gadget_ep_cmd(dwc, dep->number,
|
|
|
|
DWC3_DEPCMD_SETEPCONFIG, ¶ms);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
|
|
|
|
{
|
|
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
|
|
|
|
|
|
memset(¶ms, 0x00, sizeof(params));
|
|
|
|
|
2011-09-30 15:58:51 +08:00
|
|
|
params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
return dwc3_send_gadget_ep_cmd(dwc, dep->number,
|
|
|
|
DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* __dwc3_gadget_ep_enable - Initializes a HW endpoint
|
|
|
|
* @dep: endpoint to be initialized
|
|
|
|
* @desc: USB Endpoint Descriptor
|
|
|
|
*
|
|
|
|
* Caller should take care of locking
|
|
|
|
*/
|
|
|
|
static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
|
2011-11-29 19:11:21 +08:00
|
|
|
const struct usb_endpoint_descriptor *desc,
|
|
|
|
const struct usb_ss_ep_comp_descriptor *comp_desc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
u32 reg;
|
|
|
|
int ret = -ENOMEM;
|
|
|
|
|
|
|
|
if (!(dep->flags & DWC3_EP_ENABLED)) {
|
|
|
|
ret = dwc3_gadget_start_config(dwc, dep);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-11-29 19:11:21 +08:00
|
|
|
ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (!(dep->flags & DWC3_EP_ENABLED)) {
|
2012-02-06 17:04:53 +08:00
|
|
|
struct dwc3_trb *trb_st_hw;
|
|
|
|
struct dwc3_trb *trb_link;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
ret = dwc3_gadget_set_xfer_resource(dwc, dep);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2012-03-13 02:25:24 +08:00
|
|
|
dep->endpoint.desc = desc;
|
2011-11-29 19:11:21 +08:00
|
|
|
dep->comp_desc = comp_desc;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dep->type = usb_endpoint_type(desc);
|
|
|
|
dep->flags |= DWC3_EP_ENABLED;
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
|
|
|
|
reg |= DWC3_DALEPENA_EP(dep->number);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
|
|
|
|
|
|
|
|
if (!usb_endpoint_xfer_isoc(desc))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
memset(&trb_link, 0, sizeof(trb_link));
|
|
|
|
|
2012-02-16 10:56:56 +08:00
|
|
|
/* Link TRB for ISOC. The HWO bit is never reset */
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
trb_st_hw = &dep->trb_pool[0];
|
|
|
|
|
2012-02-06 17:04:53 +08:00
|
|
|
trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-02-06 17:04:53 +08:00
|
|
|
trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
|
|
|
|
trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
|
|
|
|
trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
|
|
|
|
trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-08-29 19:56:37 +08:00
|
|
|
static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
|
|
|
|
static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
|
|
|
struct dwc3_request *req;
|
|
|
|
|
2011-08-29 19:56:37 +08:00
|
|
|
if (!list_empty(&dep->req_queued))
|
|
|
|
dwc3_stop_active_transfer(dwc, dep->number);
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
while (!list_empty(&dep->request_list)) {
|
|
|
|
req = next_request(&dep->request_list);
|
|
|
|
|
2011-08-29 19:56:37 +08:00
|
|
|
dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* __dwc3_gadget_ep_disable - Disables a HW endpoint
|
|
|
|
* @dep: the endpoint to disable
|
|
|
|
*
|
2011-08-29 19:56:37 +08:00
|
|
|
* This function also removes requests which are currently processed ny the
|
|
|
|
* hardware and those which are not yet scheduled.
|
|
|
|
* Caller should take care of locking.
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*/
|
|
|
|
static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
u32 reg;
|
|
|
|
|
2011-08-29 19:56:37 +08:00
|
|
|
dwc3_remove_requests(dwc, dep);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
|
|
|
|
reg &= ~DWC3_DALEPENA_EP(dep->number);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
|
|
|
|
|
2011-09-30 15:58:47 +08:00
|
|
|
dep->stream_capable = false;
|
2012-02-08 19:56:48 +08:00
|
|
|
dep->endpoint.desc = NULL;
|
2011-11-29 19:11:21 +08:00
|
|
|
dep->comp_desc = NULL;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dep->type = 0;
|
2011-09-30 15:58:47 +08:00
|
|
|
dep->flags = 0;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
|
|
|
|
const struct usb_endpoint_descriptor *desc)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
static int dwc3_gadget_ep_enable(struct usb_ep *ep,
|
|
|
|
const struct usb_endpoint_descriptor *desc)
|
|
|
|
{
|
|
|
|
struct dwc3_ep *dep;
|
|
|
|
struct dwc3 *dwc;
|
|
|
|
unsigned long flags;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
|
|
|
|
pr_debug("dwc3: invalid parameters\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!desc->wMaxPacketSize) {
|
|
|
|
pr_debug("dwc3: missing wMaxPacketSize\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dep = to_dwc3_ep(ep);
|
|
|
|
dwc = dep->dwc;
|
|
|
|
|
|
|
|
switch (usb_endpoint_type(desc)) {
|
|
|
|
case USB_ENDPOINT_XFER_CONTROL:
|
2012-02-23 14:38:46 +08:00
|
|
|
strlcat(dep->name, "-control", sizeof(dep->name));
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
break;
|
|
|
|
case USB_ENDPOINT_XFER_ISOC:
|
2012-02-23 14:38:46 +08:00
|
|
|
strlcat(dep->name, "-isoc", sizeof(dep->name));
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
break;
|
|
|
|
case USB_ENDPOINT_XFER_BULK:
|
2012-02-23 14:38:46 +08:00
|
|
|
strlcat(dep->name, "-bulk", sizeof(dep->name));
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
break;
|
|
|
|
case USB_ENDPOINT_XFER_INT:
|
2012-02-23 14:38:46 +08:00
|
|
|
strlcat(dep->name, "-int", sizeof(dep->name));
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(dwc->dev, "invalid endpoint transfer type\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dep->flags & DWC3_EP_ENABLED) {
|
|
|
|
dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
|
|
|
|
dep->name);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
2011-11-29 19:11:21 +08:00
|
|
|
ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_ep_disable(struct usb_ep *ep)
|
|
|
|
{
|
|
|
|
struct dwc3_ep *dep;
|
|
|
|
struct dwc3 *dwc;
|
|
|
|
unsigned long flags;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!ep) {
|
|
|
|
pr_debug("dwc3: invalid parameters\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dep = to_dwc3_ep(ep);
|
|
|
|
dwc = dep->dwc;
|
|
|
|
|
|
|
|
if (!(dep->flags & DWC3_EP_ENABLED)) {
|
|
|
|
dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
|
|
|
|
dep->name);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
snprintf(dep->name, sizeof(dep->name), "ep%d%s",
|
|
|
|
dep->number >> 1,
|
|
|
|
(dep->number & 1) ? "in" : "out");
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
ret = __dwc3_gadget_ep_disable(dep);
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
|
|
|
|
gfp_t gfp_flags)
|
|
|
|
{
|
|
|
|
struct dwc3_request *req;
|
|
|
|
struct dwc3_ep *dep = to_dwc3_ep(ep);
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
|
|
|
req = kzalloc(sizeof(*req), gfp_flags);
|
|
|
|
if (!req) {
|
|
|
|
dev_err(dwc->dev, "not enough memory\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
req->epnum = dep->number;
|
|
|
|
req->dep = dep;
|
|
|
|
|
|
|
|
return &req->request;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
|
|
|
|
struct usb_request *request)
|
|
|
|
{
|
|
|
|
struct dwc3_request *req = to_dwc3_request(request);
|
|
|
|
|
|
|
|
kfree(req);
|
|
|
|
}
|
|
|
|
|
2011-11-22 17:37:34 +08:00
|
|
|
/**
|
|
|
|
* dwc3_prepare_one_trb - setup one TRB from one request
|
|
|
|
* @dep: endpoint for which this request is prepared
|
|
|
|
* @req: dwc3_request pointer
|
|
|
|
*/
|
2011-11-28 18:25:01 +08:00
|
|
|
static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
|
2011-11-28 18:46:59 +08:00
|
|
|
struct dwc3_request *req, dma_addr_t dma,
|
|
|
|
unsigned length, unsigned last, unsigned chain)
|
2011-11-22 17:37:34 +08:00
|
|
|
{
|
2011-11-28 18:46:59 +08:00
|
|
|
struct dwc3 *dwc = dep->dwc;
|
2012-02-06 17:04:53 +08:00
|
|
|
struct dwc3_trb *trb;
|
2011-11-22 17:37:34 +08:00
|
|
|
|
|
|
|
unsigned int cur_slot;
|
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
|
|
|
|
dep->name, req, (unsigned long long) dma,
|
|
|
|
length, last ? " last" : "",
|
|
|
|
chain ? " chain" : "");
|
|
|
|
|
2012-02-06 17:04:53 +08:00
|
|
|
trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
|
2011-11-22 17:37:34 +08:00
|
|
|
cur_slot = dep->free_slot;
|
|
|
|
dep->free_slot++;
|
|
|
|
|
|
|
|
/* Skip the LINK-TRB on ISOC */
|
|
|
|
if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
|
2012-03-13 02:25:24 +08:00
|
|
|
usb_endpoint_xfer_isoc(dep->endpoint.desc))
|
2011-11-28 18:25:01 +08:00
|
|
|
return;
|
2011-11-22 17:37:34 +08:00
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
if (!req->trb) {
|
|
|
|
dwc3_gadget_move_request_queued(req);
|
2012-02-06 17:04:53 +08:00
|
|
|
req->trb = trb;
|
|
|
|
req->trb_dma = dwc3_trb_dma_offset(dep, trb);
|
2011-11-28 18:46:59 +08:00
|
|
|
}
|
2011-11-22 17:37:34 +08:00
|
|
|
|
2012-02-06 17:04:53 +08:00
|
|
|
trb->size = DWC3_TRB_SIZE_LENGTH(length);
|
|
|
|
trb->bpl = lower_32_bits(dma);
|
|
|
|
trb->bph = upper_32_bits(dma);
|
2011-11-22 17:37:34 +08:00
|
|
|
|
2012-03-13 02:25:24 +08:00
|
|
|
switch (usb_endpoint_type(dep->endpoint.desc)) {
|
2011-11-22 17:37:34 +08:00
|
|
|
case USB_ENDPOINT_XFER_CONTROL:
|
2012-02-06 17:04:53 +08:00
|
|
|
trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
|
2011-11-22 17:37:34 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case USB_ENDPOINT_XFER_ISOC:
|
2012-02-06 17:04:53 +08:00
|
|
|
trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
|
2011-11-22 17:37:34 +08:00
|
|
|
|
|
|
|
/* IOC every DWC3_TRB_NUM / 4 so we can refill */
|
|
|
|
if (!(cur_slot % (DWC3_TRB_NUM / 4)))
|
2012-02-06 17:04:53 +08:00
|
|
|
trb->ctrl |= DWC3_TRB_CTRL_IOC;
|
2011-11-22 17:37:34 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case USB_ENDPOINT_XFER_BULK:
|
|
|
|
case USB_ENDPOINT_XFER_INT:
|
2012-02-06 17:04:53 +08:00
|
|
|
trb->ctrl = DWC3_TRBCTL_NORMAL;
|
2011-11-22 17:37:34 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/*
|
|
|
|
* This is only possible with faulty memory because we
|
|
|
|
* checked it already :)
|
|
|
|
*/
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
|
2012-03-13 02:25:24 +08:00
|
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
2012-02-06 17:04:53 +08:00
|
|
|
trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
|
|
|
|
trb->ctrl |= DWC3_TRB_CTRL_CSP;
|
|
|
|
} else {
|
|
|
|
if (chain)
|
|
|
|
trb->ctrl |= DWC3_TRB_CTRL_CHN;
|
|
|
|
|
|
|
|
if (last)
|
|
|
|
trb->ctrl |= DWC3_TRB_CTRL_LST;
|
|
|
|
}
|
2011-11-22 17:37:34 +08:00
|
|
|
|
2012-03-13 02:25:24 +08:00
|
|
|
if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
|
2012-02-06 17:04:53 +08:00
|
|
|
trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
|
2011-11-22 17:37:34 +08:00
|
|
|
|
2012-02-06 17:04:53 +08:00
|
|
|
trb->ctrl |= DWC3_TRB_CTRL_HWO;
|
2011-11-22 17:37:34 +08:00
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/*
|
|
|
|
* dwc3_prepare_trbs - setup TRBs from requests
|
|
|
|
* @dep: endpoint for which requests are being prepared
|
|
|
|
* @starting: true if the endpoint is idle and no requests are queued.
|
|
|
|
*
|
2012-02-16 10:56:56 +08:00
|
|
|
* The function goes through the requests list and sets up TRBs for the
|
|
|
|
* transfers. The function returns once there are no more TRBs available or
|
|
|
|
* it runs out of requests.
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*/
|
2011-11-28 18:25:01 +08:00
|
|
|
static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
2011-11-28 18:25:01 +08:00
|
|
|
struct dwc3_request *req, *n;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
u32 trbs_left;
|
2012-02-15 19:35:06 +08:00
|
|
|
u32 max;
|
2011-11-22 17:37:34 +08:00
|
|
|
unsigned int last_one = 0;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
|
|
|
|
|
|
|
|
/* the first request must not be queued */
|
|
|
|
trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
|
2011-11-22 17:37:34 +08:00
|
|
|
|
2012-02-15 19:35:06 +08:00
|
|
|
/* Can't wrap around on a non-isoc EP since there's no link TRB */
|
2012-03-13 02:25:24 +08:00
|
|
|
if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
2012-02-15 19:35:06 +08:00
|
|
|
max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
|
|
|
|
if (trbs_left > max)
|
|
|
|
trbs_left = max;
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/*
|
2012-02-16 10:56:56 +08:00
|
|
|
* If busy & slot are equal than it is either full or empty. If we are
|
|
|
|
* starting to process requests then we are empty. Otherwise we are
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* full and don't do anything
|
|
|
|
*/
|
|
|
|
if (!trbs_left) {
|
|
|
|
if (!starting)
|
2011-11-28 18:25:01 +08:00
|
|
|
return;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
trbs_left = DWC3_TRB_NUM;
|
|
|
|
/*
|
|
|
|
* In case we start from scratch, we queue the ISOC requests
|
|
|
|
* starting from slot 1. This is done because we use ring
|
|
|
|
* buffer and have no LST bit to stop us. Instead, we place
|
2012-02-16 10:56:56 +08:00
|
|
|
* IOC bit every TRB_NUM/4. We try to avoid having an interrupt
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* after the first request so we start at slot 1 and have
|
|
|
|
* 7 requests proceed before we hit the first IOC.
|
|
|
|
* Other transfer types don't use the ring buffer and are
|
|
|
|
* processed from the first TRB until the last one. Since we
|
|
|
|
* don't wrap around we have to start at the beginning.
|
|
|
|
*/
|
2012-03-13 02:25:24 +08:00
|
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dep->busy_slot = 1;
|
|
|
|
dep->free_slot = 1;
|
|
|
|
} else {
|
|
|
|
dep->busy_slot = 0;
|
|
|
|
dep->free_slot = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The last TRB is a link TRB, not used for xfer */
|
2012-03-13 02:25:24 +08:00
|
|
|
if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
|
2011-11-28 18:25:01 +08:00
|
|
|
return;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
list_for_each_entry_safe(req, n, &dep->request_list, list) {
|
2011-11-28 18:46:59 +08:00
|
|
|
unsigned length;
|
|
|
|
dma_addr_t dma;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
if (req->request.num_mapped_sgs > 0) {
|
|
|
|
struct usb_request *request = &req->request;
|
|
|
|
struct scatterlist *sg = request->sg;
|
|
|
|
struct scatterlist *s;
|
|
|
|
int i;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
for_each_sg(sg, s, request->num_mapped_sgs, i) {
|
|
|
|
unsigned chain = true;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
length = sg_dma_len(s);
|
|
|
|
dma = sg_dma_address(s);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-02-16 10:56:56 +08:00
|
|
|
if (i == (request->num_mapped_sgs - 1) ||
|
|
|
|
sg_is_last(s)) {
|
2011-11-28 18:46:59 +08:00
|
|
|
last_one = true;
|
|
|
|
chain = false;
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
trbs_left--;
|
|
|
|
if (!trbs_left)
|
|
|
|
last_one = true;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
if (last_one)
|
|
|
|
chain = false;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
dwc3_prepare_one_trb(dep, req, dma, length,
|
|
|
|
last_one, chain);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
if (last_one)
|
|
|
|
break;
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
} else {
|
2011-11-28 18:46:59 +08:00
|
|
|
dma = req->request.dma;
|
|
|
|
length = req->request.length;
|
|
|
|
trbs_left--;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
if (!trbs_left)
|
|
|
|
last_one = 1;
|
2011-09-30 15:58:47 +08:00
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
/* Is this the last request? */
|
|
|
|
if (list_is_last(&req->list, &dep->request_list))
|
|
|
|
last_one = 1;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
dwc3_prepare_one_trb(dep, req, dma, length,
|
|
|
|
last_one, false);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-11-28 18:46:59 +08:00
|
|
|
if (last_one)
|
|
|
|
break;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
|
|
|
|
int start_new)
|
|
|
|
{
|
|
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
|
|
struct dwc3_request *req;
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
int ret;
|
|
|
|
u32 cmd;
|
|
|
|
|
|
|
|
if (start_new && (dep->flags & DWC3_EP_BUSY)) {
|
|
|
|
dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
dep->flags &= ~DWC3_EP_PENDING_REQUEST;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we are getting here after a short-out-packet we don't enqueue any
|
|
|
|
* new requests as we try to set the IOC bit only on the last request.
|
|
|
|
*/
|
|
|
|
if (start_new) {
|
|
|
|
if (list_empty(&dep->req_queued))
|
|
|
|
dwc3_prepare_trbs(dep, start_new);
|
|
|
|
|
|
|
|
/* req points to the first request which will be sent */
|
|
|
|
req = next_request(&dep->req_queued);
|
|
|
|
} else {
|
2011-11-28 18:25:01 +08:00
|
|
|
dwc3_prepare_trbs(dep, start_new);
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/*
|
2012-02-16 10:56:56 +08:00
|
|
|
* req points to the first request where HWO changed from 0 to 1
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*/
|
2011-11-28 18:25:01 +08:00
|
|
|
req = next_request(&dep->req_queued);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
if (!req) {
|
|
|
|
dep->flags |= DWC3_EP_PENDING_REQUEST;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
memset(¶ms, 0, sizeof(params));
|
2011-09-30 15:58:51 +08:00
|
|
|
params.param0 = upper_32_bits(req->trb_dma);
|
|
|
|
params.param1 = lower_32_bits(req->trb_dma);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
if (start_new)
|
|
|
|
cmd = DWC3_DEPCMD_STARTTRANSFER;
|
|
|
|
else
|
|
|
|
cmd = DWC3_DEPCMD_UPDATETRANSFER;
|
|
|
|
|
|
|
|
cmd |= DWC3_DEPCMD_PARAM(cmd_param);
|
|
|
|
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME we need to iterate over the list of requests
|
|
|
|
* here and stop, unmap, free and del each of the linked
|
2012-02-16 10:56:56 +08:00
|
|
|
* requests instead of what we do now.
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*/
|
2011-12-19 17:32:34 +08:00
|
|
|
usb_gadget_unmap_request(&dwc->gadget, &req->request,
|
|
|
|
req->direction);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
list_del(&req->list);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
dep->flags |= DWC3_EP_BUSY;
|
2011-11-04 18:32:47 +08:00
|
|
|
|
2012-03-30 02:16:54 +08:00
|
|
|
if (start_new) {
|
|
|
|
dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
|
|
|
|
dep->number);
|
|
|
|
WARN_ON_ONCE(!dep->res_trans_idx);
|
|
|
|
}
|
2011-11-04 18:32:47 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
|
|
|
|
{
|
2011-12-19 17:32:34 +08:00
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
int ret;
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
req->request.actual = 0;
|
|
|
|
req->request.status = -EINPROGRESS;
|
|
|
|
req->direction = dep->direction;
|
|
|
|
req->epnum = dep->number;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We only add to our list of requests now and
|
|
|
|
* start consuming the list once we get XferNotReady
|
|
|
|
* IRQ.
|
|
|
|
*
|
|
|
|
* That way, we avoid doing anything that we don't need
|
|
|
|
* to do now and defer it until the point we receive a
|
|
|
|
* particular token from the Host side.
|
|
|
|
*
|
|
|
|
* This will also avoid Host cancelling URBs due to too
|
2012-02-16 10:56:56 +08:00
|
|
|
* many NAKs.
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*/
|
2011-12-19 17:32:34 +08:00
|
|
|
ret = usb_gadget_map_request(&dwc->gadget, &req->request,
|
|
|
|
dep->direction);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
list_add_tail(&req->list, &dep->request_list);
|
|
|
|
|
usb: dwc3: patches for v3.5 merge window
This pull request contains one workaround for a Silicon
Issue found on all RTL releases prior to 2.20a, which
would cause a metastability state on Run/Stop bit.
We also have some patches implementing a few extra Standard
requests introduced by USB3 spec (Set SEL and Set Isoch Delay),
as well as one patch, which has been pending for a long time,
implementing LPM support.
Last, but not least, we are splitting the host address space
out of the dwc3 core driver otherwise xHCI won't be able to
request_mem_region() its own address space. This patch is
only needed because we are (as we should) re-using the xHCI
driver, which is a completely separate module.
Together with these three big changes, come a few extra preparatory
patches which most move code around, define macros and so on, as
well as a fix for Isochronous transfers which hasn't been triggered
before.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJPo7lXAAoJEIaOsuA1yqRESaIP/AgxZIfOAUbPx0GWLnhub3qr
SxaUplweFc9q4KXRLn0kGdY9QArPR3bqW9g8KOTiRCBYRtjpACyMjibAUaAht81h
+vLdPt87Slj2c14t1uguWFvgCUYQOCugkVvDIjRg9PCLIuTahm4cIBFqL3RJOHFf
9WCd8JjH9ahr85ZtoCBk9B5bDNn71nS+Yh6/8+Ab90AE4vZ6t8Xx3+wLTHy2CBYQ
UH1o61QZreAJ0J3OiUobjqrVbYwz6TM0dFYMjA6ko+OiPRhVOj8/C8aNl/U1whRm
+7jjJiWO9aHp+Tu2OAQOBF6ydc3ZLBEiCl9RiE+O9MppmtOykzkTHFm1ZXatCEY7
UUYOy43VXLNlHoz8nidNw6P25hAwwlSijzlyawpihKbIaE8le2MpE6I00AlciM2q
BEo4LpluC8Rr6CUUr5W9dPZUexRlzxdAL5nQSJUnJgfEPphpP3x7dWTxUZBaWjq6
akqjgGqVj1QKwMnqL4GILtRgdqWj6WYrw67fYVLHqj8QQla4cgXQ2sHp9/R0imvT
nmjiL5ZiuIWWr965DgVHZwqIkdvMpSQb99a1xmptw8lFDGkVJDCssPDdEErbBMwy
KmOSaqKeg/Yway05i+Pwo/NUKHQSZeiyuguzniMrF7iYFF1/2hVYRgfpH4V+95w/
Xrnz4uH2YJGQGPddf87P
=qgf/
-----END PGP SIGNATURE-----
Merge tag 'dwc3-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
usb: dwc3: patches for v3.5 merge window
This pull request contains one workaround for a Silicon
Issue found on all RTL releases prior to 2.20a, which
would cause a metastability state on Run/Stop bit.
We also have some patches implementing a few extra Standard
requests introduced by USB3 spec (Set SEL and Set Isoch Delay),
as well as one patch, which has been pending for a long time,
implementing LPM support.
Last, but not least, we are splitting the host address space
out of the dwc3 core driver otherwise xHCI won't be able to
request_mem_region() its own address space. This patch is
only needed because we are (as we should) re-using the xHCI
driver, which is a completely separate module.
Together with these three big changes, come a few extra preparatory
patches which most move code around, define macros and so on, as
well as a fix for Isochronous transfers which hasn't been triggered
before.
[ resolved conflicts and build error in drivers/usb/dwc3/gadget.c - gregkh]
2012-05-08 01:09:55 +08:00
|
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && (dep->flags & DWC3_EP_BUSY))
|
2012-03-30 02:16:54 +08:00
|
|
|
dep->flags |= DWC3_EP_PENDING_REQUEST;
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/*
|
2012-03-30 02:16:54 +08:00
|
|
|
* There are two special cases:
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*
|
2012-03-30 02:16:54 +08:00
|
|
|
* 1. XferNotReady with empty list of requests. We need to kick the
|
|
|
|
* transfer here in that situation, otherwise we will be NAKing
|
|
|
|
* forever. If we get XferNotReady before gadget driver has a
|
|
|
|
* chance to queue a request, we will ACK the IRQ but won't be
|
|
|
|
* able to receive the data until the next request is queued.
|
|
|
|
* The following code is handling exactly that.
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*
|
2012-03-30 02:16:54 +08:00
|
|
|
* 2. XferInProgress on Isoc EP with an active transfer. We need to
|
|
|
|
* kick the transfer here after queuing a request, otherwise the
|
|
|
|
* core may not see the modified TRB(s).
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*/
|
|
|
|
if (dep->flags & DWC3_EP_PENDING_REQUEST) {
|
2012-03-30 02:16:54 +08:00
|
|
|
int ret;
|
|
|
|
int start_trans = 1;
|
|
|
|
u8 trans_idx = dep->res_trans_idx;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-03-13 02:25:24 +08:00
|
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
|
2012-03-30 02:16:54 +08:00
|
|
|
(dep->flags & DWC3_EP_BUSY)) {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
start_trans = 0;
|
2012-03-30 02:16:54 +08:00
|
|
|
WARN_ON_ONCE(!trans_idx);
|
|
|
|
} else {
|
|
|
|
trans_idx = 0;
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-03-30 02:16:54 +08:00
|
|
|
ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (ret && ret != -EBUSY) {
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
|
|
|
dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
|
|
|
|
dep->name);
|
|
|
|
}
|
2012-05-22 15:24:11 +08:00
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
|
|
|
|
gfp_t gfp_flags)
|
|
|
|
{
|
|
|
|
struct dwc3_request *req = to_dwc3_request(request);
|
|
|
|
struct dwc3_ep *dep = to_dwc3_ep(ep);
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
int ret;
|
|
|
|
|
2012-03-13 02:25:24 +08:00
|
|
|
if (!dep->endpoint.desc) {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
|
|
|
|
request, ep->name);
|
|
|
|
return -ESHUTDOWN;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
|
|
|
|
request, ep->name, request->length);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
ret = __dwc3_gadget_ep_queue(dep, req);
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
|
|
|
|
struct usb_request *request)
|
|
|
|
{
|
|
|
|
struct dwc3_request *req = to_dwc3_request(request);
|
|
|
|
struct dwc3_request *r = NULL;
|
|
|
|
|
|
|
|
struct dwc3_ep *dep = to_dwc3_ep(ep);
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
|
|
|
unsigned long flags;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
|
|
|
list_for_each_entry(r, &dep->request_list, list) {
|
|
|
|
if (r == req)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (r != req) {
|
|
|
|
list_for_each_entry(r, &dep->req_queued, list) {
|
|
|
|
if (r == req)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (r == req) {
|
|
|
|
/* wait until it is processed */
|
|
|
|
dwc3_stop_active_transfer(dwc, dep->number);
|
|
|
|
goto out0;
|
|
|
|
}
|
|
|
|
dev_err(dwc->dev, "request %p was not queued to %s\n",
|
|
|
|
request, ep->name);
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* giveback the request */
|
|
|
|
dwc3_gadget_giveback(dep, req, -ECONNRESET);
|
|
|
|
|
|
|
|
out0:
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
|
|
|
|
{
|
|
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
memset(¶ms, 0x00, sizeof(params));
|
|
|
|
|
|
|
|
if (value) {
|
2011-08-30 20:48:08 +08:00
|
|
|
if (dep->number == 0 || dep->number == 1) {
|
|
|
|
/*
|
|
|
|
* Whenever EP0 is stalled, we will restart
|
|
|
|
* the state machine, thus moving back to
|
|
|
|
* Setup Phase
|
|
|
|
*/
|
|
|
|
dwc->ep0state = EP0_SETUP_PHASE;
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
|
|
|
|
DWC3_DEPCMD_SETSTALL, ¶ms);
|
|
|
|
if (ret)
|
|
|
|
dev_err(dwc->dev, "failed to %s STALL on %s\n",
|
|
|
|
value ? "set" : "clear",
|
|
|
|
dep->name);
|
|
|
|
else
|
|
|
|
dep->flags |= DWC3_EP_STALL;
|
|
|
|
} else {
|
2011-09-30 15:58:44 +08:00
|
|
|
if (dep->flags & DWC3_EP_WEDGE)
|
|
|
|
return 0;
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
|
|
|
|
DWC3_DEPCMD_CLEARSTALL, ¶ms);
|
|
|
|
if (ret)
|
|
|
|
dev_err(dwc->dev, "failed to %s STALL on %s\n",
|
|
|
|
value ? "set" : "clear",
|
|
|
|
dep->name);
|
|
|
|
else
|
|
|
|
dep->flags &= ~DWC3_EP_STALL;
|
|
|
|
}
|
2011-09-30 15:58:44 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
|
|
|
|
{
|
|
|
|
struct dwc3_ep *dep = to_dwc3_ep(ep);
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
2012-03-13 02:25:24 +08:00
|
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = __dwc3_gadget_ep_set_halt(dep, value);
|
|
|
|
out:
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
|
|
|
|
{
|
|
|
|
struct dwc3_ep *dep = to_dwc3_ep(ep);
|
2012-02-25 09:32:16 +08:00
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
unsigned long flags;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-02-25 09:32:16 +08:00
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dep->flags |= DWC3_EP_WEDGE;
|
2012-02-25 09:32:16 +08:00
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-09-30 15:58:44 +08:00
|
|
|
return dwc3_gadget_ep_set_halt(ep, 1);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
|
|
|
|
.bLength = USB_DT_ENDPOINT_SIZE,
|
|
|
|
.bDescriptorType = USB_DT_ENDPOINT,
|
|
|
|
.bmAttributes = USB_ENDPOINT_XFER_CONTROL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
|
|
|
|
.enable = dwc3_gadget_ep0_enable,
|
|
|
|
.disable = dwc3_gadget_ep0_disable,
|
|
|
|
.alloc_request = dwc3_gadget_ep_alloc_request,
|
|
|
|
.free_request = dwc3_gadget_ep_free_request,
|
|
|
|
.queue = dwc3_gadget_ep0_queue,
|
|
|
|
.dequeue = dwc3_gadget_ep_dequeue,
|
|
|
|
.set_halt = dwc3_gadget_ep_set_halt,
|
|
|
|
.set_wedge = dwc3_gadget_ep_set_wedge,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct usb_ep_ops dwc3_gadget_ep_ops = {
|
|
|
|
.enable = dwc3_gadget_ep_enable,
|
|
|
|
.disable = dwc3_gadget_ep_disable,
|
|
|
|
.alloc_request = dwc3_gadget_ep_alloc_request,
|
|
|
|
.free_request = dwc3_gadget_ep_free_request,
|
|
|
|
.queue = dwc3_gadget_ep_queue,
|
|
|
|
.dequeue = dwc3_gadget_ep_dequeue,
|
|
|
|
.set_halt = dwc3_gadget_ep_set_halt,
|
|
|
|
.set_wedge = dwc3_gadget_ep_set_wedge,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
static int dwc3_gadget_get_frame(struct usb_gadget *g)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = gadget_to_dwc(g);
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
|
|
return DWC3_DSTS_SOFFN(reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_wakeup(struct usb_gadget *g)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = gadget_to_dwc(g);
|
|
|
|
|
|
|
|
unsigned long timeout;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
u8 link_state;
|
|
|
|
u8 speed;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* According to the Databook Remote wakeup request should
|
|
|
|
* be issued only when the device is in early suspend state.
|
|
|
|
*
|
|
|
|
* We can check that via USB Link State bits in DSTS register.
|
|
|
|
*/
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
|
|
|
|
|
|
speed = reg & DWC3_DSTS_CONNECTSPD;
|
|
|
|
if (speed == DWC3_DSTS_SUPERSPEED) {
|
|
|
|
dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
link_state = DWC3_DSTS_USBLNKST(reg);
|
|
|
|
|
|
|
|
switch (link_state) {
|
|
|
|
case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
|
|
|
|
case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
|
|
|
|
link_state);
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2012-01-03 00:55:57 +08:00
|
|
|
ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(dwc->dev, "failed to put link in Recovery\n");
|
|
|
|
goto out;
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-04-27 18:10:52 +08:00
|
|
|
/* Recent versions do this automatically */
|
|
|
|
if (dwc->revision < DWC3_REVISION_194A) {
|
|
|
|
/* write zeroes to Link Change Request */
|
2012-05-24 15:27:56 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
2012-04-27 18:10:52 +08:00
|
|
|
reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-02-16 10:56:56 +08:00
|
|
|
/* poll until Link State changes to ON */
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
timeout = jiffies + msecs_to_jiffies(100);
|
|
|
|
|
2012-02-16 10:56:56 +08:00
|
|
|
while (!time_after(jiffies, timeout)) {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
|
|
|
|
|
|
/* in HS, means ON */
|
|
|
|
if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
|
|
|
|
dev_err(dwc->dev, "failed to send remote wakeup\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
|
|
|
|
int is_selfpowered)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = gadget_to_dwc(g);
|
2012-02-25 09:32:16 +08:00
|
|
|
unsigned long flags;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-02-25 09:32:16 +08:00
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc->is_selfpowered = !!is_selfpowered;
|
2012-02-25 09:32:16 +08:00
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
|
|
|
|
{
|
|
|
|
u32 reg;
|
2011-08-29 22:46:38 +08:00
|
|
|
u32 timeout = 500;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
2012-01-19 00:32:29 +08:00
|
|
|
if (is_on) {
|
2012-04-27 18:10:52 +08:00
|
|
|
if (dwc->revision <= DWC3_REVISION_187A) {
|
|
|
|
reg &= ~DWC3_DCTL_TRGTULST_MASK;
|
|
|
|
reg |= DWC3_DCTL_TRGTULST_RX_DET;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dwc->revision >= DWC3_REVISION_194A)
|
|
|
|
reg &= ~DWC3_DCTL_KEEP_CONNECT;
|
|
|
|
reg |= DWC3_DCTL_RUN_STOP;
|
2012-01-19 00:32:29 +08:00
|
|
|
} else {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
reg &= ~DWC3_DCTL_RUN_STOP;
|
2012-01-19 00:32:29 +08:00
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
|
|
|
|
do {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
|
|
if (is_on) {
|
|
|
|
if (!(reg & DWC3_DSTS_DEVCTRLHLT))
|
|
|
|
break;
|
|
|
|
} else {
|
|
|
|
if (reg & DWC3_DSTS_DEVCTRLHLT)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
timeout--;
|
|
|
|
if (!timeout)
|
|
|
|
break;
|
2011-08-29 22:46:38 +08:00
|
|
|
udelay(1);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
} while (1);
|
|
|
|
|
|
|
|
dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
|
|
|
|
dwc->gadget_driver
|
|
|
|
? dwc->gadget_driver->function : "no-function",
|
|
|
|
is_on ? "connect" : "disconnect");
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = gadget_to_dwc(g);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
is_on = !!is_on;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
dwc3_gadget_run_stop(dwc, is_on);
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_start(struct usb_gadget *g,
|
|
|
|
struct usb_gadget_driver *driver)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = gadget_to_dwc(g);
|
|
|
|
struct dwc3_ep *dep;
|
|
|
|
unsigned long flags;
|
|
|
|
int ret = 0;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
|
|
|
if (dwc->gadget_driver) {
|
|
|
|
dev_err(dwc->dev, "%s is already bound to %s\n",
|
|
|
|
dwc->gadget.name,
|
|
|
|
dwc->gadget_driver->driver.name);
|
|
|
|
ret = -EBUSY;
|
|
|
|
goto err0;
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc->gadget_driver = driver;
|
|
|
|
dwc->gadget.dev.driver = &driver->driver;
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
|
|
|
|
reg &= ~(DWC3_DCFG_SPEED_MASK);
|
2012-03-23 18:20:31 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* WORKAROUND: DWC3 revision < 2.20a have an issue
|
|
|
|
* which would cause metastability state on Run/Stop
|
|
|
|
* bit if we try to force the IP to USB2-only mode.
|
|
|
|
*
|
|
|
|
* Because of that, we cannot configure the IP to any
|
|
|
|
* speed other than the SuperSpeed
|
|
|
|
*
|
|
|
|
* Refers to:
|
|
|
|
*
|
|
|
|
* STAR#9000525659: Clock Domain Crossing on DCTL in
|
|
|
|
* USB 2.0 Mode
|
|
|
|
*/
|
|
|
|
if (dwc->revision < DWC3_REVISION_220A)
|
|
|
|
reg |= DWC3_DCFG_SUPERSPEED;
|
|
|
|
else
|
|
|
|
reg |= dwc->maximum_speed;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
|
|
|
|
|
2011-09-30 15:58:42 +08:00
|
|
|
dwc->start_config_issued = false;
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* Start with SuperSpeed Default */
|
|
|
|
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
|
|
|
|
|
|
|
|
dep = dwc->eps[0];
|
2011-11-29 19:11:21 +08:00
|
|
|
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to enable %s\n", dep->name);
|
|
|
|
goto err0;
|
|
|
|
}
|
|
|
|
|
|
|
|
dep = dwc->eps[1];
|
2011-11-29 19:11:21 +08:00
|
|
|
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to enable %s\n", dep->name);
|
|
|
|
goto err1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* begin to receive SETUP packets */
|
2011-08-28 03:28:36 +08:00
|
|
|
dwc->ep0state = EP0_SETUP_PHASE;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_ep0_out_start(dwc);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err1:
|
|
|
|
__dwc3_gadget_ep_disable(dwc->eps[0]);
|
|
|
|
|
|
|
|
err0:
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_gadget_stop(struct usb_gadget *g,
|
|
|
|
struct usb_gadget_driver *driver)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = gadget_to_dwc(g);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
|
|
|
|
__dwc3_gadget_ep_disable(dwc->eps[0]);
|
|
|
|
__dwc3_gadget_ep_disable(dwc->eps[1]);
|
|
|
|
|
|
|
|
dwc->gadget_driver = NULL;
|
|
|
|
dwc->gadget.dev.driver = NULL;
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2012-04-27 18:10:52 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
static const struct usb_gadget_ops dwc3_gadget_ops = {
|
|
|
|
.get_frame = dwc3_gadget_get_frame,
|
|
|
|
.wakeup = dwc3_gadget_wakeup,
|
|
|
|
.set_selfpowered = dwc3_gadget_set_selfpowered,
|
|
|
|
.pullup = dwc3_gadget_pullup,
|
|
|
|
.udc_start = dwc3_gadget_start,
|
|
|
|
.udc_stop = dwc3_gadget_stop,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct dwc3_ep *dep;
|
|
|
|
u8 epnum;
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&dwc->gadget.ep_list);
|
|
|
|
|
|
|
|
for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
|
|
|
|
dep = kzalloc(sizeof(*dep), GFP_KERNEL);
|
|
|
|
if (!dep) {
|
|
|
|
dev_err(dwc->dev, "can't allocate endpoint %d\n",
|
|
|
|
epnum);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
dep->dwc = dwc;
|
|
|
|
dep->number = epnum;
|
|
|
|
dwc->eps[epnum] = dep;
|
|
|
|
|
|
|
|
snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
|
|
|
|
(epnum & 1) ? "in" : "out");
|
|
|
|
dep->endpoint.name = dep->name;
|
|
|
|
dep->direction = (epnum & 1);
|
|
|
|
|
|
|
|
if (epnum == 0 || epnum == 1) {
|
|
|
|
dep->endpoint.maxpacket = 512;
|
|
|
|
dep->endpoint.ops = &dwc3_gadget_ep0_ops;
|
|
|
|
if (!epnum)
|
|
|
|
dwc->gadget.ep0 = &dep->endpoint;
|
|
|
|
} else {
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
dep->endpoint.maxpacket = 1024;
|
2011-11-04 03:27:50 +08:00
|
|
|
dep->endpoint.max_streams = 15;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dep->endpoint.ops = &dwc3_gadget_ep_ops;
|
|
|
|
list_add_tail(&dep->endpoint.ep_list,
|
|
|
|
&dwc->gadget.ep_list);
|
|
|
|
|
|
|
|
ret = dwc3_alloc_trb_pool(dep);
|
2011-11-04 18:32:47 +08:00
|
|
|
if (ret)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
return ret;
|
|
|
|
}
|
2011-11-04 18:32:47 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
INIT_LIST_HEAD(&dep->request_list);
|
|
|
|
INIT_LIST_HEAD(&dep->req_queued);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct dwc3_ep *dep;
|
|
|
|
u8 epnum;
|
|
|
|
|
|
|
|
for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
|
|
|
|
dep = dwc->eps[epnum];
|
|
|
|
dwc3_free_trb_pool(dep);
|
|
|
|
|
|
|
|
if (epnum != 0 && epnum != 1)
|
|
|
|
list_del(&dep->endpoint.ep_list);
|
|
|
|
|
|
|
|
kfree(dep);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_gadget_release(struct device *dev)
|
|
|
|
{
|
|
|
|
dev_dbg(dev, "%s\n", __func__);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
|
|
|
|
const struct dwc3_event_depevt *event, int status)
|
|
|
|
{
|
|
|
|
struct dwc3_request *req;
|
2012-02-06 17:04:53 +08:00
|
|
|
struct dwc3_trb *trb;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
unsigned int count;
|
|
|
|
unsigned int s_pkt = 0;
|
|
|
|
|
|
|
|
do {
|
|
|
|
req = next_request(&dep->req_queued);
|
2011-11-03 17:32:20 +08:00
|
|
|
if (!req) {
|
|
|
|
WARN_ON_ONCE(1);
|
|
|
|
return 1;
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-02-06 17:04:53 +08:00
|
|
|
trb = req->trb;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-02-06 17:04:53 +08:00
|
|
|
if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
|
2011-08-20 01:59:12 +08:00
|
|
|
/*
|
|
|
|
* We continue despite the error. There is not much we
|
2012-02-16 10:56:56 +08:00
|
|
|
* can do. If we don't clean it up we loop forever. If
|
|
|
|
* we skip the TRB then it gets overwritten after a
|
|
|
|
* while since we use them in a ring buffer. A BUG()
|
|
|
|
* would help. Lets hope that if this occurs, someone
|
2011-08-20 01:59:12 +08:00
|
|
|
* fixes the root cause instead of looking away :)
|
|
|
|
*/
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
|
|
|
|
dep->name, req->trb);
|
2012-02-06 17:04:53 +08:00
|
|
|
count = trb->size & DWC3_TRB_SIZE_MASK;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
if (dep->direction) {
|
|
|
|
if (count) {
|
|
|
|
dev_err(dwc->dev, "incomplete IN transfer %s\n",
|
|
|
|
dep->name);
|
|
|
|
status = -ECONNRESET;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (count && (event->status & DEPEVT_STATUS_SHORT))
|
|
|
|
s_pkt = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We assume here we will always receive the entire data block
|
|
|
|
* which we should receive. Meaning, if we program RX to
|
|
|
|
* receive 4K but we receive only 2K, we assume that's all we
|
|
|
|
* should receive and we simply bounce the request back to the
|
|
|
|
* gadget driver for further processing.
|
|
|
|
*/
|
|
|
|
req->request.actual += req->request.length - count;
|
|
|
|
dwc3_gadget_giveback(dep, req, status);
|
|
|
|
if (s_pkt)
|
|
|
|
break;
|
2012-02-06 17:04:53 +08:00
|
|
|
if ((event->status & DEPEVT_STATUS_LST) &&
|
|
|
|
(trb->ctrl & DWC3_TRB_CTRL_LST))
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
break;
|
2012-02-06 17:04:53 +08:00
|
|
|
if ((event->status & DEPEVT_STATUS_IOC) &&
|
|
|
|
(trb->ctrl & DWC3_TRB_CTRL_IOC))
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
break;
|
|
|
|
} while (1);
|
|
|
|
|
2012-02-06 17:04:53 +08:00
|
|
|
if ((event->status & DEPEVT_STATUS_IOC) &&
|
|
|
|
(trb->ctrl & DWC3_TRB_CTRL_IOC))
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
return 0;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
|
|
|
|
struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
|
|
|
|
int start_new)
|
|
|
|
{
|
|
|
|
unsigned status = 0;
|
|
|
|
int clean_busy;
|
|
|
|
|
|
|
|
if (event->status & DEPEVT_STATUS_BUSERR)
|
|
|
|
status = -ECONNRESET;
|
|
|
|
|
2012-02-16 10:56:56 +08:00
|
|
|
clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
|
2012-02-25 09:32:18 +08:00
|
|
|
if (clean_busy)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dep->flags &= ~DWC3_EP_BUSY;
|
2011-10-14 18:00:30 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
|
|
|
|
* See dwc3_gadget_linksts_change_interrupt() for 1st half.
|
|
|
|
*/
|
|
|
|
if (dwc->revision < DWC3_REVISION_183A) {
|
|
|
|
u32 reg;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
|
|
|
|
struct dwc3_ep *dep = dwc->eps[i];
|
|
|
|
|
|
|
|
if (!(dep->flags & DWC3_EP_ENABLED))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!list_empty(&dep->req_queued))
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
reg |= dwc->u1u2;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
|
|
|
|
dwc->u1u2 = 0;
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
|
|
|
|
struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
|
|
|
|
{
|
2012-02-18 06:10:16 +08:00
|
|
|
u32 uf, mask;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
if (list_empty(&dep->request_list)) {
|
|
|
|
dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
|
|
|
|
dep->name);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-02-18 06:10:16 +08:00
|
|
|
mask = ~(dep->interval - 1);
|
|
|
|
uf = event->parameters & mask;
|
|
|
|
/* 4 micro frames in the future */
|
|
|
|
uf += dep->interval * 4;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
__dwc3_gadget_kick_transfer(dep, uf, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
|
|
|
|
const struct dwc3_event_depevt *event)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
struct dwc3_event_depevt mod_ev = *event;
|
|
|
|
|
|
|
|
/*
|
2012-02-16 10:56:56 +08:00
|
|
|
* We were asked to remove one request. It is possible that this
|
|
|
|
* request and a few others were started together and have the same
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* transfer index. Since we stopped the complete endpoint we don't
|
|
|
|
* know how many requests were already completed (and not yet)
|
|
|
|
* reported and how could be done (later). We purge them all until
|
|
|
|
* the end of the list.
|
|
|
|
*/
|
|
|
|
mod_ev.status = DEPEVT_STATUS_LST;
|
|
|
|
dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
|
|
|
|
dep->flags &= ~DWC3_EP_BUSY;
|
2012-02-16 10:56:56 +08:00
|
|
|
/* pending requests are ignored and are queued on XferNotReady */
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
|
|
|
|
const struct dwc3_event_depevt *event)
|
|
|
|
{
|
|
|
|
u32 param = event->parameters;
|
|
|
|
u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
|
|
|
|
|
|
|
|
switch (cmd_type) {
|
|
|
|
case DWC3_DEPCMD_ENDTRANSFER:
|
|
|
|
dwc3_process_ep_cmd_complete(dep, event);
|
|
|
|
break;
|
|
|
|
case DWC3_DEPCMD_STARTTRANSFER:
|
|
|
|
dep->res_trans_idx = param & 0x7f;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
|
|
|
|
__func__, cmd_type);
|
|
|
|
break;
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
|
|
|
|
const struct dwc3_event_depevt *event)
|
|
|
|
{
|
|
|
|
struct dwc3_ep *dep;
|
|
|
|
u8 epnum = event->endpoint_number;
|
|
|
|
|
|
|
|
dep = dwc->eps[epnum];
|
|
|
|
|
|
|
|
dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
|
|
|
|
dwc3_ep_event_string(event->endpoint_event));
|
|
|
|
|
|
|
|
if (epnum == 0 || epnum == 1) {
|
|
|
|
dwc3_ep0_interrupt(dwc, event);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (event->endpoint_event) {
|
|
|
|
case DWC3_DEPEVT_XFERCOMPLETE:
|
2012-02-25 09:32:18 +08:00
|
|
|
dep->res_trans_idx = 0;
|
|
|
|
|
2012-03-13 02:25:24 +08:00
|
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
|
|
|
|
dep->name);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
|
|
|
|
break;
|
|
|
|
case DWC3_DEPEVT_XFERINPROGRESS:
|
2012-03-13 02:25:24 +08:00
|
|
|
if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
|
|
|
|
dep->name);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
|
|
|
|
break;
|
|
|
|
case DWC3_DEPEVT_XFERNOTREADY:
|
2012-03-13 02:25:24 +08:00
|
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_gadget_start_isoc(dwc, dep, event);
|
|
|
|
} else {
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
dev_vdbg(dwc->dev, "%s: reason %s\n",
|
2012-01-18 23:06:03 +08:00
|
|
|
dep->name, event->status &
|
|
|
|
DEPEVT_STATUS_TRANSFER_ACTIVE
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
? "Transfer Active"
|
|
|
|
: "Transfer Not Active");
|
|
|
|
|
|
|
|
ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
|
|
|
|
if (!ret || ret == -EBUSY)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
|
|
|
|
dep->name);
|
|
|
|
}
|
|
|
|
|
2011-09-30 15:58:47 +08:00
|
|
|
break;
|
|
|
|
case DWC3_DEPEVT_STREAMEVT:
|
2012-03-13 02:25:24 +08:00
|
|
|
if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
|
2011-09-30 15:58:47 +08:00
|
|
|
dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
|
|
|
|
dep->name);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (event->status) {
|
|
|
|
case DEPEVT_STREAMEVT_FOUND:
|
|
|
|
dev_vdbg(dwc->dev, "Stream %d found and started\n",
|
|
|
|
event->parameters);
|
|
|
|
|
|
|
|
break;
|
|
|
|
case DEPEVT_STREAMEVT_NOTFOUND:
|
|
|
|
/* FALLTHROUGH */
|
|
|
|
default:
|
|
|
|
dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
break;
|
|
|
|
case DWC3_DEPEVT_RXTXFIFOEVT:
|
|
|
|
dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
|
|
|
|
break;
|
|
|
|
case DWC3_DEPEVT_EPCMDCMPLT:
|
|
|
|
dwc3_ep_cmd_compl(dep, event);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_disconnect_gadget(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
|
|
|
|
spin_unlock(&dwc->lock);
|
|
|
|
dwc->gadget_driver->disconnect(&dwc->gadget);
|
|
|
|
spin_lock(&dwc->lock);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
|
|
|
|
{
|
|
|
|
struct dwc3_ep *dep;
|
|
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
|
|
u32 cmd;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
dep = dwc->eps[epnum];
|
|
|
|
|
2011-08-29 19:56:37 +08:00
|
|
|
WARN_ON(!dep->res_trans_idx);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (dep->res_trans_idx) {
|
|
|
|
cmd = DWC3_DEPCMD_ENDTRANSFER;
|
|
|
|
cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
|
|
|
|
cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
|
|
|
|
memset(¶ms, 0, sizeof(params));
|
|
|
|
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
|
|
|
|
WARN_ON_ONCE(ret);
|
2011-08-22 23:42:18 +08:00
|
|
|
dep->res_trans_idx = 0;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_stop_active_transfers(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
u32 epnum;
|
|
|
|
|
|
|
|
for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
|
|
|
|
struct dwc3_ep *dep;
|
|
|
|
|
|
|
|
dep = dwc->eps[epnum];
|
|
|
|
if (!(dep->flags & DWC3_EP_ENABLED))
|
|
|
|
continue;
|
|
|
|
|
2011-08-29 19:56:37 +08:00
|
|
|
dwc3_remove_requests(dwc, dep);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
u32 epnum;
|
|
|
|
|
|
|
|
for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
|
|
|
|
struct dwc3_ep *dep;
|
|
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
dep = dwc->eps[epnum];
|
|
|
|
|
|
|
|
if (!(dep->flags & DWC3_EP_STALL))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
dep->flags &= ~DWC3_EP_STALL;
|
|
|
|
|
|
|
|
memset(¶ms, 0, sizeof(params));
|
|
|
|
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
|
|
|
|
DWC3_DEPCMD_CLEARSTALL, ¶ms);
|
|
|
|
WARN_ON_ONCE(ret);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
|
|
|
|
{
|
2012-05-24 15:30:01 +08:00
|
|
|
int reg;
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dev_vdbg(dwc->dev, "%s\n", __func__);
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
reg &= ~DWC3_DCTL_INITU1ENA;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
|
|
|
|
reg &= ~DWC3_DCTL_INITU2ENA;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
|
|
|
|
dwc3_stop_active_transfers(dwc);
|
|
|
|
dwc3_disconnect_gadget(dwc);
|
2011-09-30 15:58:42 +08:00
|
|
|
dwc->start_config_issued = false;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
dwc->gadget.speed = USB_SPEED_UNKNOWN;
|
2011-10-14 20:11:49 +08:00
|
|
|
dwc->setup_packet_pending = false;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
2012-04-27 17:54:05 +08:00
|
|
|
static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
|
|
|
|
|
2012-04-27 17:54:05 +08:00
|
|
|
if (suspend)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
reg |= DWC3_GUSB3PIPECTL_SUSPHY;
|
2012-04-27 17:54:05 +08:00
|
|
|
else
|
|
|
|
reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
|
|
|
|
}
|
|
|
|
|
2012-04-27 17:54:05 +08:00
|
|
|
static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
|
|
|
2012-04-27 17:54:05 +08:00
|
|
|
if (suspend)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
reg |= DWC3_GUSB2PHYCFG_SUSPHY;
|
2012-04-27 17:54:05 +08:00
|
|
|
else
|
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
dev_vdbg(dwc->dev, "%s\n", __func__);
|
|
|
|
|
2011-10-14 20:11:49 +08:00
|
|
|
/*
|
|
|
|
* WORKAROUND: DWC3 revisions <1.88a have an issue which
|
|
|
|
* would cause a missing Disconnect Event if there's a
|
|
|
|
* pending Setup Packet in the FIFO.
|
|
|
|
*
|
|
|
|
* There's no suggested workaround on the official Bug
|
|
|
|
* report, which states that "unless the driver/application
|
|
|
|
* is doing any special handling of a disconnect event,
|
|
|
|
* there is no functional issue".
|
|
|
|
*
|
|
|
|
* Unfortunately, it turns out that we _do_ some special
|
|
|
|
* handling of a disconnect event, namely complete all
|
|
|
|
* pending transfers, notify gadget driver of the
|
|
|
|
* disconnection, and so on.
|
|
|
|
*
|
|
|
|
* Our suggested workaround is to follow the Disconnect
|
|
|
|
* Event steps here, instead, based on a setup_packet_pending
|
|
|
|
* flag. Such flag gets set whenever we have a XferNotReady
|
|
|
|
* event on EP0 and gets cleared on XferComplete for the
|
|
|
|
* same endpoint.
|
|
|
|
*
|
|
|
|
* Refers to:
|
|
|
|
*
|
|
|
|
* STAR#9000466709: RTL: Device : Disconnect event not
|
|
|
|
* generated if setup packet pending in FIFO
|
|
|
|
*/
|
|
|
|
if (dwc->revision < DWC3_REVISION_188A) {
|
|
|
|
if (dwc->setup_packet_pending)
|
|
|
|
dwc3_gadget_disconnect_interrupt(dwc);
|
|
|
|
}
|
|
|
|
|
2011-12-20 21:37:21 +08:00
|
|
|
/* after reset -> Default State */
|
|
|
|
dwc->dev_state = DWC3_DEFAULT_STATE;
|
|
|
|
|
2012-04-27 18:10:52 +08:00
|
|
|
/* Recent versions support automatic phy suspend and don't need this */
|
|
|
|
if (dwc->revision < DWC3_REVISION_194A) {
|
|
|
|
/* Resume PHYs */
|
|
|
|
dwc3_gadget_usb2_phy_suspend(dwc, false);
|
|
|
|
dwc3_gadget_usb3_phy_suspend(dwc, false);
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
|
|
|
|
dwc3_disconnect_gadget(dwc);
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
reg &= ~DWC3_DCTL_TSTCTRL_MASK;
|
2011-09-13 23:54:39 +08:00
|
|
|
reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
2012-02-10 18:21:18 +08:00
|
|
|
dwc->test_mode = false;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
dwc3_stop_active_transfers(dwc);
|
|
|
|
dwc3_clear_stall_all_ep(dwc);
|
2011-09-30 15:58:42 +08:00
|
|
|
dwc->start_config_issued = false;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
/* Reset device address to zero */
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
|
|
|
|
reg &= ~(DWC3_DCFG_DEVADDR_MASK);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
u32 usb30_clock = DWC3_GCTL_CLK_BUS;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We change the clock only at SS but I dunno why I would want to do
|
|
|
|
* this. Maybe it becomes part of the power saving plan.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (speed != DWC3_DSTS_SUPERSPEED)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
|
|
|
|
* each time on Connect Done.
|
|
|
|
*/
|
|
|
|
if (!usb30_clock)
|
|
|
|
return;
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
|
|
|
reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
|
|
|
|
}
|
|
|
|
|
2012-04-27 17:54:05 +08:00
|
|
|
static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
|
|
|
switch (speed) {
|
|
|
|
case USB_SPEED_SUPER:
|
2012-04-27 17:54:05 +08:00
|
|
|
dwc3_gadget_usb2_phy_suspend(dwc, true);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
break;
|
|
|
|
case USB_SPEED_HIGH:
|
|
|
|
case USB_SPEED_FULL:
|
|
|
|
case USB_SPEED_LOW:
|
2012-04-27 17:54:05 +08:00
|
|
|
dwc3_gadget_usb3_phy_suspend(dwc, true);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
|
|
struct dwc3_ep *dep;
|
|
|
|
int ret;
|
|
|
|
u32 reg;
|
|
|
|
u8 speed;
|
|
|
|
|
|
|
|
dev_vdbg(dwc->dev, "%s\n", __func__);
|
|
|
|
|
|
|
|
memset(¶ms, 0x00, sizeof(params));
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
|
|
speed = reg & DWC3_DSTS_CONNECTSPD;
|
|
|
|
dwc->speed = speed;
|
|
|
|
|
|
|
|
dwc3_update_ram_clk_sel(dwc, speed);
|
|
|
|
|
|
|
|
switch (speed) {
|
|
|
|
case DWC3_DCFG_SUPERSPEED:
|
2011-10-14 19:51:38 +08:00
|
|
|
/*
|
|
|
|
* WORKAROUND: DWC3 revisions <1.90a have an issue which
|
|
|
|
* would cause a missing USB3 Reset event.
|
|
|
|
*
|
|
|
|
* In such situations, we should force a USB3 Reset
|
|
|
|
* event by calling our dwc3_gadget_reset_interrupt()
|
|
|
|
* routine.
|
|
|
|
*
|
|
|
|
* Refers to:
|
|
|
|
*
|
|
|
|
* STAR#9000483510: RTL: SS : USB3 reset event may
|
|
|
|
* not be generated always when the link enters poll
|
|
|
|
*/
|
|
|
|
if (dwc->revision < DWC3_REVISION_190A)
|
|
|
|
dwc3_gadget_reset_interrupt(dwc);
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
|
|
|
|
dwc->gadget.ep0->maxpacket = 512;
|
|
|
|
dwc->gadget.speed = USB_SPEED_SUPER;
|
|
|
|
break;
|
|
|
|
case DWC3_DCFG_HIGHSPEED:
|
|
|
|
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
|
|
|
|
dwc->gadget.ep0->maxpacket = 64;
|
|
|
|
dwc->gadget.speed = USB_SPEED_HIGH;
|
|
|
|
break;
|
|
|
|
case DWC3_DCFG_FULLSPEED2:
|
|
|
|
case DWC3_DCFG_FULLSPEED1:
|
|
|
|
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
|
|
|
|
dwc->gadget.ep0->maxpacket = 64;
|
|
|
|
dwc->gadget.speed = USB_SPEED_FULL;
|
|
|
|
break;
|
|
|
|
case DWC3_DCFG_LOWSPEED:
|
|
|
|
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
|
|
|
|
dwc->gadget.ep0->maxpacket = 8;
|
|
|
|
dwc->gadget.speed = USB_SPEED_LOW;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2012-04-27 18:10:52 +08:00
|
|
|
/* Recent versions support automatic phy suspend and don't need this */
|
|
|
|
if (dwc->revision < DWC3_REVISION_194A) {
|
|
|
|
/* Suspend unneeded PHY */
|
|
|
|
dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
dep = dwc->eps[0];
|
2011-11-29 19:11:21 +08:00
|
|
|
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to enable %s\n", dep->name);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
dep = dwc->eps[1];
|
2011-11-29 19:11:21 +08:00
|
|
|
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to enable %s\n", dep->name);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure PHY via GUSB3PIPECTLn if required.
|
|
|
|
*
|
|
|
|
* Update GTXFIFOSIZn
|
|
|
|
*
|
|
|
|
* In both cases reset values should be sufficient.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
dev_vdbg(dwc->dev, "%s\n", __func__);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO take core out of low power mode when that's
|
|
|
|
* implemented.
|
|
|
|
*/
|
|
|
|
|
|
|
|
dwc->gadget_driver->resume(&dwc->gadget);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
|
|
|
|
unsigned int evtinfo)
|
|
|
|
{
|
2011-10-14 18:00:30 +08:00
|
|
|
enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
|
|
|
|
* on the link partner, the USB session might do multiple entry/exit
|
|
|
|
* of low power states before a transfer takes place.
|
|
|
|
*
|
|
|
|
* Due to this problem, we might experience lower throughput. The
|
|
|
|
* suggested workaround is to disable DCTL[12:9] bits if we're
|
|
|
|
* transitioning from U1/U2 to U0 and enable those bits again
|
|
|
|
* after a transfer completes and there are no pending transfers
|
|
|
|
* on any of the enabled endpoints.
|
|
|
|
*
|
|
|
|
* This is the first half of that workaround.
|
|
|
|
*
|
|
|
|
* Refers to:
|
|
|
|
*
|
|
|
|
* STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
|
|
|
|
* core send LGO_Ux entering U0
|
|
|
|
*/
|
|
|
|
if (dwc->revision < DWC3_REVISION_183A) {
|
|
|
|
if (next == DWC3_LINK_STATE_U0) {
|
|
|
|
u32 u1u2;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
switch (dwc->link_state) {
|
|
|
|
case DWC3_LINK_STATE_U1:
|
|
|
|
case DWC3_LINK_STATE_U2:
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
u1u2 = reg & (DWC3_DCTL_INITU2ENA
|
|
|
|
| DWC3_DCTL_ACCEPTU2ENA
|
|
|
|
| DWC3_DCTL_INITU1ENA
|
|
|
|
| DWC3_DCTL_ACCEPTU1ENA);
|
|
|
|
|
|
|
|
if (!dwc->u1u2)
|
|
|
|
dwc->u1u2 = reg & u1u2;
|
|
|
|
|
|
|
|
reg &= ~u1u2;
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc->link_state = next;
|
2011-09-09 02:18:47 +08:00
|
|
|
|
|
|
|
dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_gadget_interrupt(struct dwc3 *dwc,
|
|
|
|
const struct dwc3_event_devt *event)
|
|
|
|
{
|
|
|
|
switch (event->type) {
|
|
|
|
case DWC3_DEVICE_EVENT_DISCONNECT:
|
|
|
|
dwc3_gadget_disconnect_interrupt(dwc);
|
|
|
|
break;
|
|
|
|
case DWC3_DEVICE_EVENT_RESET:
|
|
|
|
dwc3_gadget_reset_interrupt(dwc);
|
|
|
|
break;
|
|
|
|
case DWC3_DEVICE_EVENT_CONNECT_DONE:
|
|
|
|
dwc3_gadget_conndone_interrupt(dwc);
|
|
|
|
break;
|
|
|
|
case DWC3_DEVICE_EVENT_WAKEUP:
|
|
|
|
dwc3_gadget_wakeup_interrupt(dwc);
|
|
|
|
break;
|
|
|
|
case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
|
|
|
|
dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
|
|
|
|
break;
|
|
|
|
case DWC3_DEVICE_EVENT_EOPF:
|
|
|
|
dev_vdbg(dwc->dev, "End of Periodic Frame\n");
|
|
|
|
break;
|
|
|
|
case DWC3_DEVICE_EVENT_SOF:
|
|
|
|
dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
|
|
|
|
break;
|
|
|
|
case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
|
|
|
|
dev_vdbg(dwc->dev, "Erratic Error\n");
|
|
|
|
break;
|
|
|
|
case DWC3_DEVICE_EVENT_CMD_CMPL:
|
|
|
|
dev_vdbg(dwc->dev, "Command Complete\n");
|
|
|
|
break;
|
|
|
|
case DWC3_DEVICE_EVENT_OVERFLOW:
|
|
|
|
dev_vdbg(dwc->dev, "Overflow\n");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_process_event_entry(struct dwc3 *dwc,
|
|
|
|
const union dwc3_event *event)
|
|
|
|
{
|
|
|
|
/* Endpoint IRQ, handle it and return early */
|
|
|
|
if (event->type.is_devspec == 0) {
|
|
|
|
/* depevt */
|
|
|
|
return dwc3_endpoint_interrupt(dwc, &event->depevt);
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (event->type.type) {
|
|
|
|
case DWC3_EVENT_TYPE_DEV:
|
|
|
|
dwc3_gadget_interrupt(dwc, &event->devt);
|
|
|
|
break;
|
|
|
|
/* REVISIT what to do with Carkit and I2C events ? */
|
|
|
|
default:
|
|
|
|
dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
|
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
int left;
|
|
|
|
u32 count;
|
|
|
|
|
|
|
|
count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
|
|
|
|
count &= DWC3_GEVNTCOUNT_MASK;
|
|
|
|
if (!count)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
evt = dwc->ev_buffs[buf];
|
|
|
|
left = count;
|
|
|
|
|
|
|
|
while (left > 0) {
|
|
|
|
union dwc3_event event;
|
|
|
|
|
2012-02-06 19:40:17 +08:00
|
|
|
event.raw = *(u32 *) (evt->buf + evt->lpos);
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_process_event_entry(dwc, &event);
|
|
|
|
/*
|
|
|
|
* XXX we wrap around correctly to the next entry as almost all
|
|
|
|
* entries are 4 bytes in size. There is one entry which has 12
|
|
|
|
* bytes which is a regular entry followed by 8 bytes data. ATM
|
|
|
|
* I don't know how things are organized if were get next to the
|
|
|
|
* a boundary so I worry about that once we try to handle that.
|
|
|
|
*/
|
|
|
|
evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
|
|
|
|
left -= 4;
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = _dwc;
|
|
|
|
int i;
|
|
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
|
|
|
|
spin_lock(&dwc->lock);
|
|
|
|
|
2011-10-12 15:31:04 +08:00
|
|
|
for (i = 0; i < dwc->num_event_buffers; i++) {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
irqreturn_t status;
|
|
|
|
|
|
|
|
status = dwc3_process_event_buf(dwc, i);
|
|
|
|
if (status == IRQ_HANDLED)
|
|
|
|
ret = status;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock(&dwc->lock);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dwc3_gadget_init - Initializes gadget related registers
|
2012-02-16 10:56:56 +08:00
|
|
|
* @dwc: pointer to our controller context structure
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*
|
|
|
|
* Returns 0 on success otherwise negative errno.
|
|
|
|
*/
|
|
|
|
int __devinit dwc3_gadget_init(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
int ret;
|
|
|
|
int irq;
|
|
|
|
|
|
|
|
dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
|
|
|
|
&dwc->ctrl_req_addr, GFP_KERNEL);
|
|
|
|
if (!dwc->ctrl_req) {
|
|
|
|
dev_err(dwc->dev, "failed to allocate ctrl request\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err0;
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
|
|
|
|
&dwc->ep0_trb_addr, GFP_KERNEL);
|
|
|
|
if (!dwc->ep0_trb) {
|
|
|
|
dev_err(dwc->dev, "failed to allocate ep0 trb\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err1;
|
|
|
|
}
|
|
|
|
|
2012-05-04 17:58:14 +08:00
|
|
|
dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (!dwc->setup_buf) {
|
|
|
|
dev_err(dwc->dev, "failed to allocate setup buffer\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err2;
|
|
|
|
}
|
|
|
|
|
2011-08-28 03:07:53 +08:00
|
|
|
dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
|
2012-05-04 17:58:14 +08:00
|
|
|
DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
|
|
|
|
GFP_KERNEL);
|
2011-08-28 03:07:53 +08:00
|
|
|
if (!dwc->ep0_bounce) {
|
|
|
|
dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err3;
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dev_set_name(&dwc->gadget.dev, "gadget");
|
|
|
|
|
|
|
|
dwc->gadget.ops = &dwc3_gadget_ops;
|
2011-11-20 01:27:37 +08:00
|
|
|
dwc->gadget.max_speed = USB_SPEED_SUPER;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc->gadget.speed = USB_SPEED_UNKNOWN;
|
|
|
|
dwc->gadget.dev.parent = dwc->dev;
|
2011-11-28 18:46:59 +08:00
|
|
|
dwc->gadget.sg_supported = true;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
|
|
|
|
|
|
|
|
dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
|
|
|
|
dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
|
|
|
|
dwc->gadget.dev.release = dwc3_gadget_release;
|
|
|
|
dwc->gadget.name = "dwc3-gadget";
|
|
|
|
|
|
|
|
/*
|
|
|
|
* REVISIT: Here we should clear all pending IRQs to be
|
|
|
|
* sure we're starting from a well known location.
|
|
|
|
*/
|
|
|
|
|
|
|
|
ret = dwc3_gadget_init_endpoints(dwc);
|
|
|
|
if (ret)
|
2011-08-28 03:07:53 +08:00
|
|
|
goto err4;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
irq = platform_get_irq(to_platform_device(dwc->dev), 0);
|
|
|
|
|
|
|
|
ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
|
|
|
|
"dwc3", dwc);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
|
|
|
|
irq, ret);
|
2011-08-28 03:07:53 +08:00
|
|
|
goto err5;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
2011-09-13 23:54:39 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
|
|
|
|
reg |= DWC3_DCFG_LPM_CAP;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
reg |= DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* Enable all but Start and End of Frame IRQs */
|
|
|
|
reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
|
|
|
|
DWC3_DEVTEN_EVNTOVERFLOWEN |
|
|
|
|
DWC3_DEVTEN_CMDCMPLTEN |
|
|
|
|
DWC3_DEVTEN_ERRTICERREN |
|
|
|
|
DWC3_DEVTEN_WKUPEVTEN |
|
|
|
|
DWC3_DEVTEN_ULSTCNGEN |
|
|
|
|
DWC3_DEVTEN_CONNECTDONEEN |
|
|
|
|
DWC3_DEVTEN_USBRSTEN |
|
|
|
|
DWC3_DEVTEN_DISCONNEVTEN);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
|
|
|
|
|
2012-04-27 18:10:52 +08:00
|
|
|
/* Enable USB2 LPM and automatic phy suspend only on recent versions */
|
|
|
|
if (dwc->revision >= DWC3_REVISION_194A) {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
|
|
|
|
reg |= DWC3_DCFG_LPM_CAP;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
|
|
|
|
|
|
|
|
/* TODO: This should be configurable */
|
|
|
|
reg |= DWC3_DCTL_HIRD_THRES(31);
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
|
|
|
|
dwc3_gadget_usb2_phy_suspend(dwc, true);
|
|
|
|
dwc3_gadget_usb3_phy_suspend(dwc, true);
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
ret = device_register(&dwc->gadget.dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to register gadget device\n");
|
|
|
|
put_device(&dwc->gadget.dev);
|
2011-08-28 03:07:53 +08:00
|
|
|
goto err6;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to register udc\n");
|
2011-08-28 03:07:53 +08:00
|
|
|
goto err7;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2011-08-28 03:07:53 +08:00
|
|
|
err7:
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
device_unregister(&dwc->gadget.dev);
|
|
|
|
|
2011-08-28 03:07:53 +08:00
|
|
|
err6:
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
|
|
|
|
free_irq(irq, dwc);
|
|
|
|
|
2011-08-28 03:07:53 +08:00
|
|
|
err5:
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_gadget_free_endpoints(dwc);
|
|
|
|
|
2011-08-28 03:07:53 +08:00
|
|
|
err4:
|
2012-05-04 17:58:14 +08:00
|
|
|
dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
|
|
|
|
dwc->ep0_bounce, dwc->ep0_bounce_addr);
|
2011-08-28 03:07:53 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
err3:
|
2011-12-19 17:32:34 +08:00
|
|
|
kfree(dwc->setup_buf);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
err2:
|
|
|
|
dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
|
|
|
|
dwc->ep0_trb, dwc->ep0_trb_addr);
|
|
|
|
|
|
|
|
err1:
|
|
|
|
dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
|
|
|
|
dwc->ctrl_req, dwc->ctrl_req_addr);
|
|
|
|
|
|
|
|
err0:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dwc3_gadget_exit(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
int irq;
|
|
|
|
|
|
|
|
usb_del_gadget_udc(&dwc->gadget);
|
|
|
|
irq = platform_get_irq(to_platform_device(dwc->dev), 0);
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
|
|
|
|
free_irq(irq, dwc);
|
|
|
|
|
|
|
|
dwc3_gadget_free_endpoints(dwc);
|
|
|
|
|
2012-05-04 17:58:14 +08:00
|
|
|
dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
|
|
|
|
dwc->ep0_bounce, dwc->ep0_bounce_addr);
|
2011-08-28 03:07:53 +08:00
|
|
|
|
2011-12-19 17:32:34 +08:00
|
|
|
kfree(dwc->setup_buf);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
|
|
|
|
dwc->ep0_trb, dwc->ep0_trb_addr);
|
|
|
|
|
|
|
|
dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
|
|
|
|
dwc->ctrl_req, dwc->ctrl_req_addr);
|
|
|
|
|
|
|
|
device_unregister(&dwc->gadget.dev);
|
|
|
|
}
|