2019-05-19 20:07:45 +08:00
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# SPDX-License-Identifier: GPL-2.0-only
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2012-04-27 20:24:05 +08:00
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#
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# Memory devices
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#
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menuconfig MEMORY
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bool "Memory Controller drivers"
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2020-07-24 15:40:37 +08:00
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help
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This option allows to enable specific memory controller drivers,
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useful mostly on embedded systems. These could be controllers
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for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
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vary from memory tuning and frequency scaling to enabling
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access to attached peripherals through memory bus.
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2012-04-27 20:24:05 +08:00
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if MEMORY
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2019-06-03 16:12:32 +08:00
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config DDR
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bool
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help
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Data from JEDEC specs for DDR SDRAM memories,
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particularly the AC timing parameters and addressing
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information. This data is useful for drivers handling
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DDR SDRAM controllers.
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2015-07-14 05:20:11 +08:00
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config ARM_PL172_MPMC
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tristate "ARM PL172 MPMC driver"
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depends on ARM_AMBA && OF
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help
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This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
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If you have an embedded system with an AMBA bus and a PL172
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controller, say Y or M here.
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2014-07-09 00:21:12 +08:00
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config ATMEL_SDRAMC
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bool "Atmel (Multi-port DDR-)SDRAM Controller"
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2020-07-24 15:40:15 +08:00
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default y if ARCH_AT91
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depends on ARCH_AT91 || COMPILE_TEST
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depends on OF
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2014-07-09 00:21:12 +08:00
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help
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This driver is for Atmel SDRAM Controller or Atmel Multi-port
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DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
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Starting with the at91sam9g45, this controller supports SDR, DDR and
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LP-DDR memories.
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2016-05-23 15:44:54 +08:00
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config ATMEL_EBI
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bool "Atmel EBI driver"
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2020-07-24 15:40:15 +08:00
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default y if ARCH_AT91
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depends on ARCH_AT91 || COMPILE_TEST
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depends on OF
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2016-05-23 15:44:54 +08:00
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select MFD_SYSCON
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2017-03-16 16:30:29 +08:00
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select MFD_ATMEL_SMC
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2016-05-23 15:44:54 +08:00
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help
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Driver for Atmel EBI controller.
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Used to configure the EBI (external bus interface) when the device-
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tree is used. This bus supports NANDs, external ethernet controller,
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SRAMs, ATA devices, etc.
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2020-07-25 01:40:16 +08:00
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config BRCMSTB_DPFE
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2021-09-24 11:14:59 +08:00
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tristate "Broadcom STB DPFE driver"
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default ARCH_BRCMSTB
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2020-07-25 01:40:16 +08:00
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depends on ARCH_BRCMSTB || COMPILE_TEST
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help
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This driver provides access to the DPFE interface of Broadcom
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STB SoCs. The firmware running on the DCPU inside the DDR PHY can
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provide current information about the system's RAM, for instance
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the DRAM refresh rate. This can be used as an indirect indicator
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for the DRAM's temperature. Slower refresh rate means cooler RAM,
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higher refresh rate means hotter RAM.
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2020-05-26 20:59:28 +08:00
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config BT1_L2_CTL
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bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
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depends on MIPS_BAIKAL_T1 || COMPILE_TEST
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select MFD_SYSCON
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help
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Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
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resides Coherency Manager v2 with embedded 1MB L2-cache. It's
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possible to tune the L2 cache performance up by setting the data,
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tags and way-select latencies of RAM access. This driver provides a
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dt properties-based and sysfs interface for it.
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2014-02-25 01:26:11 +08:00
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config TI_AEMIF
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tristate "Texas Instruments AEMIF driver"
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2020-07-24 15:40:15 +08:00
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depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST
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depends on OF
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2014-02-25 01:26:11 +08:00
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help
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This driver is for the AEMIF module available in Texas Instruments
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SoCs. AEMIF stands for Asynchronous External Memory Interface and
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is intended to provide a glue-less interface to a variety of
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asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
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of 256M bytes of any of these memories can be accessed at a given
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time via four chip selects with 64M byte access per chip select.
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2012-04-27 20:24:05 +08:00
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config TI_EMIF
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tristate "Texas Instruments EMIF driver"
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2020-07-24 15:40:15 +08:00
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depends on ARCH_OMAP2PLUS || COMPILE_TEST
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2012-04-27 20:24:05 +08:00
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select DDR
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help
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This driver is for the EMIF module available in Texas Instruments
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SoCs. EMIF is an SDRAM controller that, based on its revision,
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supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
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This driver takes care of only LPDDR2 memories presently. The
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functions of the driver includes re-configuring AC timing
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parameters and other settings during frequency, voltage and
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temperature changes
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2014-11-21 01:13:42 +08:00
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config OMAP_GPMC
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2022-04-26 16:26:11 +08:00
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tristate "Texas Instruments OMAP SoC GPMC driver"
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2020-09-11 22:32:51 +08:00
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depends on OF_ADDRESS
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2022-05-10 17:29:13 +08:00
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depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
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2016-03-07 18:18:43 +08:00
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select GPIOLIB
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2014-11-21 01:13:42 +08:00
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help
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This driver is for the General Purpose Memory Controller (GPMC)
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present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
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interfacing to a variety of asynchronous as well as synchronous
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memory drives like NOR, NAND, OneNAND, SRAM.
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2015-06-02 09:22:10 +08:00
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config OMAP_GPMC_DEBUG
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2015-10-13 07:19:54 +08:00
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bool "Enable GPMC debug output and skip reset of GPMC during init"
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2015-06-02 09:22:10 +08:00
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depends on OMAP_GPMC
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help
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Enables verbose debugging mostly to decode the bootloader provided
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2015-10-13 07:19:54 +08:00
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timings. To preserve the bootloader provided timings, the reset
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of GPMC is skipped during init. Enable this during development to
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configure devices connected to the GPMC bus.
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NOTE: In addition to matching the register setup with the bootloader
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you also need to match the GPMC FCLK frequency used by the
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bootloader or else the GPMC timings won't be identical with the
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bootloader timings.
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2015-06-02 09:22:10 +08:00
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memory: ti-emif-sram: introduce relocatable suspend/resume handlers
Certain SoCs like Texas Instruments AM335x and AM437x require parts
of the EMIF PM code to run late in the suspend sequence from SRAM,
such as saving and restoring the EMIF context and placing the memory
into self-refresh.
One requirement for these SoCs to suspend and enter its lowest power
mode, called DeepSleep0, is that the PER power domain must be shut off.
Because the EMIF (DDR Controller) resides within this power domain, it
will lose context during a suspend operation, so we must save it so we
can restore once we resume. However, we cannot execute this code from
external memory, as it is not available at this point, so the code must
be executed late in the suspend path from SRAM.
This patch introduces a ti-emif-sram driver that includes several
functions written in ARM ASM that are relocatable so the PM SRAM
code can use them. It also allocates a region of writable SRAM to
be used by the code running in the executable region of SRAM to save
and restore the EMIF context. It can export a table containing the
absolute addresses of the available PM functions so that other SRAM
code can branch to them. This code is required for suspend/resume on
AM335x and AM437x to work.
In addition to this, to be able to share data structures between C and
the ti-emif-sram-pm assembly code, we can automatically generate all of
the C struct member offsets and sizes as macros by processing
emif-asm-offsets.c into assembly code and then extracting the relevant
data as is done for the generated platform asm-offsets.h files.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2015-06-18 03:52:10 +08:00
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config TI_EMIF_SRAM
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tristate "Texas Instruments EMIF SRAM driver"
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2020-12-04 07:08:14 +08:00
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depends on SOC_AM33XX || SOC_AM43XX || (ARM && CPU_V7 && COMPILE_TEST)
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2020-07-24 15:40:15 +08:00
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depends on SRAM
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memory: ti-emif-sram: introduce relocatable suspend/resume handlers
Certain SoCs like Texas Instruments AM335x and AM437x require parts
of the EMIF PM code to run late in the suspend sequence from SRAM,
such as saving and restoring the EMIF context and placing the memory
into self-refresh.
One requirement for these SoCs to suspend and enter its lowest power
mode, called DeepSleep0, is that the PER power domain must be shut off.
Because the EMIF (DDR Controller) resides within this power domain, it
will lose context during a suspend operation, so we must save it so we
can restore once we resume. However, we cannot execute this code from
external memory, as it is not available at this point, so the code must
be executed late in the suspend path from SRAM.
This patch introduces a ti-emif-sram driver that includes several
functions written in ARM ASM that are relocatable so the PM SRAM
code can use them. It also allocates a region of writable SRAM to
be used by the code running in the executable region of SRAM to save
and restore the EMIF context. It can export a table containing the
absolute addresses of the available PM functions so that other SRAM
code can branch to them. This code is required for suspend/resume on
AM335x and AM437x to work.
In addition to this, to be able to share data structures between C and
the ti-emif-sram-pm assembly code, we can automatically generate all of
the C struct member offsets and sizes as macros by processing
emif-asm-offsets.c into assembly code and then extracting the relevant
data as is done for the generated platform asm-offsets.h files.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2015-06-18 03:52:10 +08:00
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help
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This driver is for the EMIF module available on Texas Instruments
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AM33XX and AM43XX SoCs and is required for PM. Certain parts of
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the EMIF PM code must run from on-chip SRAM late in the suspend
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sequence so this driver provides several relocatable PM functions
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for the SoC PM code to use.
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2021-01-07 12:37:14 +08:00
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config FPGA_DFL_EMIF
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tristate "FPGA DFL EMIF Driver"
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depends on FPGA_DFL && HAS_IOMEM
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help
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This driver is for the EMIF private feature implemented under
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FPGA Device Feature List (DFL) framework. It is used to expose
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memory interface status information as well as memory clearing
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control.
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2013-04-24 03:21:26 +08:00
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config MVEBU_DEVBUS
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bool "Marvell EBU Device Bus Controller"
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2020-07-24 15:40:15 +08:00
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default y if PLAT_ORION
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depends on PLAT_ORION || COMPILE_TEST
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depends on OF
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2013-04-24 03:21:26 +08:00
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help
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This driver is for the Device Bus controller available in some
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Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
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Armada 370 and Armada XP. This controller allows to handle flash
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devices such as NOR, NAND, SRAM, and FPGA.
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2014-07-03 07:52:11 +08:00
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config FSL_CORENET_CF
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tristate "Freescale CoreNet Error Reporting"
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2020-07-24 15:40:15 +08:00
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depends on FSL_SOC_BOOKE || COMPILE_TEST
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2014-07-03 07:52:11 +08:00
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help
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Say Y for reporting of errors from the Freescale CoreNet
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Coherency Fabric. Errors reported include accesses to
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physical addresses that mapped by no local access window
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(LAW) or an invalid LAW, as well as bad cache state that
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represents a coherency violation.
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2014-02-20 06:46:40 +08:00
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config FSL_IFC
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2020-07-24 15:40:15 +08:00
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bool "Freescale IFC driver" if COMPILE_TEST
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2018-07-10 04:09:37 +08:00
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depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST
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depends on HAS_IOMEM
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2014-02-20 06:46:40 +08:00
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2015-03-09 22:29:04 +08:00
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config JZ4780_NEMC
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bool "Ingenic JZ4780 SoC NEMC driver"
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2019-06-04 22:30:16 +08:00
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depends on MIPS || COMPILE_TEST
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2018-07-25 17:19:28 +08:00
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depends on HAS_IOMEM && OF
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2015-03-09 22:29:04 +08:00
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help
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This driver is for the NAND/External Memory Controller (NEMC) in
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the Ingenic JZ4780. This controller is used to handle external
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memory devices such as NAND and SRAM.
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2016-02-23 01:20:49 +08:00
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config MTK_SMI
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2021-01-26 14:00:55 +08:00
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tristate "MediaTek SoC Memory Controller driver" if COMPILE_TEST
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2016-02-23 01:20:49 +08:00
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depends on ARCH_MEDIATEK || COMPILE_TEST
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help
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This driver is for the Memory Controller module in MediaTek SoCs,
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mainly help enable/disable iommu and control the power domain and
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clocks for each local arbiter.
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2016-10-31 22:45:34 +08:00
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config DA8XX_DDRCTL
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bool "Texas Instruments da8xx DDR2/mDDR driver"
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2020-07-24 15:40:15 +08:00
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depends on ARCH_DAVINCI_DA8XX || COMPILE_TEST
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2016-10-31 22:45:34 +08:00
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help
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This driver is for the DDR2/mDDR Memory Controller present on
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Texas Instruments da8xx SoCs. It's used to tweak various memory
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controller configuration options.
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2018-12-06 20:47:34 +08:00
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config PL353_SMC
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tristate "ARM PL35X Static Memory Controller(SMC) driver"
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2020-07-24 15:40:15 +08:00
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default y if ARM
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2020-10-30 03:33:57 +08:00
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depends on ARM || COMPILE_TEST
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depends on ARM_AMBA
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2018-12-06 20:47:34 +08:00
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help
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This driver is for the ARM PL351/PL353 Static Memory
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Controller(SMC) module.
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2020-06-17 04:03:48 +08:00
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config RENESAS_RPCIF
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tristate "Renesas RPC-IF driver"
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2020-07-24 15:40:15 +08:00
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depends on ARCH_RENESAS || COMPILE_TEST
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2020-06-17 04:03:48 +08:00
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select REGMAP_MMIO
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2021-10-05 23:29:22 +08:00
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select RESET_CONTROLLER
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2020-06-17 04:03:48 +08:00
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help
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2021-01-02 19:54:10 +08:00
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This supports Renesas R-Car Gen3 or RZ/G2 RPC-IF which provides
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either SPI host or HyperFlash. You'll have to select individual
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components under the corresponding menu.
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2020-06-17 04:03:48 +08:00
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2020-06-12 23:22:40 +08:00
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config STM32_FMC2_EBI
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tristate "Support for FMC2 External Bus Interface on STM32MP SoCs"
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depends on MACH_STM32MP157 || COMPILE_TEST
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select MFD_SYSCON
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help
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Select this option to enable the STM32 FMC2 External Bus Interface
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controller. This driver configures the transactions with external
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devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
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SOCs containing the FMC2 External Bus Interface.
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2016-04-11 15:42:24 +08:00
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source "drivers/memory/samsung/Kconfig"
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2014-04-16 15:24:44 +08:00
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source "drivers/memory/tegra/Kconfig"
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2012-04-27 20:24:05 +08:00
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endif
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