2008-03-18 17:24:28 +08:00
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/*
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2009-12-09 07:18:47 +08:00
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* OMAP3 clock function prototypes and macros
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2008-03-18 17:24:28 +08:00
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*
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2009-12-09 07:18:47 +08:00
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* Copyright (C) 2007-2009 Texas Instruments, Inc.
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* Copyright (C) 2007-2009 Nokia Corporation
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2008-03-18 17:24:28 +08:00
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*/
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2009-12-09 07:18:47 +08:00
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
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2008-03-18 17:24:28 +08:00
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2009-12-09 07:18:47 +08:00
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int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
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int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
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void omap3_clk_lock_dpll5(void);
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[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 21:29:22 +08:00
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2009-12-09 07:18:47 +08:00
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extern struct clk *sdrc_ick_p;
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extern struct clk *arm_fck_p;
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2008-03-18 17:24:28 +08:00
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2009-12-09 07:18:47 +08:00
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/* OMAP34xx-specific clkops */
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extern const struct clkops clkops_omap3430es2_ssi_wait;
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extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
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extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
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extern const struct clkops clkops_noncore_dpll_ops;
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2008-03-18 17:24:28 +08:00
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#endif
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