2019-05-27 14:55:01 +08:00
|
|
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
/*
|
|
|
|
|
* net/dsa/slave.c - Slave device handling
|
dsa: add switch chip cascading support
The initial version of the DSA driver only supported a single switch
chip per network interface, while DSA-capable switch chips can be
interconnected to form a tree of switch chips. This patch adds support
for multiple switch chips on a network interface.
An example topology for a 16-port device with an embedded CPU is as
follows:
+-----+ +--------+ +--------+
| |eth0 10| switch |9 10| switch |
| CPU +----------+ +-------+ |
| | | chip 0 | | chip 1 |
+-----+ +---++---+ +---++---+
|| ||
|| ||
||1000baseT ||1000baseT
||ports 1-8 ||ports 9-16
This requires a couple of interdependent changes in the DSA layer:
- The dsa platform driver data needs to be extended: there is still
only one netdevice per DSA driver instance (eth0 in the example
above), but each of the switch chips in the tree needs its own
mii_bus device pointer, MII management bus address, and port name
array. (include/net/dsa.h) The existing in-tree dsa users need
some small changes to deal with this. (arch/arm)
- The DSA and Ethertype DSA tagging modules need to be extended to
use the DSA device ID field on receive and demultiplex the packet
accordingly, and fill in the DSA device ID field on transmit
according to which switch chip the packet is heading to.
(net/dsa/tag_{dsa,edsa}.c)
- The concept of "CPU port", which is the switch chip port that the
CPU is connected to (port 10 on switch chip 0 in the example), needs
to be extended with the concept of "upstream port", which is the
port on the switch chip that will bring us one hop closer to the CPU
(port 10 for both switch chips in the example above).
- The dsa platform data needs to specify which ports on which switch
chips are links to other switch chips, so that we can enable DSA
tagging mode on them. (For inter-switch links, we always use
non-EtherType DSA tagging, since it has lower overhead. The CPU
link uses dsa or edsa tagging depending on what the 'root' switch
chip supports.) This is done by specifying "dsa" for the given
port in the port array.
- The dsa platform data needs to be extended with information on via
which port to reach any given switch chip from any given switch chip.
This info is specified via the per-switch chip data struct ->rtable[]
array, which gives the nexthop ports for each of the other switches
in the tree.
For the example topology above, the dsa platform data would look
something like this:
static struct dsa_chip_data sw[2] = {
{
.mii_bus = &foo,
.sw_addr = 1,
.port_names[0] = "p1",
.port_names[1] = "p2",
.port_names[2] = "p3",
.port_names[3] = "p4",
.port_names[4] = "p5",
.port_names[5] = "p6",
.port_names[6] = "p7",
.port_names[7] = "p8",
.port_names[9] = "dsa",
.port_names[10] = "cpu",
.rtable = (s8 []){ -1, 9, },
}, {
.mii_bus = &foo,
.sw_addr = 2,
.port_names[0] = "p9",
.port_names[1] = "p10",
.port_names[2] = "p11",
.port_names[3] = "p12",
.port_names[4] = "p13",
.port_names[5] = "p14",
.port_names[6] = "p15",
.port_names[7] = "p16",
.port_names[10] = "dsa",
.rtable = (s8 []){ 10, -1, },
},
},
static struct dsa_platform_data pd = {
.netdev = &foo,
.nr_switches = 2,
.sw = sw,
};
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Gary Thomas <gary@mlbassoc.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-03-20 17:52:09 +08:00
|
|
|
* Copyright (c) 2008-2009 Marvell Semiconductor
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#include <linux/list.h>
|
2008-11-11 13:53:12 +08:00
|
|
|
#include <linux/etherdevice.h>
|
2015-02-25 05:15:33 +08:00
|
|
|
#include <linux/netdevice.h>
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
#include <linux/phy.h>
|
2014-10-18 07:02:13 +08:00
|
|
|
#include <linux/phy_fixed.h>
|
2018-05-11 04:17:36 +08:00
|
|
|
#include <linux/phylink.h>
|
2014-08-28 08:04:51 +08:00
|
|
|
#include <linux/of_net.h>
|
|
|
|
|
#include <linux/of_mdio.h>
|
2016-01-07 03:11:18 +08:00
|
|
|
#include <linux/mdio.h>
|
2015-02-25 05:15:33 +08:00
|
|
|
#include <net/rtnetlink.h>
|
2017-01-31 04:41:40 +08:00
|
|
|
#include <net/pkt_cls.h>
|
|
|
|
|
#include <net/tc_act/tc_mirred.h>
|
2015-02-25 05:15:33 +08:00
|
|
|
#include <linux/if_bridge.h>
|
2015-08-01 02:42:57 +08:00
|
|
|
#include <linux/netpoll.h>
|
2018-02-14 08:07:49 +08:00
|
|
|
#include <linux/ptp_classify.h>
|
2017-05-18 03:46:03 +08:00
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
#include "dsa_priv.h"
|
|
|
|
|
|
|
|
|
|
/* slave mii_bus handling ***************************************************/
|
|
|
|
|
static int dsa_slave_phy_read(struct mii_bus *bus, int addr, int reg)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_switch *ds = bus->priv;
|
|
|
|
|
|
2014-08-28 08:04:51 +08:00
|
|
|
if (ds->phys_mii_mask & (1 << addr))
|
2016-08-24 00:38:56 +08:00
|
|
|
return ds->ops->phy_read(ds, addr, reg);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
|
|
|
|
|
return 0xffff;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_phy_write(struct mii_bus *bus, int addr, int reg, u16 val)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_switch *ds = bus->priv;
|
|
|
|
|
|
2014-08-28 08:04:51 +08:00
|
|
|
if (ds->phys_mii_mask & (1 << addr))
|
2016-08-24 00:38:56 +08:00
|
|
|
return ds->ops->phy_write(ds, addr, reg, val);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void dsa_slave_mii_bus_init(struct dsa_switch *ds)
|
|
|
|
|
{
|
|
|
|
|
ds->slave_mii_bus->priv = (void *)ds;
|
|
|
|
|
ds->slave_mii_bus->name = "dsa slave smi";
|
|
|
|
|
ds->slave_mii_bus->read = dsa_slave_phy_read;
|
|
|
|
|
ds->slave_mii_bus->write = dsa_slave_phy_write;
|
2016-06-08 07:32:38 +08:00
|
|
|
snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "dsa-%d.%d",
|
2017-11-04 07:05:21 +08:00
|
|
|
ds->dst->index, ds->index);
|
2016-05-11 05:27:23 +08:00
|
|
|
ds->slave_mii_bus->parent = ds->dev;
|
net: dsa: set slave MII bus PHY mask
When registering a mdio bus, Linux assumes than every port has a PHY and tries
to scan it. If a switch port has no PHY registered, DSA will fail to register
the slave MII bus. To fix this, set the slave MII bus PHY mask to the switch
PHYs mask.
As an example, if we use a Marvell MV88E6352 (which is a 7-port switch with no
registered PHYs for port 5 and port 6), with the following declared names:
static struct dsa_chip_data switch_cdata = {
[...]
.port_names[0] = "sw0",
.port_names[1] = "sw1",
.port_names[2] = "sw2",
.port_names[3] = "sw3",
.port_names[4] = "sw4",
.port_names[5] = "cpu",
};
DSA will fail to create the switch instance. With the PHY mask set for the
slave MII bus, only the PHY for ports 0-4 will be scanned and the instance will
be successfully created.
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-01-21 08:13:32 +08:00
|
|
|
ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* slave device handling ****************************************************/
|
2015-04-02 23:07:08 +08:00
|
|
|
static int dsa_slave_get_iflink(const struct net_device *dev)
|
dsa: set ->iflink on slave interfaces to the ifindex of the parent
..so that we can parse the DSA topology from 'ip link' output:
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 16436 qdisc noqueue
2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast qlen 1000
3: eth1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast qlen 1000
4: lan1@eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc noqueue
5: lan2@eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
6: lan3@eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
7: lan4@eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-03-20 17:49:49 +08:00
|
|
|
{
|
2017-10-16 23:12:16 +08:00
|
|
|
return dsa_slave_to_master(dev)->ifindex;
|
dsa: set ->iflink on slave interfaces to the ifindex of the parent
..so that we can parse the DSA topology from 'ip link' output:
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 16436 qdisc noqueue
2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast qlen 1000
3: eth1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast qlen 1000
4: lan1@eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc noqueue
5: lan2@eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
6: lan3@eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
7: lan4@eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-03-20 17:49:49 +08:00
|
|
|
}
|
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
static int dsa_slave_open(struct net_device *dev)
|
|
|
|
|
{
|
2017-10-16 23:12:16 +08:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2008-11-11 13:53:12 +08:00
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (!(master->flags & IFF_UP))
|
|
|
|
|
return -ENETDOWN;
|
|
|
|
|
|
dsa: Convert compare_ether_addr to ether_addr_equal
Use the new bool function ether_addr_equal to add
some clarity and reduce the likelihood for misuse
of compare_ether_addr for sorting.
Done via cocci script:
$ cat compare_ether_addr.cocci
@@
expression a,b;
@@
- !compare_ether_addr(a, b)
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- compare_ether_addr(a, b)
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) == 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) != 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) == 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) != 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !!ether_addr_equal(a, b)
+ ether_addr_equal(a, b)
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-09 02:56:57 +08:00
|
|
|
if (!ether_addr_equal(dev->dev_addr, master->dev_addr)) {
|
2010-04-02 05:22:09 +08:00
|
|
|
err = dev_uc_add(master, dev->dev_addr);
|
2008-11-11 13:53:12 +08:00
|
|
|
if (err < 0)
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dev->flags & IFF_ALLMULTI) {
|
|
|
|
|
err = dev_set_allmulti(master, 1);
|
|
|
|
|
if (err < 0)
|
|
|
|
|
goto del_unicast;
|
|
|
|
|
}
|
|
|
|
|
if (dev->flags & IFF_PROMISC) {
|
|
|
|
|
err = dev_set_promiscuity(master, 1);
|
|
|
|
|
if (err < 0)
|
|
|
|
|
goto clear_allmulti;
|
|
|
|
|
}
|
|
|
|
|
|
2020-03-03 23:01:46 +08:00
|
|
|
err = dsa_port_enable_rt(dp, dev->phydev);
|
2017-09-23 07:01:56 +08:00
|
|
|
if (err)
|
|
|
|
|
goto clear_promisc;
|
2015-02-25 05:15:33 +08:00
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
return 0;
|
2008-11-11 13:53:12 +08:00
|
|
|
|
2014-09-25 08:05:18 +08:00
|
|
|
clear_promisc:
|
|
|
|
|
if (dev->flags & IFF_PROMISC)
|
2015-06-25 21:50:13 +08:00
|
|
|
dev_set_promiscuity(master, -1);
|
2008-11-11 13:53:12 +08:00
|
|
|
clear_allmulti:
|
|
|
|
|
if (dev->flags & IFF_ALLMULTI)
|
|
|
|
|
dev_set_allmulti(master, -1);
|
|
|
|
|
del_unicast:
|
dsa: Convert compare_ether_addr to ether_addr_equal
Use the new bool function ether_addr_equal to add
some clarity and reduce the likelihood for misuse
of compare_ether_addr for sorting.
Done via cocci script:
$ cat compare_ether_addr.cocci
@@
expression a,b;
@@
- !compare_ether_addr(a, b)
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- compare_ether_addr(a, b)
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) == 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) != 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) == 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) != 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !!ether_addr_equal(a, b)
+ ether_addr_equal(a, b)
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-09 02:56:57 +08:00
|
|
|
if (!ether_addr_equal(dev->dev_addr, master->dev_addr))
|
2010-04-02 05:22:09 +08:00
|
|
|
dev_uc_del(master, dev->dev_addr);
|
2008-11-11 13:53:12 +08:00
|
|
|
out:
|
|
|
|
|
return err;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_close(struct net_device *dev)
|
|
|
|
|
{
|
2017-10-16 23:12:16 +08:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2008-11-11 13:53:12 +08:00
|
|
|
|
2020-03-03 23:01:46 +08:00
|
|
|
dsa_port_disable_rt(dp);
|
2017-09-23 07:01:55 +08:00
|
|
|
|
2008-11-11 13:53:12 +08:00
|
|
|
dev_mc_unsync(master, dev);
|
2010-04-02 05:22:09 +08:00
|
|
|
dev_uc_unsync(master, dev);
|
2008-11-11 13:53:12 +08:00
|
|
|
if (dev->flags & IFF_ALLMULTI)
|
|
|
|
|
dev_set_allmulti(master, -1);
|
|
|
|
|
if (dev->flags & IFF_PROMISC)
|
|
|
|
|
dev_set_promiscuity(master, -1);
|
|
|
|
|
|
dsa: Convert compare_ether_addr to ether_addr_equal
Use the new bool function ether_addr_equal to add
some clarity and reduce the likelihood for misuse
of compare_ether_addr for sorting.
Done via cocci script:
$ cat compare_ether_addr.cocci
@@
expression a,b;
@@
- !compare_ether_addr(a, b)
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- compare_ether_addr(a, b)
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) == 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) != 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) == 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) != 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !!ether_addr_equal(a, b)
+ ether_addr_equal(a, b)
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-09 02:56:57 +08:00
|
|
|
if (!ether_addr_equal(dev->dev_addr, master->dev_addr))
|
2010-04-02 05:22:09 +08:00
|
|
|
dev_uc_del(master, dev->dev_addr);
|
2008-11-11 13:53:12 +08:00
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dsa_slave_change_rx_flags(struct net_device *dev, int change)
|
|
|
|
|
{
|
2017-10-16 23:12:16 +08:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2019-02-02 22:29:35 +08:00
|
|
|
if (dev->flags & IFF_UP) {
|
|
|
|
|
if (change & IFF_ALLMULTI)
|
|
|
|
|
dev_set_allmulti(master,
|
|
|
|
|
dev->flags & IFF_ALLMULTI ? 1 : -1);
|
|
|
|
|
if (change & IFF_PROMISC)
|
|
|
|
|
dev_set_promiscuity(master,
|
|
|
|
|
dev->flags & IFF_PROMISC ? 1 : -1);
|
|
|
|
|
}
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dsa_slave_set_rx_mode(struct net_device *dev)
|
|
|
|
|
{
|
2017-10-16 23:12:16 +08:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
|
|
|
|
|
dev_mc_sync(master, dev);
|
2010-04-02 05:22:09 +08:00
|
|
|
dev_uc_sync(master, dev);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
}
|
|
|
|
|
|
2008-11-11 13:53:12 +08:00
|
|
|
static int dsa_slave_set_mac_address(struct net_device *dev, void *a)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
{
|
2017-10-16 23:12:16 +08:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2008-11-11 13:53:12 +08:00
|
|
|
struct sockaddr *addr = a;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (!is_valid_ether_addr(addr->sa_data))
|
|
|
|
|
return -EADDRNOTAVAIL;
|
|
|
|
|
|
|
|
|
|
if (!(dev->flags & IFF_UP))
|
|
|
|
|
goto out;
|
|
|
|
|
|
dsa: Convert compare_ether_addr to ether_addr_equal
Use the new bool function ether_addr_equal to add
some clarity and reduce the likelihood for misuse
of compare_ether_addr for sorting.
Done via cocci script:
$ cat compare_ether_addr.cocci
@@
expression a,b;
@@
- !compare_ether_addr(a, b)
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- compare_ether_addr(a, b)
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) == 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) != 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) == 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) != 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !!ether_addr_equal(a, b)
+ ether_addr_equal(a, b)
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-09 02:56:57 +08:00
|
|
|
if (!ether_addr_equal(addr->sa_data, master->dev_addr)) {
|
2010-04-02 05:22:09 +08:00
|
|
|
err = dev_uc_add(master, addr->sa_data);
|
2008-11-11 13:53:12 +08:00
|
|
|
if (err < 0)
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
dsa: Convert compare_ether_addr to ether_addr_equal
Use the new bool function ether_addr_equal to add
some clarity and reduce the likelihood for misuse
of compare_ether_addr for sorting.
Done via cocci script:
$ cat compare_ether_addr.cocci
@@
expression a,b;
@@
- !compare_ether_addr(a, b)
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- compare_ether_addr(a, b)
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) == 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) != 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) == 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) != 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !!ether_addr_equal(a, b)
+ ether_addr_equal(a, b)
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-09 02:56:57 +08:00
|
|
|
if (!ether_addr_equal(dev->dev_addr, master->dev_addr))
|
2010-04-02 05:22:09 +08:00
|
|
|
dev_uc_del(master, dev->dev_addr);
|
2008-11-11 13:53:12 +08:00
|
|
|
|
|
|
|
|
out:
|
2014-01-21 01:52:20 +08:00
|
|
|
ether_addr_copy(dev->dev_addr, addr->sa_data);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-06 21:15:49 +08:00
|
|
|
struct dsa_slave_dump_ctx {
|
|
|
|
|
struct net_device *dev;
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
struct netlink_callback *cb;
|
|
|
|
|
int idx;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
dsa_slave_port_fdb_do_dump(const unsigned char *addr, u16 vid,
|
|
|
|
|
bool is_static, void *data)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_slave_dump_ctx *dump = data;
|
|
|
|
|
u32 portid = NETLINK_CB(dump->cb->skb).portid;
|
|
|
|
|
u32 seq = dump->cb->nlh->nlmsg_seq;
|
|
|
|
|
struct nlmsghdr *nlh;
|
|
|
|
|
struct ndmsg *ndm;
|
|
|
|
|
|
|
|
|
|
if (dump->idx < dump->cb->args[2])
|
|
|
|
|
goto skip;
|
|
|
|
|
|
|
|
|
|
nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
|
|
|
|
|
sizeof(*ndm), NLM_F_MULTI);
|
|
|
|
|
if (!nlh)
|
|
|
|
|
return -EMSGSIZE;
|
|
|
|
|
|
|
|
|
|
ndm = nlmsg_data(nlh);
|
|
|
|
|
ndm->ndm_family = AF_BRIDGE;
|
|
|
|
|
ndm->ndm_pad1 = 0;
|
|
|
|
|
ndm->ndm_pad2 = 0;
|
|
|
|
|
ndm->ndm_flags = NTF_SELF;
|
|
|
|
|
ndm->ndm_type = 0;
|
|
|
|
|
ndm->ndm_ifindex = dump->dev->ifindex;
|
|
|
|
|
ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
|
|
|
|
|
|
|
|
|
|
if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
|
|
|
|
|
goto nla_put_failure;
|
|
|
|
|
|
|
|
|
|
if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
|
|
|
|
|
goto nla_put_failure;
|
|
|
|
|
|
|
|
|
|
nlmsg_end(dump->skb, nlh);
|
|
|
|
|
|
|
|
|
|
skip:
|
|
|
|
|
dump->idx++;
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
nla_put_failure:
|
|
|
|
|
nlmsg_cancel(dump->skb, nlh);
|
|
|
|
|
return -EMSGSIZE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
dsa_slave_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb,
|
|
|
|
|
struct net_device *dev, struct net_device *filter_dev,
|
|
|
|
|
int *idx)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2017-08-06 21:15:49 +08:00
|
|
|
struct dsa_slave_dump_ctx dump = {
|
|
|
|
|
.dev = dev,
|
|
|
|
|
.skb = skb,
|
|
|
|
|
.cb = cb,
|
|
|
|
|
.idx = *idx,
|
|
|
|
|
};
|
|
|
|
|
int err;
|
|
|
|
|
|
2017-09-21 07:32:14 +08:00
|
|
|
err = dsa_port_fdb_dump(dp, dsa_slave_port_fdb_do_dump, &dump);
|
2017-08-06 21:15:49 +08:00
|
|
|
*idx = dump.idx;
|
2017-09-21 07:32:14 +08:00
|
|
|
|
2017-08-06 21:15:49 +08:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
static int dsa_slave_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
|
|
|
|
{
|
2018-02-14 08:07:48 +08:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
|
struct dsa_switch *ds = p->dp->ds;
|
|
|
|
|
int port = p->dp->index;
|
|
|
|
|
|
|
|
|
|
/* Pass through to switch driver if it supports timestamping */
|
|
|
|
|
switch (cmd) {
|
|
|
|
|
case SIOCGHWTSTAMP:
|
|
|
|
|
if (ds->ops->port_hwtstamp_get)
|
|
|
|
|
return ds->ops->port_hwtstamp_get(ds, port, ifr);
|
|
|
|
|
break;
|
|
|
|
|
case SIOCSHWTSTAMP:
|
|
|
|
|
if (ds->ops->port_hwtstamp_set)
|
|
|
|
|
return ds->ops->port_hwtstamp_set(ds, port, ifr);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2018-05-11 04:17:36 +08:00
|
|
|
return phylink_mii_ioctl(p->dp->pl, ifr, cmd);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
}
|
|
|
|
|
|
2015-05-11 00:47:51 +08:00
|
|
|
static int dsa_slave_port_attr_set(struct net_device *dev,
|
2015-10-15 01:40:49 +08:00
|
|
|
const struct switchdev_attr *attr,
|
2015-09-24 16:02:41 +08:00
|
|
|
struct switchdev_trans *trans)
|
2015-05-11 00:47:51 +08:00
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2015-09-30 00:38:36 +08:00
|
|
|
int ret;
|
2015-05-11 00:47:51 +08:00
|
|
|
|
|
|
|
|
switch (attr->id) {
|
2015-10-01 17:03:42 +08:00
|
|
|
case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
|
2017-05-20 05:00:36 +08:00
|
|
|
ret = dsa_port_set_state(dp, attr->u.stp_state, trans);
|
2015-05-11 00:47:51 +08:00
|
|
|
break;
|
2016-02-27 02:16:00 +08:00
|
|
|
case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
|
2017-05-20 05:00:42 +08:00
|
|
|
ret = dsa_port_vlan_filtering(dp, attr->u.vlan_filtering,
|
|
|
|
|
trans);
|
2016-02-27 02:16:00 +08:00
|
|
|
break;
|
2016-07-19 08:45:38 +08:00
|
|
|
case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
|
2017-05-20 05:00:43 +08:00
|
|
|
ret = dsa_port_ageing_time(dp, attr->u.ageing_time, trans);
|
2016-07-19 08:45:38 +08:00
|
|
|
break;
|
2019-02-21 08:58:22 +08:00
|
|
|
case SWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS:
|
|
|
|
|
ret = dsa_port_pre_bridge_flags(dp, attr->u.brport_flags,
|
|
|
|
|
trans);
|
|
|
|
|
break;
|
2019-02-21 07:35:04 +08:00
|
|
|
case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:
|
|
|
|
|
ret = dsa_port_bridge_flags(dp, attr->u.brport_flags, trans);
|
|
|
|
|
break;
|
2019-07-09 11:31:13 +08:00
|
|
|
case SWITCHDEV_ATTR_ID_BRIDGE_MROUTER:
|
|
|
|
|
ret = dsa_port_mrouter(dp->cpu_dp, attr->u.mrouter, trans);
|
|
|
|
|
break;
|
2015-05-11 00:47:51 +08:00
|
|
|
default:
|
|
|
|
|
ret = -EOPNOTSUPP;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-21 08:10:26 +08:00
|
|
|
/* Must be called under rcu_read_lock() */
|
|
|
|
|
static int
|
|
|
|
|
dsa_slave_vlan_check_for_8021q_uppers(struct net_device *slave,
|
|
|
|
|
const struct switchdev_obj_port_vlan *vlan)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *upper_dev;
|
|
|
|
|
struct list_head *iter;
|
|
|
|
|
|
|
|
|
|
netdev_for_each_upper_dev_rcu(slave, upper_dev, iter) {
|
|
|
|
|
u16 vid;
|
|
|
|
|
|
|
|
|
|
if (!is_vlan_dev(upper_dev))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
vid = vlan_dev_vlan_id(upper_dev);
|
|
|
|
|
if (vid >= vlan->vid_begin && vid <= vlan->vid_end)
|
|
|
|
|
return -EBUSY;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-08-26 01:25:17 +08:00
|
|
|
static int dsa_slave_vlan_add(struct net_device *dev,
|
|
|
|
|
const struct switchdev_obj *obj,
|
|
|
|
|
struct switchdev_trans *trans)
|
|
|
|
|
{
|
2020-09-21 08:10:29 +08:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2019-08-26 01:25:17 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct switchdev_obj_port_vlan vlan;
|
2020-09-21 08:10:29 +08:00
|
|
|
int vid, err;
|
2019-08-26 01:25:17 +08:00
|
|
|
|
|
|
|
|
if (obj->orig_dev != dev)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
2020-05-13 01:20:25 +08:00
|
|
|
if (dsa_port_skip_vlan_configuration(dp))
|
2019-08-26 01:25:18 +08:00
|
|
|
return 0;
|
|
|
|
|
|
2019-08-26 01:25:17 +08:00
|
|
|
vlan = *SWITCHDEV_OBJ_PORT_VLAN(obj);
|
|
|
|
|
|
2020-09-21 08:10:26 +08:00
|
|
|
/* Deny adding a bridge VLAN when there is already an 802.1Q upper with
|
|
|
|
|
* the same VID.
|
|
|
|
|
*/
|
2020-09-21 08:10:28 +08:00
|
|
|
if (trans->ph_prepare && br_vlan_enabled(dp->bridge_dev)) {
|
2020-09-21 08:10:26 +08:00
|
|
|
rcu_read_lock();
|
|
|
|
|
err = dsa_slave_vlan_check_for_8021q_uppers(dev, &vlan);
|
|
|
|
|
rcu_read_unlock();
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2019-08-26 01:25:17 +08:00
|
|
|
err = dsa_port_vlan_add(dp, &vlan, trans);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
2019-08-26 01:25:20 +08:00
|
|
|
/* We need the dedicated CPU port to be a member of the VLAN as well.
|
|
|
|
|
* Even though drivers often handle CPU membership in special ways,
|
|
|
|
|
* it doesn't make sense to program a PVID, so clear this flag.
|
|
|
|
|
*/
|
|
|
|
|
vlan.flags &= ~BRIDGE_VLAN_INFO_PVID;
|
|
|
|
|
|
2019-08-26 01:25:19 +08:00
|
|
|
err = dsa_port_vlan_add(dp->cpu_dp, &vlan, trans);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
2020-09-21 08:10:29 +08:00
|
|
|
for (vid = vlan.vid_begin; vid <= vlan.vid_end; vid++) {
|
|
|
|
|
err = vlan_vid_add(master, htons(ETH_P_8021Q), vid);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2019-08-26 01:25:17 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2015-08-10 21:09:53 +08:00
|
|
|
static int dsa_slave_port_obj_add(struct net_device *dev,
|
2015-10-01 17:03:45 +08:00
|
|
|
const struct switchdev_obj *obj,
|
2019-06-15 01:49:22 +08:00
|
|
|
struct switchdev_trans *trans,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
2015-08-10 21:09:53 +08:00
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2015-08-10 21:09:53 +08:00
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
/* For the prepare phase, ensure the full set of changes is feasable in
|
|
|
|
|
* one go in order to signal a failure properly. If an operation is not
|
|
|
|
|
* supported, return -EOPNOTSUPP.
|
|
|
|
|
*/
|
|
|
|
|
|
2015-10-01 17:03:46 +08:00
|
|
|
switch (obj->id) {
|
2016-08-31 23:50:03 +08:00
|
|
|
case SWITCHDEV_OBJ_ID_PORT_MDB:
|
2019-06-15 01:49:22 +08:00
|
|
|
if (obj->orig_dev != dev)
|
|
|
|
|
return -EOPNOTSUPP;
|
2017-05-20 05:00:40 +08:00
|
|
|
err = dsa_port_mdb_add(dp, SWITCHDEV_OBJ_PORT_MDB(obj), trans);
|
2016-08-31 23:50:03 +08:00
|
|
|
break;
|
2017-11-10 06:11:00 +08:00
|
|
|
case SWITCHDEV_OBJ_ID_HOST_MDB:
|
|
|
|
|
/* DSA can directly translate this to a normal MDB add,
|
|
|
|
|
* but on the CPU port.
|
|
|
|
|
*/
|
|
|
|
|
err = dsa_port_mdb_add(dp->cpu_dp, SWITCHDEV_OBJ_PORT_MDB(obj),
|
|
|
|
|
trans);
|
|
|
|
|
break;
|
2015-10-01 17:03:41 +08:00
|
|
|
case SWITCHDEV_OBJ_ID_PORT_VLAN:
|
2019-08-26 01:25:17 +08:00
|
|
|
err = dsa_slave_vlan_add(dev, obj, trans);
|
2015-08-14 00:52:17 +08:00
|
|
|
break;
|
2015-08-10 21:09:53 +08:00
|
|
|
default:
|
|
|
|
|
err = -EOPNOTSUPP;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2019-08-26 01:25:17 +08:00
|
|
|
static int dsa_slave_vlan_del(struct net_device *dev,
|
|
|
|
|
const struct switchdev_obj *obj)
|
|
|
|
|
{
|
2020-09-21 08:10:29 +08:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2019-08-26 01:25:17 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2020-09-21 08:10:29 +08:00
|
|
|
struct switchdev_obj_port_vlan *vlan;
|
|
|
|
|
int vid, err;
|
2019-08-26 01:25:17 +08:00
|
|
|
|
|
|
|
|
if (obj->orig_dev != dev)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
2020-05-13 01:20:25 +08:00
|
|
|
if (dsa_port_skip_vlan_configuration(dp))
|
2019-08-26 01:25:18 +08:00
|
|
|
return 0;
|
|
|
|
|
|
2020-09-21 08:10:29 +08:00
|
|
|
vlan = SWITCHDEV_OBJ_PORT_VLAN(obj);
|
|
|
|
|
|
2019-08-26 01:25:19 +08:00
|
|
|
/* Do not deprogram the CPU port as it may be shared with other user
|
|
|
|
|
* ports which can be members of this VLAN as well.
|
|
|
|
|
*/
|
2020-09-21 08:10:29 +08:00
|
|
|
err = dsa_port_vlan_del(dp, vlan);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++)
|
|
|
|
|
vlan_vid_del(master, htons(ETH_P_8021Q), vid);
|
|
|
|
|
|
|
|
|
|
return 0;
|
2019-08-26 01:25:17 +08:00
|
|
|
}
|
|
|
|
|
|
2015-08-10 21:09:53 +08:00
|
|
|
static int dsa_slave_port_obj_del(struct net_device *dev,
|
2015-10-01 17:03:45 +08:00
|
|
|
const struct switchdev_obj *obj)
|
2015-08-10 21:09:53 +08:00
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2015-08-10 21:09:53 +08:00
|
|
|
int err;
|
|
|
|
|
|
2015-10-01 17:03:46 +08:00
|
|
|
switch (obj->id) {
|
2016-08-31 23:50:03 +08:00
|
|
|
case SWITCHDEV_OBJ_ID_PORT_MDB:
|
2019-06-15 01:49:22 +08:00
|
|
|
if (obj->orig_dev != dev)
|
|
|
|
|
return -EOPNOTSUPP;
|
2017-05-20 05:00:40 +08:00
|
|
|
err = dsa_port_mdb_del(dp, SWITCHDEV_OBJ_PORT_MDB(obj));
|
2016-08-31 23:50:03 +08:00
|
|
|
break;
|
2017-11-10 06:11:00 +08:00
|
|
|
case SWITCHDEV_OBJ_ID_HOST_MDB:
|
|
|
|
|
/* DSA can directly translate this to a normal MDB add,
|
|
|
|
|
* but on the CPU port.
|
|
|
|
|
*/
|
|
|
|
|
err = dsa_port_mdb_del(dp->cpu_dp, SWITCHDEV_OBJ_PORT_MDB(obj));
|
|
|
|
|
break;
|
2015-10-01 17:03:41 +08:00
|
|
|
case SWITCHDEV_OBJ_ID_PORT_VLAN:
|
2019-08-26 01:25:17 +08:00
|
|
|
err = dsa_slave_vlan_del(dev, obj);
|
2015-08-14 00:52:17 +08:00
|
|
|
break;
|
2015-08-10 21:09:53 +08:00
|
|
|
default:
|
|
|
|
|
err = -EOPNOTSUPP;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2019-02-07 01:45:45 +08:00
|
|
|
static int dsa_slave_get_port_parent_id(struct net_device *dev,
|
|
|
|
|
struct netdev_phys_item_id *ppid)
|
2015-02-25 05:15:33 +08:00
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2017-11-10 05:29:51 +08:00
|
|
|
struct dsa_switch_tree *dst = ds->dst;
|
2015-02-25 05:15:33 +08:00
|
|
|
|
2019-04-03 20:24:26 +08:00
|
|
|
/* For non-legacy ports, devlink is used and it takes
|
|
|
|
|
* care of the name generation. This ndo implementation
|
|
|
|
|
* should be removed with legacy support.
|
|
|
|
|
*/
|
|
|
|
|
if (dp->ds->devlink)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
2019-02-07 01:45:45 +08:00
|
|
|
ppid->id_len = sizeof(dst->index);
|
|
|
|
|
memcpy(&ppid->id, &dst->index, ppid->id_len);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2017-09-21 07:31:57 +08:00
|
|
|
static inline netdev_tx_t dsa_slave_netpoll_send_skb(struct net_device *dev,
|
|
|
|
|
struct sk_buff *skb)
|
2015-08-01 02:42:57 +08:00
|
|
|
{
|
|
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
2017-09-21 07:31:57 +08:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
|
|
2020-05-08 00:32:21 +08:00
|
|
|
return netpoll_send_skb(p->netpoll, skb);
|
2015-08-01 02:42:57 +08:00
|
|
|
#else
|
|
|
|
|
BUG();
|
|
|
|
|
return NETDEV_TX_OK;
|
2020-05-08 00:32:21 +08:00
|
|
|
#endif
|
2015-08-01 02:42:57 +08:00
|
|
|
}
|
|
|
|
|
|
2018-02-14 08:07:49 +08:00
|
|
|
static void dsa_skb_tx_timestamp(struct dsa_slave_priv *p,
|
|
|
|
|
struct sk_buff *skb)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_switch *ds = p->dp->ds;
|
|
|
|
|
struct sk_buff *clone;
|
|
|
|
|
unsigned int type;
|
|
|
|
|
|
|
|
|
|
type = ptp_classify_raw(skb);
|
|
|
|
|
if (type == PTP_CLASS_NONE)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
if (!ds->ops->port_txtstamp)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
clone = skb_clone_sk(skb);
|
|
|
|
|
if (!clone)
|
|
|
|
|
return;
|
|
|
|
|
|
2020-11-19 19:09:06 +08:00
|
|
|
if (ds->ops->port_txtstamp(ds, p->dp->index, clone, type)) {
|
|
|
|
|
DSA_SKB_CB(skb)->clone = clone;
|
2018-02-14 08:07:49 +08:00
|
|
|
return;
|
2020-11-19 19:09:06 +08:00
|
|
|
}
|
2018-02-14 08:07:49 +08:00
|
|
|
|
|
|
|
|
kfree_skb(clone);
|
|
|
|
|
}
|
|
|
|
|
|
2019-05-05 18:19:25 +08:00
|
|
|
netdev_tx_t dsa_enqueue_skb(struct sk_buff *skb, struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
/* SKB for netpoll still need to be mangled with the protocol-specific
|
|
|
|
|
* tag to be successfully transmitted
|
|
|
|
|
*/
|
|
|
|
|
if (unlikely(netpoll_tx_running(dev)))
|
|
|
|
|
return dsa_slave_netpoll_send_skb(dev, skb);
|
|
|
|
|
|
|
|
|
|
/* Queue the SKB for transmission on the parent interface, but
|
|
|
|
|
* do not modify its EtherType
|
|
|
|
|
*/
|
|
|
|
|
skb->dev = dsa_slave_to_master(dev);
|
|
|
|
|
dev_queue_xmit(skb);
|
|
|
|
|
|
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
|
}
|
|
|
|
|
EXPORT_SYMBOL_GPL(dsa_enqueue_skb);
|
|
|
|
|
|
net: dsa: implement a central TX reallocation procedure
At the moment, taggers are left with the task of ensuring that the skb
headers are writable (which they aren't, if the frames were cloned for
TX timestamping, for flooding by the bridge, etc), and that there is
enough space in the skb data area for the DSA tag to be pushed.
Moreover, the life of tail taggers is even harder, because they need to
ensure that short frames have enough padding, a problem that normal
taggers don't have.
The principle of the DSA framework is that everything except for the
most intimate hardware specifics (like in this case, the actual packing
of the DSA tag bits) should be done inside the core, to avoid having
code paths that are very rarely tested.
So provide a TX reallocation procedure that should cover the known needs
of DSA today.
Note that this patch also gives the network stack a good hint about the
headroom/tailroom it's going to need. Up till now it wasn't doing that.
So the reallocation procedure should really be there only for the
exceptional cases, and for cloned packets which need to be unshared.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Christian Eggers <ceggers@arri.de> # For tail taggers only
Tested-by: Kurt Kanzenbach <kurt@linutronix.de>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-02 03:16:09 +08:00
|
|
|
static int dsa_realloc_skb(struct sk_buff *skb, struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
int needed_headroom = dev->needed_headroom;
|
|
|
|
|
int needed_tailroom = dev->needed_tailroom;
|
|
|
|
|
|
|
|
|
|
/* For tail taggers, we need to pad short frames ourselves, to ensure
|
|
|
|
|
* that the tail tag does not fail at its role of being at the end of
|
|
|
|
|
* the packet, once the master interface pads the frame. Account for
|
|
|
|
|
* that pad length here, and pad later.
|
|
|
|
|
*/
|
|
|
|
|
if (unlikely(needed_tailroom && skb->len < ETH_ZLEN))
|
|
|
|
|
needed_tailroom += ETH_ZLEN - skb->len;
|
|
|
|
|
/* skb_headroom() returns unsigned int... */
|
|
|
|
|
needed_headroom = max_t(int, needed_headroom - skb_headroom(skb), 0);
|
|
|
|
|
needed_tailroom = max_t(int, needed_tailroom - skb_tailroom(skb), 0);
|
|
|
|
|
|
|
|
|
|
if (likely(!needed_headroom && !needed_tailroom && !skb_cloned(skb)))
|
|
|
|
|
/* No reallocation needed, yay! */
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
return pskb_expand_head(skb, needed_headroom, needed_tailroom,
|
|
|
|
|
GFP_ATOMIC);
|
|
|
|
|
}
|
|
|
|
|
|
2014-08-28 08:04:46 +08:00
|
|
|
static netdev_tx_t dsa_slave_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
2015-08-01 02:42:56 +08:00
|
|
|
struct sk_buff *nskb;
|
2014-08-28 08:04:46 +08:00
|
|
|
|
2020-11-08 04:49:46 +08:00
|
|
|
dev_sw_netstats_tx_add(dev, 1, skb->len);
|
2014-08-28 08:04:46 +08:00
|
|
|
|
2019-06-08 20:04:27 +08:00
|
|
|
DSA_SKB_CB(skb)->clone = NULL;
|
2019-05-12 04:14:45 +08:00
|
|
|
|
2018-02-14 08:07:49 +08:00
|
|
|
/* Identify PTP protocol packets, clone them, and pass them to the
|
|
|
|
|
* switch driver
|
|
|
|
|
*/
|
|
|
|
|
dsa_skb_tx_timestamp(p, skb);
|
|
|
|
|
|
net: dsa: implement a central TX reallocation procedure
At the moment, taggers are left with the task of ensuring that the skb
headers are writable (which they aren't, if the frames were cloned for
TX timestamping, for flooding by the bridge, etc), and that there is
enough space in the skb data area for the DSA tag to be pushed.
Moreover, the life of tail taggers is even harder, because they need to
ensure that short frames have enough padding, a problem that normal
taggers don't have.
The principle of the DSA framework is that everything except for the
most intimate hardware specifics (like in this case, the actual packing
of the DSA tag bits) should be done inside the core, to avoid having
code paths that are very rarely tested.
So provide a TX reallocation procedure that should cover the known needs
of DSA today.
Note that this patch also gives the network stack a good hint about the
headroom/tailroom it's going to need. Up till now it wasn't doing that.
So the reallocation procedure should really be there only for the
exceptional cases, and for cloned packets which need to be unshared.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Christian Eggers <ceggers@arri.de> # For tail taggers only
Tested-by: Kurt Kanzenbach <kurt@linutronix.de>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-02 03:16:09 +08:00
|
|
|
if (dsa_realloc_skb(skb, dev)) {
|
|
|
|
|
dev_kfree_skb_any(skb);
|
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* needed_tailroom should still be 'warm' in the cache line from
|
|
|
|
|
* dsa_realloc_skb(), which has also ensured that padding is safe.
|
|
|
|
|
*/
|
|
|
|
|
if (dev->needed_tailroom)
|
|
|
|
|
eth_skb_pad(skb);
|
|
|
|
|
|
2017-06-02 04:07:15 +08:00
|
|
|
/* Transmit function may have to reallocate the original SKB,
|
|
|
|
|
* in which case it must have freed it. Only free it here on error.
|
|
|
|
|
*/
|
2015-08-01 02:42:56 +08:00
|
|
|
nskb = p->xmit(skb, dev);
|
2017-06-02 04:07:15 +08:00
|
|
|
if (!nskb) {
|
net: dsa: Make deferred_xmit private to sja1105
There are 3 things that are wrong with the DSA deferred xmit mechanism:
1. Its introduction has made the DSA hotpath ever so slightly more
inefficient for everybody, since DSA_SKB_CB(skb)->deferred_xmit needs
to be initialized to false for every transmitted frame, in order to
figure out whether the driver requested deferral or not (a very rare
occasion, rare even for the only driver that does use this mechanism:
sja1105). That was necessary to avoid kfree_skb from freeing the skb.
2. Because L2 PTP is a link-local protocol like STP, it requires
management routes and deferred xmit with this switch. But as opposed
to STP, the deferred work mechanism needs to schedule the packet
rather quickly for the TX timstamp to be collected in time and sent
to user space. But there is no provision for controlling the
scheduling priority of this deferred xmit workqueue. Too bad this is
a rather specific requirement for a feature that nobody else uses
(more below).
3. Perhaps most importantly, it makes the DSA core adhere a bit too
much to the NXP company-wide policy "Innovate Where It Doesn't
Matter". The sja1105 is probably the only DSA switch that requires
some frames sent from the CPU to be routed to the slave port via an
out-of-band configuration (register write) rather than in-band (DSA
tag). And there are indeed very good reasons to not want to do that:
if that out-of-band register is at the other end of a slow bus such
as SPI, then you limit that Ethernet flow's throughput to effectively
the throughput of the SPI bus. So hardware vendors should definitely
not be encouraged to design this way. We do _not_ want more
widespread use of this mechanism.
Luckily we have a solution for each of the 3 issues:
For 1, we can just remove that variable in the skb->cb and counteract
the effect of kfree_skb with skb_get, much to the same effect. The
advantage, of course, being that anybody who doesn't use deferred xmit
doesn't need to do any extra operation in the hotpath.
For 2, we can create a kernel thread for each port's deferred xmit work.
If the user switch ports are named swp0, swp1, swp2, the kernel threads
will be named swp0_xmit, swp1_xmit, swp2_xmit (there appears to be a 15
character length limit on kernel thread names). With this, the user can
change the scheduling priority with chrt $(pidof swp2_xmit).
For 3, we can actually move the entire implementation to the sja1105
driver.
So this patch deletes the generic implementation from the DSA core and
adds a new one, more adequate to the requirements of PTP TX
timestamping, in sja1105_main.c.
Suggested-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-04 08:37:10 +08:00
|
|
|
kfree_skb(skb);
|
2015-08-01 02:42:56 +08:00
|
|
|
return NETDEV_TX_OK;
|
2017-06-02 04:07:15 +08:00
|
|
|
}
|
2014-08-28 08:04:52 +08:00
|
|
|
|
2019-05-05 18:19:25 +08:00
|
|
|
return dsa_enqueue_skb(nskb, dev);
|
|
|
|
|
}
|
2015-08-01 02:42:57 +08:00
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
/* ethtool operations *******************************************************/
|
|
|
|
|
|
|
|
|
|
static void dsa_slave_get_drvinfo(struct net_device *dev,
|
|
|
|
|
struct ethtool_drvinfo *drvinfo)
|
|
|
|
|
{
|
2013-01-06 08:44:26 +08:00
|
|
|
strlcpy(drvinfo->driver, "dsa", sizeof(drvinfo->driver));
|
|
|
|
|
strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
|
|
|
|
|
strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
}
|
|
|
|
|
|
2014-10-30 01:45:04 +08:00
|
|
|
static int dsa_slave_get_regs_len(struct net_device *dev)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-10-30 01:45:04 +08:00
|
|
|
|
2016-08-24 00:38:56 +08:00
|
|
|
if (ds->ops->get_regs_len)
|
2017-10-16 23:12:15 +08:00
|
|
|
return ds->ops->get_regs_len(ds, dp->index);
|
2014-10-30 01:45:04 +08:00
|
|
|
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
dsa_slave_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-10-30 01:45:04 +08:00
|
|
|
|
2016-08-24 00:38:56 +08:00
|
|
|
if (ds->ops->get_regs)
|
2017-10-16 23:12:15 +08:00
|
|
|
ds->ops->get_regs(ds, dp->index, regs, _p);
|
2014-10-30 01:45:04 +08:00
|
|
|
}
|
|
|
|
|
|
2018-05-11 04:17:36 +08:00
|
|
|
static int dsa_slave_nway_reset(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
|
|
return phylink_ethtool_nway_reset(dp->pl);
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-30 01:45:01 +08:00
|
|
|
static int dsa_slave_get_eeprom_len(struct net_device *dev)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-10-30 01:45:01 +08:00
|
|
|
|
2016-06-05 03:16:52 +08:00
|
|
|
if (ds->cd && ds->cd->eeprom_len)
|
2016-05-11 05:27:24 +08:00
|
|
|
return ds->cd->eeprom_len;
|
2014-10-30 01:45:01 +08:00
|
|
|
|
2016-08-24 00:38:56 +08:00
|
|
|
if (ds->ops->get_eeprom_len)
|
|
|
|
|
return ds->ops->get_eeprom_len(ds);
|
2014-10-30 01:45:01 +08:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_get_eeprom(struct net_device *dev,
|
|
|
|
|
struct ethtool_eeprom *eeprom, u8 *data)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-10-30 01:45:01 +08:00
|
|
|
|
2016-08-24 00:38:56 +08:00
|
|
|
if (ds->ops->get_eeprom)
|
|
|
|
|
return ds->ops->get_eeprom(ds, eeprom, data);
|
2014-10-30 01:45:01 +08:00
|
|
|
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_set_eeprom(struct net_device *dev,
|
|
|
|
|
struct ethtool_eeprom *eeprom, u8 *data)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-10-30 01:45:01 +08:00
|
|
|
|
2016-08-24 00:38:56 +08:00
|
|
|
if (ds->ops->set_eeprom)
|
|
|
|
|
return ds->ops->set_eeprom(ds, eeprom, data);
|
2014-10-30 01:45:01 +08:00
|
|
|
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
static void dsa_slave_get_strings(struct net_device *dev,
|
|
|
|
|
uint32_t stringset, uint8_t *data)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
|
|
|
|
|
if (stringset == ETH_SS_STATS) {
|
|
|
|
|
int len = ETH_GSTRING_LEN;
|
|
|
|
|
|
|
|
|
|
strncpy(data, "tx_packets", len);
|
|
|
|
|
strncpy(data + len, "tx_bytes", len);
|
|
|
|
|
strncpy(data + 2 * len, "rx_packets", len);
|
|
|
|
|
strncpy(data + 3 * len, "rx_bytes", len);
|
2016-08-24 00:38:56 +08:00
|
|
|
if (ds->ops->get_strings)
|
2018-04-26 03:12:50 +08:00
|
|
|
ds->ops->get_strings(ds, dp->index, stringset,
|
|
|
|
|
data + 4 * len);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dsa_slave_get_ethtool_stats(struct net_device *dev,
|
|
|
|
|
struct ethtool_stats *stats,
|
|
|
|
|
uint64_t *data)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2017-08-04 12:33:27 +08:00
|
|
|
struct pcpu_sw_netstats *s;
|
2017-08-02 06:00:36 +08:00
|
|
|
unsigned int start;
|
2017-08-04 12:33:27 +08:00
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for_each_possible_cpu(i) {
|
|
|
|
|
u64 tx_packets, tx_bytes, rx_packets, rx_bytes;
|
|
|
|
|
|
2020-11-08 04:49:46 +08:00
|
|
|
s = per_cpu_ptr(dev->tstats, i);
|
2017-08-04 12:33:27 +08:00
|
|
|
do {
|
|
|
|
|
start = u64_stats_fetch_begin_irq(&s->syncp);
|
|
|
|
|
tx_packets = s->tx_packets;
|
|
|
|
|
tx_bytes = s->tx_bytes;
|
|
|
|
|
rx_packets = s->rx_packets;
|
|
|
|
|
rx_bytes = s->rx_bytes;
|
|
|
|
|
} while (u64_stats_fetch_retry_irq(&s->syncp, start));
|
|
|
|
|
data[0] += tx_packets;
|
|
|
|
|
data[1] += tx_bytes;
|
|
|
|
|
data[2] += rx_packets;
|
|
|
|
|
data[3] += rx_bytes;
|
|
|
|
|
}
|
2016-08-24 00:38:56 +08:00
|
|
|
if (ds->ops->get_ethtool_stats)
|
2017-10-16 23:12:15 +08:00
|
|
|
ds->ops->get_ethtool_stats(ds, dp->index, data + 4);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_get_sset_count(struct net_device *dev, int sset)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
|
|
|
|
|
if (sset == ETH_SS_STATS) {
|
|
|
|
|
int count;
|
|
|
|
|
|
|
|
|
|
count = 4;
|
2016-08-24 00:38:56 +08:00
|
|
|
if (ds->ops->get_sset_count)
|
2018-04-26 03:12:50 +08:00
|
|
|
count += ds->ops->get_sset_count(ds, dp->index, sset);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
|
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-19 08:31:24 +08:00
|
|
|
static void dsa_slave_get_wol(struct net_device *dev, struct ethtool_wolinfo *w)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-09-19 08:31:24 +08:00
|
|
|
|
2018-05-11 04:17:36 +08:00
|
|
|
phylink_ethtool_get_wol(dp->pl, w);
|
|
|
|
|
|
2016-08-24 00:38:56 +08:00
|
|
|
if (ds->ops->get_wol)
|
2017-10-16 23:12:15 +08:00
|
|
|
ds->ops->get_wol(ds, dp->index, w);
|
2014-09-19 08:31:24 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_set_wol(struct net_device *dev, struct ethtool_wolinfo *w)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-09-19 08:31:24 +08:00
|
|
|
int ret = -EOPNOTSUPP;
|
|
|
|
|
|
2018-05-11 04:17:36 +08:00
|
|
|
phylink_ethtool_set_wol(dp->pl, w);
|
|
|
|
|
|
2016-08-24 00:38:56 +08:00
|
|
|
if (ds->ops->set_wol)
|
2017-10-16 23:12:15 +08:00
|
|
|
ret = ds->ops->set_wol(ds, dp->index, w);
|
2014-09-19 08:31:24 +08:00
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-25 08:05:21 +08:00
|
|
|
static int dsa_slave_set_eee(struct net_device *dev, struct ethtool_eee *e)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-09-25 08:05:21 +08:00
|
|
|
int ret;
|
|
|
|
|
|
2017-08-02 04:32:31 +08:00
|
|
|
/* Port's PHY and MAC both need to be EEE capable */
|
2019-02-06 23:35:15 +08:00
|
|
|
if (!dev->phydev || !dp->pl)
|
2017-08-02 04:32:31 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
2017-08-02 04:32:41 +08:00
|
|
|
if (!ds->ops->set_mac_eee)
|
2014-09-25 08:05:21 +08:00
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
2017-10-16 23:12:15 +08:00
|
|
|
ret = ds->ops->set_mac_eee(ds, dp->index, e);
|
2014-09-25 08:05:21 +08:00
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
2018-05-11 04:17:36 +08:00
|
|
|
return phylink_ethtool_set_eee(dp->pl, e);
|
2014-09-25 08:05:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_get_eee(struct net_device *dev, struct ethtool_eee *e)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-09-25 08:05:21 +08:00
|
|
|
int ret;
|
|
|
|
|
|
2017-08-02 04:32:31 +08:00
|
|
|
/* Port's PHY and MAC both need to be EEE capable */
|
2019-02-06 23:35:15 +08:00
|
|
|
if (!dev->phydev || !dp->pl)
|
2017-08-02 04:32:31 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
2017-08-02 04:32:41 +08:00
|
|
|
if (!ds->ops->get_mac_eee)
|
2014-09-25 08:05:21 +08:00
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
2017-10-16 23:12:15 +08:00
|
|
|
ret = ds->ops->get_mac_eee(ds, dp->index, e);
|
2014-09-25 08:05:21 +08:00
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
2018-05-11 04:17:36 +08:00
|
|
|
return phylink_ethtool_get_eee(dp->pl, e);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_get_link_ksettings(struct net_device *dev,
|
|
|
|
|
struct ethtool_link_ksettings *cmd)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
|
|
return phylink_ethtool_ksettings_get(dp->pl, cmd);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_set_link_ksettings(struct net_device *dev,
|
|
|
|
|
const struct ethtool_link_ksettings *cmd)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
|
|
return phylink_ethtool_ksettings_set(dp->pl, cmd);
|
2014-09-25 08:05:21 +08:00
|
|
|
}
|
|
|
|
|
|
2019-10-30 05:32:48 +08:00
|
|
|
static void dsa_slave_get_pauseparam(struct net_device *dev,
|
|
|
|
|
struct ethtool_pauseparam *pause)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
|
|
phylink_ethtool_get_pauseparam(dp->pl, pause);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_set_pauseparam(struct net_device *dev,
|
|
|
|
|
struct ethtool_pauseparam *pause)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
|
|
return phylink_ethtool_set_pauseparam(dp->pl, pause);
|
|
|
|
|
}
|
|
|
|
|
|
2015-08-01 02:42:57 +08:00
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
|
|
|
static int dsa_slave_netpoll_setup(struct net_device *dev,
|
|
|
|
|
struct netpoll_info *ni)
|
|
|
|
|
{
|
2017-10-16 23:12:16 +08:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2015-08-01 02:42:57 +08:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
|
struct netpoll *netpoll;
|
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
|
|
netpoll = kzalloc(sizeof(*netpoll), GFP_KERNEL);
|
|
|
|
|
if (!netpoll)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
err = __netpoll_setup(netpoll, master);
|
|
|
|
|
if (err) {
|
|
|
|
|
kfree(netpoll);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
p->netpoll = netpoll;
|
|
|
|
|
out:
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dsa_slave_netpoll_cleanup(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
|
struct netpoll *netpoll = p->netpoll;
|
|
|
|
|
|
|
|
|
|
if (!netpoll)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
p->netpoll = NULL;
|
|
|
|
|
|
2018-10-18 23:18:26 +08:00
|
|
|
__netpoll_free(netpoll);
|
2015-08-01 02:42:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dsa_slave_poll_controller(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2017-01-11 04:32:36 +08:00
|
|
|
static int dsa_slave_get_phys_port_name(struct net_device *dev,
|
|
|
|
|
char *name, size_t len)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2017-01-11 04:32:36 +08:00
|
|
|
|
2019-03-28 20:56:44 +08:00
|
|
|
/* For non-legacy ports, devlink is used and it takes
|
|
|
|
|
* care of the name generation. This ndo implementation
|
|
|
|
|
* should be removed with legacy support.
|
|
|
|
|
*/
|
|
|
|
|
if (dp->ds->devlink)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
2017-10-16 23:12:15 +08:00
|
|
|
if (snprintf(name, len, "p%d", dp->index) >= len)
|
2017-01-11 04:32:36 +08:00
|
|
|
return -EINVAL;
|
2016-12-30 06:20:56 +08:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 04:41:40 +08:00
|
|
|
static struct dsa_mall_tc_entry *
|
2017-09-21 07:31:57 +08:00
|
|
|
dsa_slave_mall_tc_entry_find(struct net_device *dev, unsigned long cookie)
|
2017-01-31 04:41:40 +08:00
|
|
|
{
|
2017-09-21 07:31:57 +08:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
2017-01-31 04:41:40 +08:00
|
|
|
struct dsa_mall_tc_entry *mall_tc_entry;
|
|
|
|
|
|
|
|
|
|
list_for_each_entry(mall_tc_entry, &p->mall_tc_list, list)
|
|
|
|
|
if (mall_tc_entry->cookie == cookie)
|
|
|
|
|
return mall_tc_entry;
|
|
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2020-03-29 19:51:58 +08:00
|
|
|
static int
|
|
|
|
|
dsa_slave_add_cls_matchall_mirred(struct net_device *dev,
|
|
|
|
|
struct tc_cls_matchall_offload *cls,
|
|
|
|
|
bool ingress)
|
2017-01-31 04:41:40 +08:00
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2017-01-31 04:41:40 +08:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
2020-03-29 19:51:58 +08:00
|
|
|
struct dsa_mall_mirror_tc_entry *mirror;
|
2017-01-31 04:41:40 +08:00
|
|
|
struct dsa_mall_tc_entry *mall_tc_entry;
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_switch *ds = dp->ds;
|
2019-05-04 19:46:19 +08:00
|
|
|
struct flow_action_entry *act;
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *to_dp;
|
2020-03-29 19:51:58 +08:00
|
|
|
int err;
|
|
|
|
|
|
2017-01-31 04:41:40 +08:00
|
|
|
if (!ds->ops->port_mirror_add)
|
2020-03-29 19:51:59 +08:00
|
|
|
return -EOPNOTSUPP;
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2020-03-17 09:42:11 +08:00
|
|
|
if (!flow_action_basic_hw_stats_check(&cls->rule->action,
|
|
|
|
|
cls->common.extack))
|
2020-03-29 19:51:59 +08:00
|
|
|
return -EOPNOTSUPP;
|
2020-03-07 19:40:13 +08:00
|
|
|
|
2019-05-04 19:46:19 +08:00
|
|
|
act = &cls->rule->action.entries[0];
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2020-05-05 03:58:56 +08:00
|
|
|
if (!act->dev)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
2020-03-29 19:51:58 +08:00
|
|
|
if (!dsa_slave_dev_check(act->dev))
|
|
|
|
|
return -EOPNOTSUPP;
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2020-03-29 19:51:58 +08:00
|
|
|
mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
|
|
|
|
|
if (!mall_tc_entry)
|
|
|
|
|
return -ENOMEM;
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2020-03-29 19:51:58 +08:00
|
|
|
mall_tc_entry->cookie = cls->cookie;
|
|
|
|
|
mall_tc_entry->type = DSA_PORT_MALL_MIRROR;
|
|
|
|
|
mirror = &mall_tc_entry->mirror;
|
|
|
|
|
|
|
|
|
|
to_dp = dsa_slave_to_port(act->dev);
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2020-03-29 19:51:58 +08:00
|
|
|
mirror->to_local_port = to_dp->index;
|
|
|
|
|
mirror->ingress = ingress;
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2020-03-29 19:51:58 +08:00
|
|
|
err = ds->ops->port_mirror_add(ds, dp->index, mirror, ingress);
|
|
|
|
|
if (err) {
|
|
|
|
|
kfree(mall_tc_entry);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2020-03-29 19:51:58 +08:00
|
|
|
list_add_tail(&mall_tc_entry->list, &p->mall_tc_list);
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2020-03-29 19:51:58 +08:00
|
|
|
return err;
|
|
|
|
|
}
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2020-03-29 19:51:59 +08:00
|
|
|
static int
|
|
|
|
|
dsa_slave_add_cls_matchall_police(struct net_device *dev,
|
|
|
|
|
struct tc_cls_matchall_offload *cls,
|
|
|
|
|
bool ingress)
|
|
|
|
|
{
|
|
|
|
|
struct netlink_ext_ack *extack = cls->common.extack;
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
|
struct dsa_mall_policer_tc_entry *policer;
|
|
|
|
|
struct dsa_mall_tc_entry *mall_tc_entry;
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
|
|
|
|
struct flow_action_entry *act;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (!ds->ops->port_policer_add) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack,
|
2020-05-07 08:58:27 +08:00
|
|
|
"Policing offload not implemented");
|
2020-03-29 19:51:59 +08:00
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!ingress) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack,
|
2020-05-07 08:58:27 +08:00
|
|
|
"Only supported on ingress qdisc");
|
2020-03-29 19:51:59 +08:00
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!flow_action_basic_hw_stats_check(&cls->rule->action,
|
|
|
|
|
cls->common.extack))
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
|
|
|
|
list_for_each_entry(mall_tc_entry, &p->mall_tc_list, list) {
|
|
|
|
|
if (mall_tc_entry->type == DSA_PORT_MALL_POLICER) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack,
|
2020-05-07 08:58:27 +08:00
|
|
|
"Only one port policer allowed");
|
2020-03-29 19:51:59 +08:00
|
|
|
return -EEXIST;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
act = &cls->rule->action.entries[0];
|
|
|
|
|
|
|
|
|
|
mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
|
|
|
|
|
if (!mall_tc_entry)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
mall_tc_entry->cookie = cls->cookie;
|
|
|
|
|
mall_tc_entry->type = DSA_PORT_MALL_POLICER;
|
|
|
|
|
policer = &mall_tc_entry->policer;
|
|
|
|
|
policer->rate_bytes_per_sec = act->police.rate_bytes_ps;
|
|
|
|
|
policer->burst = act->police.burst;
|
|
|
|
|
|
|
|
|
|
err = ds->ops->port_policer_add(ds, dp->index, policer);
|
|
|
|
|
if (err) {
|
|
|
|
|
kfree(mall_tc_entry);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
list_add_tail(&mall_tc_entry->list, &p->mall_tc_list);
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2020-03-29 19:51:58 +08:00
|
|
|
static int dsa_slave_add_cls_matchall(struct net_device *dev,
|
|
|
|
|
struct tc_cls_matchall_offload *cls,
|
|
|
|
|
bool ingress)
|
|
|
|
|
{
|
|
|
|
|
int err = -EOPNOTSUPP;
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2020-03-29 19:51:58 +08:00
|
|
|
if (cls->common.protocol == htons(ETH_P_ALL) &&
|
|
|
|
|
flow_offload_has_one_action(&cls->rule->action) &&
|
|
|
|
|
cls->rule->action.entries[0].id == FLOW_ACTION_MIRRED)
|
|
|
|
|
err = dsa_slave_add_cls_matchall_mirred(dev, cls, ingress);
|
2020-03-29 19:51:59 +08:00
|
|
|
else if (flow_offload_has_one_action(&cls->rule->action) &&
|
|
|
|
|
cls->rule->action.entries[0].id == FLOW_ACTION_POLICE)
|
|
|
|
|
err = dsa_slave_add_cls_matchall_police(dev, cls, ingress);
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2020-03-29 19:51:58 +08:00
|
|
|
return err;
|
2017-01-31 04:41:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dsa_slave_del_cls_matchall(struct net_device *dev,
|
|
|
|
|
struct tc_cls_matchall_offload *cls)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2017-01-31 04:41:40 +08:00
|
|
|
struct dsa_mall_tc_entry *mall_tc_entry;
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_switch *ds = dp->ds;
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2017-09-21 07:31:57 +08:00
|
|
|
mall_tc_entry = dsa_slave_mall_tc_entry_find(dev, cls->cookie);
|
2017-01-31 04:41:40 +08:00
|
|
|
if (!mall_tc_entry)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
list_del(&mall_tc_entry->list);
|
|
|
|
|
|
|
|
|
|
switch (mall_tc_entry->type) {
|
|
|
|
|
case DSA_PORT_MALL_MIRROR:
|
2020-03-29 19:51:59 +08:00
|
|
|
if (ds->ops->port_mirror_del)
|
|
|
|
|
ds->ops->port_mirror_del(ds, dp->index,
|
|
|
|
|
&mall_tc_entry->mirror);
|
|
|
|
|
break;
|
|
|
|
|
case DSA_PORT_MALL_POLICER:
|
|
|
|
|
if (ds->ops->port_policer_del)
|
|
|
|
|
ds->ops->port_policer_del(ds, dp->index);
|
2017-01-31 04:41:40 +08:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
WARN_ON(1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
kfree(mall_tc_entry);
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-07 16:15:26 +08:00
|
|
|
static int dsa_slave_setup_tc_cls_matchall(struct net_device *dev,
|
2017-10-19 21:50:45 +08:00
|
|
|
struct tc_cls_matchall_offload *cls,
|
|
|
|
|
bool ingress)
|
2017-01-31 04:41:40 +08:00
|
|
|
{
|
2017-08-07 16:15:29 +08:00
|
|
|
if (cls->common.chain_index)
|
2017-06-06 23:00:16 +08:00
|
|
|
return -EOPNOTSUPP;
|
2017-01-31 04:41:40 +08:00
|
|
|
|
2017-08-07 16:15:26 +08:00
|
|
|
switch (cls->command) {
|
|
|
|
|
case TC_CLSMATCHALL_REPLACE:
|
2017-08-07 16:15:29 +08:00
|
|
|
return dsa_slave_add_cls_matchall(dev, cls, ingress);
|
2017-08-07 16:15:26 +08:00
|
|
|
case TC_CLSMATCHALL_DESTROY:
|
|
|
|
|
dsa_slave_del_cls_matchall(dev, cls);
|
|
|
|
|
return 0;
|
|
|
|
|
default:
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-02-29 22:31:13 +08:00
|
|
|
static int dsa_slave_add_cls_flower(struct net_device *dev,
|
|
|
|
|
struct flow_cls_offload *cls,
|
|
|
|
|
bool ingress)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
|
|
|
|
int port = dp->index;
|
|
|
|
|
|
|
|
|
|
if (!ds->ops->cls_flower_add)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
|
|
|
|
return ds->ops->cls_flower_add(ds, port, cls, ingress);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_del_cls_flower(struct net_device *dev,
|
|
|
|
|
struct flow_cls_offload *cls,
|
|
|
|
|
bool ingress)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
|
|
|
|
int port = dp->index;
|
|
|
|
|
|
|
|
|
|
if (!ds->ops->cls_flower_del)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
|
|
|
|
return ds->ops->cls_flower_del(ds, port, cls, ingress);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_stats_cls_flower(struct net_device *dev,
|
|
|
|
|
struct flow_cls_offload *cls,
|
|
|
|
|
bool ingress)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
|
|
|
|
int port = dp->index;
|
|
|
|
|
|
|
|
|
|
if (!ds->ops->cls_flower_stats)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
|
|
|
|
return ds->ops->cls_flower_stats(ds, port, cls, ingress);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_setup_tc_cls_flower(struct net_device *dev,
|
|
|
|
|
struct flow_cls_offload *cls,
|
|
|
|
|
bool ingress)
|
|
|
|
|
{
|
|
|
|
|
switch (cls->command) {
|
|
|
|
|
case FLOW_CLS_REPLACE:
|
|
|
|
|
return dsa_slave_add_cls_flower(dev, cls, ingress);
|
|
|
|
|
case FLOW_CLS_DESTROY:
|
|
|
|
|
return dsa_slave_del_cls_flower(dev, cls, ingress);
|
|
|
|
|
case FLOW_CLS_STATS:
|
|
|
|
|
return dsa_slave_stats_cls_flower(dev, cls, ingress);
|
|
|
|
|
default:
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-10-19 21:50:45 +08:00
|
|
|
static int dsa_slave_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
|
|
|
|
|
void *cb_priv, bool ingress)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *dev = cb_priv;
|
|
|
|
|
|
2017-11-01 18:47:39 +08:00
|
|
|
if (!tc_can_offload(dev))
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
2017-10-19 21:50:45 +08:00
|
|
|
switch (type) {
|
|
|
|
|
case TC_SETUP_CLSMATCHALL:
|
|
|
|
|
return dsa_slave_setup_tc_cls_matchall(dev, type_data, ingress);
|
2020-02-29 22:31:13 +08:00
|
|
|
case TC_SETUP_CLSFLOWER:
|
|
|
|
|
return dsa_slave_setup_tc_cls_flower(dev, type_data, ingress);
|
2017-10-19 21:50:45 +08:00
|
|
|
default:
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_setup_tc_block_cb_ig(enum tc_setup_type type,
|
|
|
|
|
void *type_data, void *cb_priv)
|
|
|
|
|
{
|
|
|
|
|
return dsa_slave_setup_tc_block_cb(type, type_data, cb_priv, true);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_setup_tc_block_cb_eg(enum tc_setup_type type,
|
|
|
|
|
void *type_data, void *cb_priv)
|
|
|
|
|
{
|
|
|
|
|
return dsa_slave_setup_tc_block_cb(type, type_data, cb_priv, false);
|
|
|
|
|
}
|
|
|
|
|
|
2019-07-10 04:55:46 +08:00
|
|
|
static LIST_HEAD(dsa_slave_block_cb_list);
|
|
|
|
|
|
2017-10-19 21:50:45 +08:00
|
|
|
static int dsa_slave_setup_tc_block(struct net_device *dev,
|
2019-07-10 04:55:46 +08:00
|
|
|
struct flow_block_offload *f)
|
2017-10-19 21:50:45 +08:00
|
|
|
{
|
2019-07-10 04:55:46 +08:00
|
|
|
struct flow_block_cb *block_cb;
|
2019-07-20 00:20:15 +08:00
|
|
|
flow_setup_cb_t *cb;
|
2017-10-19 21:50:45 +08:00
|
|
|
|
2019-07-10 04:55:41 +08:00
|
|
|
if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
|
2017-10-19 21:50:45 +08:00
|
|
|
cb = dsa_slave_setup_tc_block_cb_ig;
|
2019-07-10 04:55:41 +08:00
|
|
|
else if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS)
|
2017-10-19 21:50:45 +08:00
|
|
|
cb = dsa_slave_setup_tc_block_cb_eg;
|
|
|
|
|
else
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
2019-07-10 04:55:46 +08:00
|
|
|
f->driver_block_list = &dsa_slave_block_cb_list;
|
|
|
|
|
|
2017-10-19 21:50:45 +08:00
|
|
|
switch (f->command) {
|
2019-07-10 04:55:40 +08:00
|
|
|
case FLOW_BLOCK_BIND:
|
2019-07-10 04:55:48 +08:00
|
|
|
if (flow_block_cb_is_busy(cb, dev, &dsa_slave_block_cb_list))
|
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
2019-07-20 00:20:14 +08:00
|
|
|
block_cb = flow_block_cb_alloc(cb, dev, dev, NULL);
|
2019-07-10 04:55:46 +08:00
|
|
|
if (IS_ERR(block_cb))
|
|
|
|
|
return PTR_ERR(block_cb);
|
|
|
|
|
|
|
|
|
|
flow_block_cb_add(block_cb, f);
|
|
|
|
|
list_add_tail(&block_cb->driver_list, &dsa_slave_block_cb_list);
|
|
|
|
|
return 0;
|
2019-07-10 04:55:40 +08:00
|
|
|
case FLOW_BLOCK_UNBIND:
|
2019-07-20 00:20:16 +08:00
|
|
|
block_cb = flow_block_cb_lookup(f->block, cb, dev);
|
2019-07-10 04:55:46 +08:00
|
|
|
if (!block_cb)
|
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
|
|
flow_block_cb_remove(block_cb, f);
|
|
|
|
|
list_del(&block_cb->driver_list);
|
2017-10-19 21:50:45 +08:00
|
|
|
return 0;
|
|
|
|
|
default:
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-07 16:15:26 +08:00
|
|
|
static int dsa_slave_setup_tc(struct net_device *dev, enum tc_setup_type type,
|
2017-08-07 16:15:32 +08:00
|
|
|
void *type_data)
|
2017-08-07 16:15:26 +08:00
|
|
|
{
|
2019-09-15 09:59:59 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
|
|
|
|
|
|
|
|
|
if (type == TC_SETUP_BLOCK)
|
2017-10-19 21:50:45 +08:00
|
|
|
return dsa_slave_setup_tc_block(dev, type_data);
|
2019-09-15 09:59:59 +08:00
|
|
|
|
|
|
|
|
if (!ds->ops->port_setup_tc)
|
2017-06-06 23:00:16 +08:00
|
|
|
return -EOPNOTSUPP;
|
2019-09-15 09:59:59 +08:00
|
|
|
|
|
|
|
|
return ds->ops->port_setup_tc(ds, dp->index, type, type_data);
|
2017-01-31 04:41:40 +08:00
|
|
|
}
|
|
|
|
|
|
2017-01-31 01:48:40 +08:00
|
|
|
static int dsa_slave_get_rxnfc(struct net_device *dev,
|
|
|
|
|
struct ethtool_rxnfc *nfc, u32 *rule_locs)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2017-01-31 01:48:40 +08:00
|
|
|
|
|
|
|
|
if (!ds->ops->get_rxnfc)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
2017-10-16 23:12:15 +08:00
|
|
|
return ds->ops->get_rxnfc(ds, dp->index, nfc, rule_locs);
|
2017-01-31 01:48:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_set_rxnfc(struct net_device *dev,
|
|
|
|
|
struct ethtool_rxnfc *nfc)
|
|
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2017-01-31 01:48:40 +08:00
|
|
|
|
|
|
|
|
if (!ds->ops->set_rxnfc)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
2017-10-16 23:12:15 +08:00
|
|
|
return ds->ops->set_rxnfc(ds, dp->index, nfc);
|
2017-01-31 01:48:40 +08:00
|
|
|
}
|
|
|
|
|
|
2018-02-14 08:07:48 +08:00
|
|
|
static int dsa_slave_get_ts_info(struct net_device *dev,
|
|
|
|
|
struct ethtool_ts_info *ts)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
|
struct dsa_switch *ds = p->dp->ds;
|
|
|
|
|
|
|
|
|
|
if (!ds->ops->get_ts_info)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
|
|
|
|
return ds->ops->get_ts_info(ds, p->dp->index, ts);
|
|
|
|
|
}
|
|
|
|
|
|
2019-02-21 06:35:39 +08:00
|
|
|
static int dsa_slave_vlan_rx_add_vid(struct net_device *dev, __be16 proto,
|
|
|
|
|
u16 vid)
|
|
|
|
|
{
|
2020-09-21 08:10:29 +08:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2019-02-21 06:35:39 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2020-09-11 00:48:57 +08:00
|
|
|
struct switchdev_obj_port_vlan vlan = {
|
|
|
|
|
.obj.id = SWITCHDEV_OBJ_ID_PORT_VLAN,
|
|
|
|
|
.vid_begin = vid,
|
|
|
|
|
.vid_end = vid,
|
|
|
|
|
/* This API only allows programming tagged, non-PVID VIDs */
|
|
|
|
|
.flags = 0,
|
|
|
|
|
};
|
|
|
|
|
struct switchdev_trans trans;
|
2019-02-21 06:35:39 +08:00
|
|
|
int ret;
|
|
|
|
|
|
2020-09-11 00:48:57 +08:00
|
|
|
/* User port... */
|
|
|
|
|
trans.ph_prepare = true;
|
|
|
|
|
ret = dsa_port_vlan_add(dp, &vlan, &trans);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
trans.ph_prepare = false;
|
|
|
|
|
ret = dsa_port_vlan_add(dp, &vlan, &trans);
|
2019-08-26 03:46:29 +08:00
|
|
|
if (ret)
|
2019-08-26 01:25:16 +08:00
|
|
|
return ret;
|
|
|
|
|
|
2020-09-11 00:48:57 +08:00
|
|
|
/* And CPU port... */
|
|
|
|
|
trans.ph_prepare = true;
|
|
|
|
|
ret = dsa_port_vlan_add(dp->cpu_dp, &vlan, &trans);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
trans.ph_prepare = false;
|
|
|
|
|
ret = dsa_port_vlan_add(dp->cpu_dp, &vlan, &trans);
|
2019-08-26 03:46:29 +08:00
|
|
|
if (ret)
|
2019-08-26 01:25:19 +08:00
|
|
|
return ret;
|
|
|
|
|
|
2020-09-21 08:10:29 +08:00
|
|
|
return vlan_vid_add(master, proto, vid);
|
2019-02-21 06:35:39 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dsa_slave_vlan_rx_kill_vid(struct net_device *dev, __be16 proto,
|
|
|
|
|
u16 vid)
|
|
|
|
|
{
|
2020-09-21 08:10:29 +08:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2019-02-21 06:35:39 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2020-09-11 00:48:57 +08:00
|
|
|
struct switchdev_obj_port_vlan vlan = {
|
|
|
|
|
.vid_begin = vid,
|
|
|
|
|
.vid_end = vid,
|
|
|
|
|
/* This API only allows programming tagged, non-PVID VIDs */
|
|
|
|
|
.flags = 0,
|
|
|
|
|
};
|
2020-09-21 08:10:29 +08:00
|
|
|
int err;
|
2019-02-21 06:35:39 +08:00
|
|
|
|
2019-08-26 01:25:19 +08:00
|
|
|
/* Do not deprogram the CPU port as it may be shared with other user
|
|
|
|
|
* ports which can be members of this VLAN as well.
|
|
|
|
|
*/
|
2020-09-21 08:10:29 +08:00
|
|
|
err = dsa_port_vlan_del(dp, &vlan);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
vlan_vid_del(master, proto, vid);
|
|
|
|
|
|
|
|
|
|
return 0;
|
2019-02-21 06:35:39 +08:00
|
|
|
}
|
|
|
|
|
|
net: dsa: implement auto-normalization of MTU for bridge hardware datapath
Many switches don't have an explicit knob for configuring the MTU
(maximum transmission unit per interface). Instead, they do the
length-based packet admission checks on the ingress interface, for
reasons that are easy to understand (why would you accept a packet in
the queuing subsystem if you know you're going to drop it anyway).
So it is actually the MRU that these switches permit configuring.
In Linux there only exists the IFLA_MTU netlink attribute and the
associated dev_set_mtu function. The comments like to play blind and say
that it's changing the "maximum transfer unit", which is to say that
there isn't any directionality in the meaning of the MTU word. So that
is the interpretation that this patch is giving to things: MTU == MRU.
When 2 interfaces having different MTUs are bridged, the bridge driver
MTU auto-adjustment logic kicks in: what br_mtu_auto_adjust() does is it
adjusts the MTU of the bridge net device itself (and not that of the
slave net devices) to the minimum value of all slave interfaces, in
order for forwarded packets to not exceed the MTU regardless of the
interface they are received and send on.
The idea behind this behavior, and why the slave MTUs are not adjusted,
is that normal termination from Linux over the L2 forwarding domain
should happen over the bridge net device, which _is_ properly limited by
the minimum MTU. And termination over individual slave devices is
possible even if those are bridged. But that is not "forwarding", so
there's no reason to do normalization there, since only a single
interface sees that packet.
The problem with those switches that can only control the MRU is with
the offloaded data path, where a packet received on an interface with
MRU 9000 would still be forwarded to an interface with MRU 1500. And the
br_mtu_auto_adjust() function does not really help, since the MTU
configured on the bridge net device is ignored.
In order to enforce the de-facto MTU == MRU rule for these switches, we
need to do MTU normalization, which means: in order for no packet larger
than the MTU configured on this port to be sent, then we need to limit
the MRU on all ports that this packet could possibly come from. AKA
since we are configuring the MRU via MTU, it means that all ports within
a bridge forwarding domain should have the same MTU.
And that is exactly what this patch is trying to do.
>From an implementation perspective, we try to follow the intent of the
user, otherwise there is a risk that we might livelock them (they try to
change the MTU on an already-bridged interface, but we just keep
changing it back in an attempt to keep the MTU normalized). So the MTU
that the bridge is normalized to is either:
- The most recently changed one:
ip link set dev swp0 master br0
ip link set dev swp1 master br0
ip link set dev swp0 mtu 1400
This sequence will make swp1 inherit MTU 1400 from swp0.
- The one of the most recently added interface to the bridge:
ip link set dev swp0 master br0
ip link set dev swp1 mtu 1400
ip link set dev swp1 master br0
The above sequence will make swp0 inherit MTU 1400 as well.
Suggested-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-28 03:55:43 +08:00
|
|
|
struct dsa_hw_port {
|
|
|
|
|
struct list_head list;
|
|
|
|
|
struct net_device *dev;
|
|
|
|
|
int old_mtu;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int dsa_hw_port_list_set_mtu(struct list_head *hw_port_list, int mtu)
|
|
|
|
|
{
|
|
|
|
|
const struct dsa_hw_port *p;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
list_for_each_entry(p, hw_port_list, list) {
|
|
|
|
|
if (p->dev->mtu == mtu)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
err = dev_set_mtu(p->dev, mtu);
|
|
|
|
|
if (err)
|
|
|
|
|
goto rollback;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
rollback:
|
|
|
|
|
list_for_each_entry_continue_reverse(p, hw_port_list, list) {
|
|
|
|
|
if (p->dev->mtu == p->old_mtu)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (dev_set_mtu(p->dev, p->old_mtu))
|
|
|
|
|
netdev_err(p->dev, "Failed to restore MTU\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dsa_hw_port_list_free(struct list_head *hw_port_list)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_hw_port *p, *n;
|
|
|
|
|
|
|
|
|
|
list_for_each_entry_safe(p, n, hw_port_list, list)
|
|
|
|
|
kfree(p);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Make the hardware datapath to/from @dev limited to a common MTU */
|
2020-04-02 09:25:48 +08:00
|
|
|
static void dsa_bridge_mtu_normalization(struct dsa_port *dp)
|
net: dsa: implement auto-normalization of MTU for bridge hardware datapath
Many switches don't have an explicit knob for configuring the MTU
(maximum transmission unit per interface). Instead, they do the
length-based packet admission checks on the ingress interface, for
reasons that are easy to understand (why would you accept a packet in
the queuing subsystem if you know you're going to drop it anyway).
So it is actually the MRU that these switches permit configuring.
In Linux there only exists the IFLA_MTU netlink attribute and the
associated dev_set_mtu function. The comments like to play blind and say
that it's changing the "maximum transfer unit", which is to say that
there isn't any directionality in the meaning of the MTU word. So that
is the interpretation that this patch is giving to things: MTU == MRU.
When 2 interfaces having different MTUs are bridged, the bridge driver
MTU auto-adjustment logic kicks in: what br_mtu_auto_adjust() does is it
adjusts the MTU of the bridge net device itself (and not that of the
slave net devices) to the minimum value of all slave interfaces, in
order for forwarded packets to not exceed the MTU regardless of the
interface they are received and send on.
The idea behind this behavior, and why the slave MTUs are not adjusted,
is that normal termination from Linux over the L2 forwarding domain
should happen over the bridge net device, which _is_ properly limited by
the minimum MTU. And termination over individual slave devices is
possible even if those are bridged. But that is not "forwarding", so
there's no reason to do normalization there, since only a single
interface sees that packet.
The problem with those switches that can only control the MRU is with
the offloaded data path, where a packet received on an interface with
MRU 9000 would still be forwarded to an interface with MRU 1500. And the
br_mtu_auto_adjust() function does not really help, since the MTU
configured on the bridge net device is ignored.
In order to enforce the de-facto MTU == MRU rule for these switches, we
need to do MTU normalization, which means: in order for no packet larger
than the MTU configured on this port to be sent, then we need to limit
the MRU on all ports that this packet could possibly come from. AKA
since we are configuring the MRU via MTU, it means that all ports within
a bridge forwarding domain should have the same MTU.
And that is exactly what this patch is trying to do.
>From an implementation perspective, we try to follow the intent of the
user, otherwise there is a risk that we might livelock them (they try to
change the MTU on an already-bridged interface, but we just keep
changing it back in an attempt to keep the MTU normalized). So the MTU
that the bridge is normalized to is either:
- The most recently changed one:
ip link set dev swp0 master br0
ip link set dev swp1 master br0
ip link set dev swp0 mtu 1400
This sequence will make swp1 inherit MTU 1400 from swp0.
- The one of the most recently added interface to the bridge:
ip link set dev swp0 master br0
ip link set dev swp1 mtu 1400
ip link set dev swp1 master br0
The above sequence will make swp0 inherit MTU 1400 as well.
Suggested-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-28 03:55:43 +08:00
|
|
|
{
|
|
|
|
|
struct list_head hw_port_list;
|
|
|
|
|
struct dsa_switch_tree *dst;
|
|
|
|
|
int min_mtu = ETH_MAX_MTU;
|
|
|
|
|
struct dsa_port *other_dp;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (!dp->ds->mtu_enforcement_ingress)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
if (!dp->bridge_dev)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&hw_port_list);
|
|
|
|
|
|
|
|
|
|
/* Populate the list of ports that are part of the same bridge
|
|
|
|
|
* as the newly added/modified port
|
|
|
|
|
*/
|
|
|
|
|
list_for_each_entry(dst, &dsa_tree_list, list) {
|
|
|
|
|
list_for_each_entry(other_dp, &dst->ports, list) {
|
|
|
|
|
struct dsa_hw_port *hw_port;
|
|
|
|
|
struct net_device *slave;
|
|
|
|
|
|
|
|
|
|
if (other_dp->type != DSA_PORT_TYPE_USER)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (other_dp->bridge_dev != dp->bridge_dev)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (!other_dp->ds->mtu_enforcement_ingress)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
slave = other_dp->slave;
|
|
|
|
|
|
|
|
|
|
if (min_mtu > slave->mtu)
|
|
|
|
|
min_mtu = slave->mtu;
|
|
|
|
|
|
|
|
|
|
hw_port = kzalloc(sizeof(*hw_port), GFP_KERNEL);
|
|
|
|
|
if (!hw_port)
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
hw_port->dev = slave;
|
|
|
|
|
hw_port->old_mtu = slave->mtu;
|
|
|
|
|
|
|
|
|
|
list_add(&hw_port->list, &hw_port_list);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Attempt to configure the entire hardware bridge to the newly added
|
|
|
|
|
* interface's MTU first, regardless of whether the intention of the
|
|
|
|
|
* user was to raise or lower it.
|
|
|
|
|
*/
|
|
|
|
|
err = dsa_hw_port_list_set_mtu(&hw_port_list, dp->slave->mtu);
|
|
|
|
|
if (!err)
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
/* Clearly that didn't work out so well, so just set the minimum MTU on
|
|
|
|
|
* all hardware bridge ports now. If this fails too, then all ports will
|
|
|
|
|
* still have their old MTU rolled back anyway.
|
|
|
|
|
*/
|
|
|
|
|
dsa_hw_port_list_set_mtu(&hw_port_list, min_mtu);
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
dsa_hw_port_list_free(&hw_port_list);
|
|
|
|
|
}
|
|
|
|
|
|
net: dsa: configure the MTU for switch ports
It is useful be able to configure port policers on a switch to accept
frames of various sizes:
- Increase the MTU for better throughput from the default of 1500 if it
is known that there is no 10/100 Mbps device in the network.
- Decrease the MTU to limit the latency of high-priority frames under
congestion, or work around various network segments that add extra
headers to packets which can't be fragmented.
For DSA slave ports, this is mostly a pass-through callback, called
through the regular ndo ops and at probe time (to ensure consistency
across all supported switches).
The CPU port is called with an MTU equal to the largest configured MTU
of the slave ports. The assumption is that the user might want to
sustain a bidirectional conversation with a partner over any switch
port.
The DSA master is configured the same as the CPU port, plus the tagger
overhead. Since the MTU is by definition L2 payload (sans Ethernet
header), it is up to each individual driver to figure out if it needs to
do anything special for its frame tags on the CPU port (it shouldn't
except in special cases). So the MTU does not contain the tagger
overhead on the CPU port.
However the MTU of the DSA master, minus the tagger overhead, is used as
a proxy for the MTU of the CPU port, which does not have a net device.
This is to avoid uselessly calling the .change_mtu function on the CPU
port when nothing should change.
So it is safe to assume that the DSA master and the CPU port MTUs are
apart by exactly the tagger's overhead in bytes.
Some changes were made around dsa_master_set_mtu(), function which was
now removed, for 2 reasons:
- dev_set_mtu() already calls dev_validate_mtu(), so it's redundant to
do the same thing in DSA
- __dev_set_mtu() returns 0 if ops->ndo_change_mtu is an absent method
That is to say, there's no need for this function in DSA, we can safely
call dev_set_mtu() directly, take the rtnl lock when necessary, and just
propagate whatever errors get reported (since the user probably wants to
be informed).
Some inspiration (mainly in the MTU DSA notifier) was taken from a
vaguely similar patch from Murali and Florian, who are credited as
co-developers down below.
Co-developed-by: Murali Krishna Policharla <murali.policharla@broadcom.com>
Signed-off-by: Murali Krishna Policharla <murali.policharla@broadcom.com>
Co-developed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-28 03:55:42 +08:00
|
|
|
static int dsa_slave_change_mtu(struct net_device *dev, int new_mtu)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
|
struct dsa_switch *ds = p->dp->ds;
|
|
|
|
|
struct dsa_port *cpu_dp;
|
|
|
|
|
int port = p->dp->index;
|
|
|
|
|
int largest_mtu = 0;
|
|
|
|
|
int new_master_mtu;
|
|
|
|
|
int old_master_mtu;
|
|
|
|
|
int mtu_limit;
|
|
|
|
|
int cpu_mtu;
|
|
|
|
|
int err, i;
|
|
|
|
|
|
|
|
|
|
if (!ds->ops->port_change_mtu)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ds->num_ports; i++) {
|
|
|
|
|
int slave_mtu;
|
|
|
|
|
|
|
|
|
|
if (!dsa_is_user_port(ds, i))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
/* During probe, this function will be called for each slave
|
|
|
|
|
* device, while not all of them have been allocated. That's
|
|
|
|
|
* ok, it doesn't change what the maximum is, so ignore it.
|
|
|
|
|
*/
|
|
|
|
|
if (!dsa_to_port(ds, i)->slave)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
/* Pretend that we already applied the setting, which we
|
|
|
|
|
* actually haven't (still haven't done all integrity checks)
|
|
|
|
|
*/
|
|
|
|
|
if (i == port)
|
|
|
|
|
slave_mtu = new_mtu;
|
|
|
|
|
else
|
|
|
|
|
slave_mtu = dsa_to_port(ds, i)->slave->mtu;
|
|
|
|
|
|
|
|
|
|
if (largest_mtu < slave_mtu)
|
|
|
|
|
largest_mtu = slave_mtu;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
cpu_dp = dsa_to_port(ds, port)->cpu_dp;
|
|
|
|
|
|
|
|
|
|
mtu_limit = min_t(int, master->max_mtu, dev->max_mtu);
|
|
|
|
|
old_master_mtu = master->mtu;
|
|
|
|
|
new_master_mtu = largest_mtu + cpu_dp->tag_ops->overhead;
|
|
|
|
|
if (new_master_mtu > mtu_limit)
|
|
|
|
|
return -ERANGE;
|
|
|
|
|
|
|
|
|
|
/* If the master MTU isn't over limit, there's no need to check the CPU
|
|
|
|
|
* MTU, since that surely isn't either.
|
|
|
|
|
*/
|
|
|
|
|
cpu_mtu = largest_mtu;
|
|
|
|
|
|
|
|
|
|
/* Start applying stuff */
|
|
|
|
|
if (new_master_mtu != old_master_mtu) {
|
|
|
|
|
err = dev_set_mtu(master, new_master_mtu);
|
|
|
|
|
if (err < 0)
|
|
|
|
|
goto out_master_failed;
|
|
|
|
|
|
|
|
|
|
/* We only need to propagate the MTU of the CPU port to
|
|
|
|
|
* upstream switches.
|
|
|
|
|
*/
|
|
|
|
|
err = dsa_port_mtu_change(cpu_dp, cpu_mtu, true);
|
|
|
|
|
if (err)
|
|
|
|
|
goto out_cpu_failed;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
err = dsa_port_mtu_change(dp, new_mtu, false);
|
|
|
|
|
if (err)
|
|
|
|
|
goto out_port_failed;
|
|
|
|
|
|
|
|
|
|
dev->mtu = new_mtu;
|
|
|
|
|
|
net: dsa: implement auto-normalization of MTU for bridge hardware datapath
Many switches don't have an explicit knob for configuring the MTU
(maximum transmission unit per interface). Instead, they do the
length-based packet admission checks on the ingress interface, for
reasons that are easy to understand (why would you accept a packet in
the queuing subsystem if you know you're going to drop it anyway).
So it is actually the MRU that these switches permit configuring.
In Linux there only exists the IFLA_MTU netlink attribute and the
associated dev_set_mtu function. The comments like to play blind and say
that it's changing the "maximum transfer unit", which is to say that
there isn't any directionality in the meaning of the MTU word. So that
is the interpretation that this patch is giving to things: MTU == MRU.
When 2 interfaces having different MTUs are bridged, the bridge driver
MTU auto-adjustment logic kicks in: what br_mtu_auto_adjust() does is it
adjusts the MTU of the bridge net device itself (and not that of the
slave net devices) to the minimum value of all slave interfaces, in
order for forwarded packets to not exceed the MTU regardless of the
interface they are received and send on.
The idea behind this behavior, and why the slave MTUs are not adjusted,
is that normal termination from Linux over the L2 forwarding domain
should happen over the bridge net device, which _is_ properly limited by
the minimum MTU. And termination over individual slave devices is
possible even if those are bridged. But that is not "forwarding", so
there's no reason to do normalization there, since only a single
interface sees that packet.
The problem with those switches that can only control the MRU is with
the offloaded data path, where a packet received on an interface with
MRU 9000 would still be forwarded to an interface with MRU 1500. And the
br_mtu_auto_adjust() function does not really help, since the MTU
configured on the bridge net device is ignored.
In order to enforce the de-facto MTU == MRU rule for these switches, we
need to do MTU normalization, which means: in order for no packet larger
than the MTU configured on this port to be sent, then we need to limit
the MRU on all ports that this packet could possibly come from. AKA
since we are configuring the MRU via MTU, it means that all ports within
a bridge forwarding domain should have the same MTU.
And that is exactly what this patch is trying to do.
>From an implementation perspective, we try to follow the intent of the
user, otherwise there is a risk that we might livelock them (they try to
change the MTU on an already-bridged interface, but we just keep
changing it back in an attempt to keep the MTU normalized). So the MTU
that the bridge is normalized to is either:
- The most recently changed one:
ip link set dev swp0 master br0
ip link set dev swp1 master br0
ip link set dev swp0 mtu 1400
This sequence will make swp1 inherit MTU 1400 from swp0.
- The one of the most recently added interface to the bridge:
ip link set dev swp0 master br0
ip link set dev swp1 mtu 1400
ip link set dev swp1 master br0
The above sequence will make swp0 inherit MTU 1400 as well.
Suggested-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-28 03:55:43 +08:00
|
|
|
dsa_bridge_mtu_normalization(dp);
|
|
|
|
|
|
net: dsa: configure the MTU for switch ports
It is useful be able to configure port policers on a switch to accept
frames of various sizes:
- Increase the MTU for better throughput from the default of 1500 if it
is known that there is no 10/100 Mbps device in the network.
- Decrease the MTU to limit the latency of high-priority frames under
congestion, or work around various network segments that add extra
headers to packets which can't be fragmented.
For DSA slave ports, this is mostly a pass-through callback, called
through the regular ndo ops and at probe time (to ensure consistency
across all supported switches).
The CPU port is called with an MTU equal to the largest configured MTU
of the slave ports. The assumption is that the user might want to
sustain a bidirectional conversation with a partner over any switch
port.
The DSA master is configured the same as the CPU port, plus the tagger
overhead. Since the MTU is by definition L2 payload (sans Ethernet
header), it is up to each individual driver to figure out if it needs to
do anything special for its frame tags on the CPU port (it shouldn't
except in special cases). So the MTU does not contain the tagger
overhead on the CPU port.
However the MTU of the DSA master, minus the tagger overhead, is used as
a proxy for the MTU of the CPU port, which does not have a net device.
This is to avoid uselessly calling the .change_mtu function on the CPU
port when nothing should change.
So it is safe to assume that the DSA master and the CPU port MTUs are
apart by exactly the tagger's overhead in bytes.
Some changes were made around dsa_master_set_mtu(), function which was
now removed, for 2 reasons:
- dev_set_mtu() already calls dev_validate_mtu(), so it's redundant to
do the same thing in DSA
- __dev_set_mtu() returns 0 if ops->ndo_change_mtu is an absent method
That is to say, there's no need for this function in DSA, we can safely
call dev_set_mtu() directly, take the rtnl lock when necessary, and just
propagate whatever errors get reported (since the user probably wants to
be informed).
Some inspiration (mainly in the MTU DSA notifier) was taken from a
vaguely similar patch from Murali and Florian, who are credited as
co-developers down below.
Co-developed-by: Murali Krishna Policharla <murali.policharla@broadcom.com>
Signed-off-by: Murali Krishna Policharla <murali.policharla@broadcom.com>
Co-developed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-28 03:55:42 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
out_port_failed:
|
|
|
|
|
if (new_master_mtu != old_master_mtu)
|
|
|
|
|
dsa_port_mtu_change(cpu_dp, old_master_mtu -
|
|
|
|
|
cpu_dp->tag_ops->overhead,
|
|
|
|
|
true);
|
|
|
|
|
out_cpu_failed:
|
|
|
|
|
if (new_master_mtu != old_master_mtu)
|
|
|
|
|
dev_set_mtu(master, old_master_mtu);
|
|
|
|
|
out_master_failed:
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
static const struct ethtool_ops dsa_slave_ethtool_ops = {
|
|
|
|
|
.get_drvinfo = dsa_slave_get_drvinfo,
|
2014-10-30 01:45:04 +08:00
|
|
|
.get_regs_len = dsa_slave_get_regs_len,
|
|
|
|
|
.get_regs = dsa_slave_get_regs,
|
2018-05-11 04:17:36 +08:00
|
|
|
.nway_reset = dsa_slave_nway_reset,
|
2018-05-11 04:17:34 +08:00
|
|
|
.get_link = ethtool_op_get_link,
|
2014-10-30 01:45:01 +08:00
|
|
|
.get_eeprom_len = dsa_slave_get_eeprom_len,
|
|
|
|
|
.get_eeprom = dsa_slave_get_eeprom,
|
|
|
|
|
.set_eeprom = dsa_slave_set_eeprom,
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
.get_strings = dsa_slave_get_strings,
|
|
|
|
|
.get_ethtool_stats = dsa_slave_get_ethtool_stats,
|
|
|
|
|
.get_sset_count = dsa_slave_get_sset_count,
|
2014-09-19 08:31:24 +08:00
|
|
|
.set_wol = dsa_slave_set_wol,
|
|
|
|
|
.get_wol = dsa_slave_get_wol,
|
2014-09-25 08:05:21 +08:00
|
|
|
.set_eee = dsa_slave_set_eee,
|
|
|
|
|
.get_eee = dsa_slave_get_eee,
|
2018-05-11 04:17:36 +08:00
|
|
|
.get_link_ksettings = dsa_slave_get_link_ksettings,
|
|
|
|
|
.set_link_ksettings = dsa_slave_set_link_ksettings,
|
2019-10-30 05:32:48 +08:00
|
|
|
.get_pauseparam = dsa_slave_get_pauseparam,
|
|
|
|
|
.set_pauseparam = dsa_slave_set_pauseparam,
|
2017-01-31 01:48:40 +08:00
|
|
|
.get_rxnfc = dsa_slave_get_rxnfc,
|
|
|
|
|
.set_rxnfc = dsa_slave_set_rxnfc,
|
2018-02-14 08:07:48 +08:00
|
|
|
.get_ts_info = dsa_slave_get_ts_info,
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
};
|
|
|
|
|
|
2017-12-07 07:03:33 +08:00
|
|
|
/* legacy way, bypassing the bridge *****************************************/
|
2021-01-09 07:30:54 +08:00
|
|
|
static int dsa_legacy_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
|
|
|
|
|
struct net_device *dev,
|
|
|
|
|
const unsigned char *addr, u16 vid,
|
|
|
|
|
u16 flags,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
2017-12-07 07:03:33 +08:00
|
|
|
{
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
|
|
return dsa_port_fdb_add(dp, addr, vid);
|
|
|
|
|
}
|
|
|
|
|
|
2021-01-09 07:30:54 +08:00
|
|
|
static int dsa_legacy_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
|
|
|
|
|
struct net_device *dev,
|
|
|
|
|
const unsigned char *addr, u16 vid)
|
2017-12-07 07:03:33 +08:00
|
|
|
{
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
|
|
return dsa_port_fdb_del(dp, addr, vid);
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-28 20:56:43 +08:00
|
|
|
static struct devlink_port *dsa_slave_get_devlink_port(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
|
|
return dp->ds->devlink ? &dp->devlink_port : NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2014-08-28 08:04:46 +08:00
|
|
|
static const struct net_device_ops dsa_slave_netdev_ops = {
|
2009-01-07 08:45:26 +08:00
|
|
|
.ndo_open = dsa_slave_open,
|
|
|
|
|
.ndo_stop = dsa_slave_close,
|
2014-08-28 08:04:46 +08:00
|
|
|
.ndo_start_xmit = dsa_slave_xmit,
|
2009-01-07 08:45:26 +08:00
|
|
|
.ndo_change_rx_flags = dsa_slave_change_rx_flags,
|
|
|
|
|
.ndo_set_rx_mode = dsa_slave_set_rx_mode,
|
|
|
|
|
.ndo_set_mac_address = dsa_slave_set_mac_address,
|
2017-08-06 21:15:43 +08:00
|
|
|
.ndo_fdb_add = dsa_legacy_fdb_add,
|
|
|
|
|
.ndo_fdb_del = dsa_legacy_fdb_del,
|
2017-08-06 21:15:49 +08:00
|
|
|
.ndo_fdb_dump = dsa_slave_fdb_dump,
|
2009-01-07 08:45:26 +08:00
|
|
|
.ndo_do_ioctl = dsa_slave_ioctl,
|
2015-04-02 23:07:08 +08:00
|
|
|
.ndo_get_iflink = dsa_slave_get_iflink,
|
2015-08-01 02:42:57 +08:00
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
|
|
|
.ndo_netpoll_setup = dsa_slave_netpoll_setup,
|
|
|
|
|
.ndo_netpoll_cleanup = dsa_slave_netpoll_cleanup,
|
|
|
|
|
.ndo_poll_controller = dsa_slave_poll_controller,
|
|
|
|
|
#endif
|
2017-01-11 04:32:36 +08:00
|
|
|
.ndo_get_phys_port_name = dsa_slave_get_phys_port_name,
|
2017-01-31 04:41:40 +08:00
|
|
|
.ndo_setup_tc = dsa_slave_setup_tc,
|
2020-11-08 04:49:46 +08:00
|
|
|
.ndo_get_stats64 = dev_get_tstats64,
|
2019-02-07 01:45:45 +08:00
|
|
|
.ndo_get_port_parent_id = dsa_slave_get_port_parent_id,
|
2019-02-21 06:35:39 +08:00
|
|
|
.ndo_vlan_rx_add_vid = dsa_slave_vlan_rx_add_vid,
|
|
|
|
|
.ndo_vlan_rx_kill_vid = dsa_slave_vlan_rx_kill_vid,
|
2019-03-28 20:56:43 +08:00
|
|
|
.ndo_get_devlink_port = dsa_slave_get_devlink_port,
|
net: dsa: configure the MTU for switch ports
It is useful be able to configure port policers on a switch to accept
frames of various sizes:
- Increase the MTU for better throughput from the default of 1500 if it
is known that there is no 10/100 Mbps device in the network.
- Decrease the MTU to limit the latency of high-priority frames under
congestion, or work around various network segments that add extra
headers to packets which can't be fragmented.
For DSA slave ports, this is mostly a pass-through callback, called
through the regular ndo ops and at probe time (to ensure consistency
across all supported switches).
The CPU port is called with an MTU equal to the largest configured MTU
of the slave ports. The assumption is that the user might want to
sustain a bidirectional conversation with a partner over any switch
port.
The DSA master is configured the same as the CPU port, plus the tagger
overhead. Since the MTU is by definition L2 payload (sans Ethernet
header), it is up to each individual driver to figure out if it needs to
do anything special for its frame tags on the CPU port (it shouldn't
except in special cases). So the MTU does not contain the tagger
overhead on the CPU port.
However the MTU of the DSA master, minus the tagger overhead, is used as
a proxy for the MTU of the CPU port, which does not have a net device.
This is to avoid uselessly calling the .change_mtu function on the CPU
port when nothing should change.
So it is safe to assume that the DSA master and the CPU port MTUs are
apart by exactly the tagger's overhead in bytes.
Some changes were made around dsa_master_set_mtu(), function which was
now removed, for 2 reasons:
- dev_set_mtu() already calls dev_validate_mtu(), so it's redundant to
do the same thing in DSA
- __dev_set_mtu() returns 0 if ops->ndo_change_mtu is an absent method
That is to say, there's no need for this function in DSA, we can safely
call dev_set_mtu() directly, take the rtnl lock when necessary, and just
propagate whatever errors get reported (since the user probably wants to
be informed).
Some inspiration (mainly in the MTU DSA notifier) was taken from a
vaguely similar patch from Murali and Florian, who are credited as
co-developers down below.
Co-developed-by: Murali Krishna Policharla <murali.policharla@broadcom.com>
Signed-off-by: Murali Krishna Policharla <murali.policharla@broadcom.com>
Co-developed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-28 03:55:42 +08:00
|
|
|
.ndo_change_mtu = dsa_slave_change_mtu,
|
2015-03-16 12:07:15 +08:00
|
|
|
};
|
|
|
|
|
|
2015-09-24 09:19:58 +08:00
|
|
|
static struct device_type dsa_type = {
|
|
|
|
|
.name = "dsa",
|
|
|
|
|
};
|
|
|
|
|
|
2018-05-11 04:17:36 +08:00
|
|
|
void dsa_port_phylink_mac_change(struct dsa_switch *ds, int port, bool up)
|
|
|
|
|
{
|
|
|
|
|
const struct dsa_port *dp = dsa_to_port(ds, port);
|
|
|
|
|
|
2020-03-31 22:17:36 +08:00
|
|
|
if (dp->pl)
|
|
|
|
|
phylink_mac_change(dp->pl, up);
|
2018-05-11 04:17:36 +08:00
|
|
|
}
|
|
|
|
|
EXPORT_SYMBOL_GPL(dsa_port_phylink_mac_change);
|
|
|
|
|
|
2020-04-24 00:02:56 +08:00
|
|
|
static void dsa_slave_phylink_fixed_state(struct phylink_config *config,
|
2018-05-11 04:17:36 +08:00
|
|
|
struct phylink_link_state *state)
|
|
|
|
|
{
|
2020-04-24 00:02:56 +08:00
|
|
|
struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
|
2018-05-11 04:17:36 +08:00
|
|
|
struct dsa_switch *ds = dp->ds;
|
|
|
|
|
|
|
|
|
|
/* No need to check that this operation is valid, the callback would
|
|
|
|
|
* not be called if it was not.
|
|
|
|
|
*/
|
|
|
|
|
ds->ops->phylink_fixed_state(ds, dp->index, state);
|
2014-08-28 08:04:54 +08:00
|
|
|
}
|
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
/* slave device setup *******************************************************/
|
2017-09-21 07:31:57 +08:00
|
|
|
static int dsa_slave_phy_connect(struct net_device *slave_dev, int addr)
|
2015-03-11 07:57:12 +08:00
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(slave_dev);
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2015-03-11 07:57:12 +08:00
|
|
|
|
2017-09-27 05:15:32 +08:00
|
|
|
slave_dev->phydev = mdiobus_get_phy(ds->slave_mii_bus, addr);
|
|
|
|
|
if (!slave_dev->phydev) {
|
2015-10-04 01:09:07 +08:00
|
|
|
netdev_err(slave_dev, "no phy at %d\n", addr);
|
2015-03-11 07:57:12 +08:00
|
|
|
return -ENODEV;
|
2015-10-04 01:09:07 +08:00
|
|
|
}
|
2015-03-11 07:57:12 +08:00
|
|
|
|
2018-05-11 04:17:36 +08:00
|
|
|
return phylink_connect_phy(dp->pl, slave_dev->phydev);
|
2018-05-11 04:17:32 +08:00
|
|
|
}
|
|
|
|
|
|
2017-09-21 07:31:57 +08:00
|
|
|
static int dsa_slave_phy_setup(struct net_device *slave_dev)
|
2014-08-28 08:04:51 +08:00
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(slave_dev);
|
|
|
|
|
struct device_node *port_dn = dp->dn;
|
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
net: of_get_phy_mode: Change API to solve int/unit warnings
Before this change of_get_phy_mode() returned an enum,
phy_interface_t. On error, -ENODEV etc, is returned. If the result of
the function is stored in a variable of type phy_interface_t, and the
compiler has decided to represent this as an unsigned int, comparision
with -ENODEV etc, is a signed vs unsigned comparision.
Fix this problem by changing the API. Make the function return an
error, or 0 on success, and pass a pointer, of type phy_interface_t,
where the phy mode should be stored.
v2:
Return with *interface set to PHY_INTERFACE_MODE_NA on error.
Add error checks to all users of of_get_phy_mode()
Fixup a few reverse christmas tree errors
Fixup a few slightly malformed reverse christmas trees
v3:
Fix 0-day reported errors.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-04 09:40:33 +08:00
|
|
|
phy_interface_t mode;
|
2014-09-20 04:07:54 +08:00
|
|
|
u32 phy_flags = 0;
|
net: of_get_phy_mode: Change API to solve int/unit warnings
Before this change of_get_phy_mode() returned an enum,
phy_interface_t. On error, -ENODEV etc, is returned. If the result of
the function is stored in a variable of type phy_interface_t, and the
compiler has decided to represent this as an unsigned int, comparision
with -ENODEV etc, is a signed vs unsigned comparision.
Fix this problem by changing the API. Make the function return an
error, or 0 on success, and pass a pointer, of type phy_interface_t,
where the phy mode should be stored.
v2:
Return with *interface set to PHY_INTERFACE_MODE_NA on error.
Add error checks to all users of of_get_phy_mode()
Fixup a few reverse christmas tree errors
Fixup a few slightly malformed reverse christmas trees
v3:
Fix 0-day reported errors.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-04 09:40:33 +08:00
|
|
|
int ret;
|
2014-08-28 08:04:51 +08:00
|
|
|
|
net: of_get_phy_mode: Change API to solve int/unit warnings
Before this change of_get_phy_mode() returned an enum,
phy_interface_t. On error, -ENODEV etc, is returned. If the result of
the function is stored in a variable of type phy_interface_t, and the
compiler has decided to represent this as an unsigned int, comparision
with -ENODEV etc, is a signed vs unsigned comparision.
Fix this problem by changing the API. Make the function return an
error, or 0 on success, and pass a pointer, of type phy_interface_t,
where the phy mode should be stored.
v2:
Return with *interface set to PHY_INTERFACE_MODE_NA on error.
Add error checks to all users of of_get_phy_mode()
Fixup a few reverse christmas tree errors
Fixup a few slightly malformed reverse christmas trees
v3:
Fix 0-day reported errors.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-04 09:40:33 +08:00
|
|
|
ret = of_get_phy_mode(port_dn, &mode);
|
|
|
|
|
if (ret)
|
2015-02-17 13:23:51 +08:00
|
|
|
mode = PHY_INTERFACE_MODE_NA;
|
2014-08-28 08:04:51 +08:00
|
|
|
|
2019-05-29 01:38:12 +08:00
|
|
|
dp->pl_config.dev = &slave_dev->dev;
|
|
|
|
|
dp->pl_config.type = PHYLINK_NETDEV;
|
|
|
|
|
|
2020-04-24 00:02:56 +08:00
|
|
|
/* The get_fixed_state callback takes precedence over polling the
|
|
|
|
|
* link GPIO in PHYLINK (see phylink_get_fixed_state). Only set
|
|
|
|
|
* this if the switch provides such a callback.
|
|
|
|
|
*/
|
|
|
|
|
if (ds->ops->phylink_fixed_state) {
|
|
|
|
|
dp->pl_config.get_fixed_state = dsa_slave_phylink_fixed_state;
|
|
|
|
|
dp->pl_config.poll_fixed_state = true;
|
|
|
|
|
}
|
|
|
|
|
|
2019-05-29 01:38:12 +08:00
|
|
|
dp->pl = phylink_create(&dp->pl_config, of_fwnode_handle(port_dn), mode,
|
2019-05-29 01:38:15 +08:00
|
|
|
&dsa_port_phylink_mac_ops);
|
2018-05-11 04:17:36 +08:00
|
|
|
if (IS_ERR(dp->pl)) {
|
|
|
|
|
netdev_err(slave_dev,
|
|
|
|
|
"error creating PHYLINK: %ld\n", PTR_ERR(dp->pl));
|
|
|
|
|
return PTR_ERR(dp->pl);
|
2014-08-28 08:04:51 +08:00
|
|
|
}
|
|
|
|
|
|
2016-08-24 00:38:56 +08:00
|
|
|
if (ds->ops->get_phy_flags)
|
2017-10-16 23:12:15 +08:00
|
|
|
phy_flags = ds->ops->get_phy_flags(ds, dp->index);
|
2014-09-20 04:07:54 +08:00
|
|
|
|
2018-05-11 04:17:36 +08:00
|
|
|
ret = phylink_of_phy_connect(dp->pl, port_dn, phy_flags);
|
2019-03-24 07:24:07 +08:00
|
|
|
if (ret == -ENODEV && ds->slave_mii_bus) {
|
|
|
|
|
/* We could not connect to a designated PHY or SFP, so try to
|
|
|
|
|
* use the switch internal MDIO bus instead
|
2018-05-11 04:17:36 +08:00
|
|
|
*/
|
2017-10-16 23:12:15 +08:00
|
|
|
ret = dsa_slave_phy_connect(slave_dev, dp->index);
|
2015-10-04 01:09:07 +08:00
|
|
|
if (ret) {
|
2018-05-11 04:17:36 +08:00
|
|
|
netdev_err(slave_dev,
|
|
|
|
|
"failed to connect to port %d: %d\n",
|
2017-10-16 23:12:15 +08:00
|
|
|
dp->index, ret);
|
2018-05-11 04:17:36 +08:00
|
|
|
phylink_destroy(dp->pl);
|
2015-03-11 07:57:12 +08:00
|
|
|
return ret;
|
2015-10-04 01:09:07 +08:00
|
|
|
}
|
2014-11-06 02:47:28 +08:00
|
|
|
}
|
2014-12-12 04:49:16 +08:00
|
|
|
|
2019-03-24 07:24:07 +08:00
|
|
|
return ret;
|
2014-08-28 08:04:51 +08:00
|
|
|
}
|
|
|
|
|
|
2020-05-03 13:22:19 +08:00
|
|
|
static struct lock_class_key dsa_slave_netdev_xmit_lock_key;
|
|
|
|
|
static void dsa_slave_set_lockdep_class_one(struct net_device *dev,
|
|
|
|
|
struct netdev_queue *txq,
|
|
|
|
|
void *_unused)
|
|
|
|
|
{
|
|
|
|
|
lockdep_set_class(&txq->_xmit_lock,
|
|
|
|
|
&dsa_slave_netdev_xmit_lock_key);
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-19 08:31:22 +08:00
|
|
|
int dsa_slave_suspend(struct net_device *slave_dev)
|
|
|
|
|
{
|
2018-05-11 04:17:36 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(slave_dev);
|
2014-09-19 08:31:22 +08:00
|
|
|
|
2018-08-01 08:12:52 +08:00
|
|
|
if (!netif_running(slave_dev))
|
|
|
|
|
return 0;
|
|
|
|
|
|
2017-01-26 01:10:41 +08:00
|
|
|
netif_device_detach(slave_dev);
|
|
|
|
|
|
2018-05-11 04:17:36 +08:00
|
|
|
rtnl_lock();
|
|
|
|
|
phylink_stop(dp->pl);
|
|
|
|
|
rtnl_unlock();
|
2014-09-19 08:31:22 +08:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int dsa_slave_resume(struct net_device *slave_dev)
|
|
|
|
|
{
|
2018-05-11 04:17:36 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(slave_dev);
|
|
|
|
|
|
2018-08-01 08:12:52 +08:00
|
|
|
if (!netif_running(slave_dev))
|
|
|
|
|
return 0;
|
|
|
|
|
|
2014-09-19 08:31:22 +08:00
|
|
|
netif_device_attach(slave_dev);
|
|
|
|
|
|
2018-05-11 04:17:36 +08:00
|
|
|
rtnl_lock();
|
|
|
|
|
phylink_start(dp->pl);
|
|
|
|
|
rtnl_unlock();
|
2014-09-19 08:31:22 +08:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2017-10-28 03:55:19 +08:00
|
|
|
int dsa_slave_create(struct dsa_port *port)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
{
|
2017-11-07 05:11:43 +08:00
|
|
|
const struct dsa_port *cpu_dp = port->cpu_dp;
|
2017-10-16 23:12:18 +08:00
|
|
|
struct net_device *master = cpu_dp->master;
|
2017-08-06 04:20:19 +08:00
|
|
|
struct dsa_switch *ds = port->ds;
|
2017-10-28 03:55:19 +08:00
|
|
|
const char *name = port->name;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
struct net_device *slave_dev;
|
|
|
|
|
struct dsa_slave_priv *p;
|
|
|
|
|
int ret;
|
|
|
|
|
|
2017-09-04 11:27:00 +08:00
|
|
|
if (!ds->num_tx_queues)
|
|
|
|
|
ds->num_tx_queues = 1;
|
|
|
|
|
|
|
|
|
|
slave_dev = alloc_netdev_mqs(sizeof(struct dsa_slave_priv), name,
|
|
|
|
|
NET_NAME_UNKNOWN, ether_setup,
|
|
|
|
|
ds->num_tx_queues, 1);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
if (slave_dev == NULL)
|
2015-02-25 05:15:32 +08:00
|
|
|
return -ENOMEM;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
|
2019-08-26 03:46:29 +08:00
|
|
|
slave_dev->features = master->vlan_features | NETIF_F_HW_TC;
|
|
|
|
|
if (ds->ops->port_vlan_add && ds->ops->port_vlan_del)
|
|
|
|
|
slave_dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
|
2017-01-31 04:41:40 +08:00
|
|
|
slave_dev->hw_features |= NETIF_F_HW_TC;
|
net: dsa: declare lockless TX feature for slave ports
Be there a platform with the following layout:
Regular NIC
|
+----> DSA master for switch port
|
+----> DSA master for another switch port
After changing DSA back to static lockdep class keys in commit
1a33e10e4a95 ("net: partially revert dynamic lockdep key changes"), this
kernel splat can be seen:
[ 13.361198] ============================================
[ 13.366524] WARNING: possible recursive locking detected
[ 13.371851] 5.7.0-rc4-02121-gc32a05ecd7af-dirty #988 Not tainted
[ 13.377874] --------------------------------------------
[ 13.383201] swapper/0/0 is trying to acquire lock:
[ 13.388004] ffff0000668ff298 (&dsa_slave_netdev_xmit_lock_key){+.-.}-{2:2}, at: __dev_queue_xmit+0x84c/0xbe0
[ 13.397879]
[ 13.397879] but task is already holding lock:
[ 13.403727] ffff0000661a1698 (&dsa_slave_netdev_xmit_lock_key){+.-.}-{2:2}, at: __dev_queue_xmit+0x84c/0xbe0
[ 13.413593]
[ 13.413593] other info that might help us debug this:
[ 13.420140] Possible unsafe locking scenario:
[ 13.420140]
[ 13.426075] CPU0
[ 13.428523] ----
[ 13.430969] lock(&dsa_slave_netdev_xmit_lock_key);
[ 13.435946] lock(&dsa_slave_netdev_xmit_lock_key);
[ 13.440924]
[ 13.440924] *** DEADLOCK ***
[ 13.440924]
[ 13.446860] May be due to missing lock nesting notation
[ 13.446860]
[ 13.453668] 6 locks held by swapper/0/0:
[ 13.457598] #0: ffff800010003de0 ((&idev->mc_ifc_timer)){+.-.}-{0:0}, at: call_timer_fn+0x0/0x400
[ 13.466593] #1: ffffd4d3fb478700 (rcu_read_lock){....}-{1:2}, at: mld_sendpack+0x0/0x560
[ 13.474803] #2: ffffd4d3fb478728 (rcu_read_lock_bh){....}-{1:2}, at: ip6_finish_output2+0x64/0xb10
[ 13.483886] #3: ffffd4d3fb478728 (rcu_read_lock_bh){....}-{1:2}, at: __dev_queue_xmit+0x6c/0xbe0
[ 13.492793] #4: ffff0000661a1698 (&dsa_slave_netdev_xmit_lock_key){+.-.}-{2:2}, at: __dev_queue_xmit+0x84c/0xbe0
[ 13.503094] #5: ffffd4d3fb478728 (rcu_read_lock_bh){....}-{1:2}, at: __dev_queue_xmit+0x6c/0xbe0
[ 13.512000]
[ 13.512000] stack backtrace:
[ 13.516369] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.7.0-rc4-02121-gc32a05ecd7af-dirty #988
[ 13.530421] Call trace:
[ 13.532871] dump_backtrace+0x0/0x1d8
[ 13.536539] show_stack+0x24/0x30
[ 13.539862] dump_stack+0xe8/0x150
[ 13.543271] __lock_acquire+0x1030/0x1678
[ 13.547290] lock_acquire+0xf8/0x458
[ 13.550873] _raw_spin_lock+0x44/0x58
[ 13.554543] __dev_queue_xmit+0x84c/0xbe0
[ 13.558562] dev_queue_xmit+0x24/0x30
[ 13.562232] dsa_slave_xmit+0xe0/0x128
[ 13.565988] dev_hard_start_xmit+0xf4/0x448
[ 13.570182] __dev_queue_xmit+0x808/0xbe0
[ 13.574200] dev_queue_xmit+0x24/0x30
[ 13.577869] neigh_resolve_output+0x15c/0x220
[ 13.582237] ip6_finish_output2+0x244/0xb10
[ 13.586430] __ip6_finish_output+0x1dc/0x298
[ 13.590709] ip6_output+0x84/0x358
[ 13.594116] mld_sendpack+0x2bc/0x560
[ 13.597786] mld_ifc_timer_expire+0x210/0x390
[ 13.602153] call_timer_fn+0xcc/0x400
[ 13.605822] run_timer_softirq+0x588/0x6e0
[ 13.609927] __do_softirq+0x118/0x590
[ 13.613597] irq_exit+0x13c/0x148
[ 13.616918] __handle_domain_irq+0x6c/0xc0
[ 13.621023] gic_handle_irq+0x6c/0x160
[ 13.624779] el1_irq+0xbc/0x180
[ 13.627927] cpuidle_enter_state+0xb4/0x4d0
[ 13.632120] cpuidle_enter+0x3c/0x50
[ 13.635703] call_cpuidle+0x44/0x78
[ 13.639199] do_idle+0x228/0x2c8
[ 13.642433] cpu_startup_entry+0x2c/0x48
[ 13.646363] rest_init+0x1ac/0x280
[ 13.649773] arch_call_rest_init+0x14/0x1c
[ 13.653878] start_kernel+0x490/0x4bc
Lockdep keys themselves were added in commit ab92d68fc22f ("net: core:
add generic lockdep keys"), and it's very likely that this splat existed
since then, but I have no real way to check, since this stacked platform
wasn't supported by mainline back then.
>From Taehee's own words:
This patch was considered that all stackable devices have LLTX flag.
But the dsa doesn't have LLTX, so this splat happened.
After this patch, dsa shares the same lockdep class key.
On the nested dsa interface architecture, which you illustrated,
the same lockdep class key will be used in __dev_queue_xmit() because
dsa doesn't have LLTX.
So that lockdep detects deadlock because the same lockdep class key is
used recursively although actually the different locks are used.
There are some ways to fix this problem.
1. using NETIF_F_LLTX flag.
If possible, using the LLTX flag is a very clear way for it.
But I'm so sorry I don't know whether the dsa could have LLTX or not.
2. using dynamic lockdep again.
It means that each interface uses a separate lockdep class key.
So, lockdep will not detect recursive locking.
But this way has a problem that it could consume lockdep class key
too many.
Currently, lockdep can have 8192 lockdep class keys.
- you can see this number with the following command.
cat /proc/lockdep_stats
lock-classes: 1251 [max: 8192]
...
The [max: 8192] means that the maximum number of lockdep class keys.
If too many lockdep class keys are registered, lockdep stops to work.
So, using a dynamic(separated) lockdep class key should be considered
carefully.
In addition, updating lockdep class key routine might have to be existing.
(lockdep_register_key(), lockdep_set_class(), lockdep_unregister_key())
3. Using lockdep subclass.
A lockdep class key could have 8 subclasses.
The different subclass is considered different locks by lockdep
infrastructure.
But "lock-classes" is not counted by subclasses.
So, it could avoid stopping lockdep infrastructure by an overflow of
lockdep class keys.
This approach should also have an updating lockdep class key routine.
(lockdep_set_subclass())
4. Using nonvalidate lockdep class key.
The lockdep infrastructure supports nonvalidate lockdep class key type.
It means this lockdep is not validated by lockdep infrastructure.
So, the splat will not happen but lockdep couldn't detect real deadlock
case because lockdep really doesn't validate it.
I think this should be used for really special cases.
(lockdep_set_novalidate_class())
Further discussion here:
https://patchwork.ozlabs.org/project/netdev/patch/20200503052220.4536-2-xiyou.wangcong@gmail.com/
There appears to be no negative side-effect to declaring lockless TX for
the DSA virtual interfaces, which means they handle their own locking.
So that's what we do to make the splat go away.
Patch tested in a wide variety of cases: unicast, multicast, PTP, etc.
Fixes: ab92d68fc22f ("net: core: add generic lockdep keys")
Suggested-by: Taehee Yoo <ap420073@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-05-28 02:08:05 +08:00
|
|
|
slave_dev->features |= NETIF_F_LLTX;
|
2014-05-11 08:12:32 +08:00
|
|
|
slave_dev->ethtool_ops = &dsa_slave_ethtool_ops;
|
2019-05-07 05:24:45 +08:00
|
|
|
if (!IS_ERR_OR_NULL(port->mac))
|
2019-03-29 13:34:58 +08:00
|
|
|
ether_addr_copy(slave_dev->dev_addr, port->mac);
|
|
|
|
|
else
|
|
|
|
|
eth_hw_addr_inherit(slave_dev, master);
|
2015-08-18 16:30:41 +08:00
|
|
|
slave_dev->priv_flags |= IFF_NO_QUEUE;
|
2014-08-28 08:04:46 +08:00
|
|
|
slave_dev->netdev_ops = &dsa_slave_netdev_ops;
|
net: dsa: configure the MTU for switch ports
It is useful be able to configure port policers on a switch to accept
frames of various sizes:
- Increase the MTU for better throughput from the default of 1500 if it
is known that there is no 10/100 Mbps device in the network.
- Decrease the MTU to limit the latency of high-priority frames under
congestion, or work around various network segments that add extra
headers to packets which can't be fragmented.
For DSA slave ports, this is mostly a pass-through callback, called
through the regular ndo ops and at probe time (to ensure consistency
across all supported switches).
The CPU port is called with an MTU equal to the largest configured MTU
of the slave ports. The assumption is that the user might want to
sustain a bidirectional conversation with a partner over any switch
port.
The DSA master is configured the same as the CPU port, plus the tagger
overhead. Since the MTU is by definition L2 payload (sans Ethernet
header), it is up to each individual driver to figure out if it needs to
do anything special for its frame tags on the CPU port (it shouldn't
except in special cases). So the MTU does not contain the tagger
overhead on the CPU port.
However the MTU of the DSA master, minus the tagger overhead, is used as
a proxy for the MTU of the CPU port, which does not have a net device.
This is to avoid uselessly calling the .change_mtu function on the CPU
port when nothing should change.
So it is safe to assume that the DSA master and the CPU port MTUs are
apart by exactly the tagger's overhead in bytes.
Some changes were made around dsa_master_set_mtu(), function which was
now removed, for 2 reasons:
- dev_set_mtu() already calls dev_validate_mtu(), so it's redundant to
do the same thing in DSA
- __dev_set_mtu() returns 0 if ops->ndo_change_mtu is an absent method
That is to say, there's no need for this function in DSA, we can safely
call dev_set_mtu() directly, take the rtnl lock when necessary, and just
propagate whatever errors get reported (since the user probably wants to
be informed).
Some inspiration (mainly in the MTU DSA notifier) was taken from a
vaguely similar patch from Murali and Florian, who are credited as
co-developers down below.
Co-developed-by: Murali Krishna Policharla <murali.policharla@broadcom.com>
Signed-off-by: Murali Krishna Policharla <murali.policharla@broadcom.com>
Co-developed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-28 03:55:42 +08:00
|
|
|
if (ds->ops->port_max_mtu)
|
|
|
|
|
slave_dev->max_mtu = ds->ops->port_max_mtu(ds, port->index);
|
net: dsa: implement a central TX reallocation procedure
At the moment, taggers are left with the task of ensuring that the skb
headers are writable (which they aren't, if the frames were cloned for
TX timestamping, for flooding by the bridge, etc), and that there is
enough space in the skb data area for the DSA tag to be pushed.
Moreover, the life of tail taggers is even harder, because they need to
ensure that short frames have enough padding, a problem that normal
taggers don't have.
The principle of the DSA framework is that everything except for the
most intimate hardware specifics (like in this case, the actual packing
of the DSA tag bits) should be done inside the core, to avoid having
code paths that are very rarely tested.
So provide a TX reallocation procedure that should cover the known needs
of DSA today.
Note that this patch also gives the network stack a good hint about the
headroom/tailroom it's going to need. Up till now it wasn't doing that.
So the reallocation procedure should really be there only for the
exceptional cases, and for cloned packets which need to be unshared.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Christian Eggers <ceggers@arri.de> # For tail taggers only
Tested-by: Kurt Kanzenbach <kurt@linutronix.de>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-02 03:16:09 +08:00
|
|
|
if (cpu_dp->tag_ops->tail_tag)
|
|
|
|
|
slave_dev->needed_tailroom = cpu_dp->tag_ops->overhead;
|
|
|
|
|
else
|
|
|
|
|
slave_dev->needed_headroom = cpu_dp->tag_ops->overhead;
|
|
|
|
|
/* Try to save one extra realloc later in the TX path (in the master)
|
|
|
|
|
* by also inheriting the master's needed headroom and tailroom.
|
|
|
|
|
* The 8021q driver also does this.
|
|
|
|
|
*/
|
|
|
|
|
slave_dev->needed_headroom += master->needed_headroom;
|
|
|
|
|
slave_dev->needed_tailroom += master->needed_tailroom;
|
2015-09-24 09:19:58 +08:00
|
|
|
SET_NETDEV_DEVTYPE(slave_dev, &dsa_type);
|
2009-01-07 08:45:26 +08:00
|
|
|
|
2020-05-03 13:22:19 +08:00
|
|
|
netdev_for_each_tx_queue(slave_dev, dsa_slave_set_lockdep_class_one,
|
|
|
|
|
NULL);
|
|
|
|
|
|
2017-08-06 04:20:19 +08:00
|
|
|
SET_NETDEV_DEV(slave_dev, port->ds->dev);
|
|
|
|
|
slave_dev->dev.of_node = port->dn;
|
2014-09-16 01:00:19 +08:00
|
|
|
slave_dev->vlan_features = master->vlan_features;
|
|
|
|
|
|
|
|
|
|
p = netdev_priv(slave_dev);
|
2020-11-08 04:49:46 +08:00
|
|
|
slave_dev->tstats = netdev_alloc_pcpu_stats(struct pcpu_sw_netstats);
|
|
|
|
|
if (!slave_dev->tstats) {
|
2017-08-04 12:33:27 +08:00
|
|
|
free_netdev(slave_dev);
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
}
|
2020-04-21 21:41:08 +08:00
|
|
|
|
|
|
|
|
ret = gro_cells_init(&p->gcells, slave_dev);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto out_free;
|
|
|
|
|
|
2017-08-06 04:20:19 +08:00
|
|
|
p->dp = port;
|
2017-01-31 04:41:40 +08:00
|
|
|
INIT_LIST_HEAD(&p->mall_tc_list);
|
2017-09-30 05:19:18 +08:00
|
|
|
p->xmit = cpu_dp->tag_ops->xmit;
|
2017-10-16 23:12:18 +08:00
|
|
|
port->slave = slave_dev;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
|
net: dsa: configure the MTU for switch ports
It is useful be able to configure port policers on a switch to accept
frames of various sizes:
- Increase the MTU for better throughput from the default of 1500 if it
is known that there is no 10/100 Mbps device in the network.
- Decrease the MTU to limit the latency of high-priority frames under
congestion, or work around various network segments that add extra
headers to packets which can't be fragmented.
For DSA slave ports, this is mostly a pass-through callback, called
through the regular ndo ops and at probe time (to ensure consistency
across all supported switches).
The CPU port is called with an MTU equal to the largest configured MTU
of the slave ports. The assumption is that the user might want to
sustain a bidirectional conversation with a partner over any switch
port.
The DSA master is configured the same as the CPU port, plus the tagger
overhead. Since the MTU is by definition L2 payload (sans Ethernet
header), it is up to each individual driver to figure out if it needs to
do anything special for its frame tags on the CPU port (it shouldn't
except in special cases). So the MTU does not contain the tagger
overhead on the CPU port.
However the MTU of the DSA master, minus the tagger overhead, is used as
a proxy for the MTU of the CPU port, which does not have a net device.
This is to avoid uselessly calling the .change_mtu function on the CPU
port when nothing should change.
So it is safe to assume that the DSA master and the CPU port MTUs are
apart by exactly the tagger's overhead in bytes.
Some changes were made around dsa_master_set_mtu(), function which was
now removed, for 2 reasons:
- dev_set_mtu() already calls dev_validate_mtu(), so it's redundant to
do the same thing in DSA
- __dev_set_mtu() returns 0 if ops->ndo_change_mtu is an absent method
That is to say, there's no need for this function in DSA, we can safely
call dev_set_mtu() directly, take the rtnl lock when necessary, and just
propagate whatever errors get reported (since the user probably wants to
be informed).
Some inspiration (mainly in the MTU DSA notifier) was taken from a
vaguely similar patch from Murali and Florian, who are credited as
co-developers down below.
Co-developed-by: Murali Krishna Policharla <murali.policharla@broadcom.com>
Signed-off-by: Murali Krishna Policharla <murali.policharla@broadcom.com>
Co-developed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-28 03:55:42 +08:00
|
|
|
rtnl_lock();
|
|
|
|
|
ret = dsa_slave_change_mtu(slave_dev, ETH_DATA_LEN);
|
|
|
|
|
rtnl_unlock();
|
2020-09-08 07:25:56 +08:00
|
|
|
if (ret && ret != -EOPNOTSUPP)
|
2020-12-05 21:39:44 +08:00
|
|
|
dev_warn(ds->dev, "nonfatal error %d setting MTU to %d on port %d\n",
|
|
|
|
|
ret, ETH_DATA_LEN, port->index);
|
net: dsa: configure the MTU for switch ports
It is useful be able to configure port policers on a switch to accept
frames of various sizes:
- Increase the MTU for better throughput from the default of 1500 if it
is known that there is no 10/100 Mbps device in the network.
- Decrease the MTU to limit the latency of high-priority frames under
congestion, or work around various network segments that add extra
headers to packets which can't be fragmented.
For DSA slave ports, this is mostly a pass-through callback, called
through the regular ndo ops and at probe time (to ensure consistency
across all supported switches).
The CPU port is called with an MTU equal to the largest configured MTU
of the slave ports. The assumption is that the user might want to
sustain a bidirectional conversation with a partner over any switch
port.
The DSA master is configured the same as the CPU port, plus the tagger
overhead. Since the MTU is by definition L2 payload (sans Ethernet
header), it is up to each individual driver to figure out if it needs to
do anything special for its frame tags on the CPU port (it shouldn't
except in special cases). So the MTU does not contain the tagger
overhead on the CPU port.
However the MTU of the DSA master, minus the tagger overhead, is used as
a proxy for the MTU of the CPU port, which does not have a net device.
This is to avoid uselessly calling the .change_mtu function on the CPU
port when nothing should change.
So it is safe to assume that the DSA master and the CPU port MTUs are
apart by exactly the tagger's overhead in bytes.
Some changes were made around dsa_master_set_mtu(), function which was
now removed, for 2 reasons:
- dev_set_mtu() already calls dev_validate_mtu(), so it's redundant to
do the same thing in DSA
- __dev_set_mtu() returns 0 if ops->ndo_change_mtu is an absent method
That is to say, there's no need for this function in DSA, we can safely
call dev_set_mtu() directly, take the rtnl lock when necessary, and just
propagate whatever errors get reported (since the user probably wants to
be informed).
Some inspiration (mainly in the MTU DSA notifier) was taken from a
vaguely similar patch from Murali and Florian, who are credited as
co-developers down below.
Co-developed-by: Murali Krishna Policharla <murali.policharla@broadcom.com>
Signed-off-by: Murali Krishna Policharla <murali.policharla@broadcom.com>
Co-developed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-28 03:55:42 +08:00
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
netif_carrier_off(slave_dev);
|
|
|
|
|
|
2017-09-21 07:31:57 +08:00
|
|
|
ret = dsa_slave_phy_setup(slave_dev);
|
2016-01-07 03:11:20 +08:00
|
|
|
if (ret) {
|
net: dsa: change PHY error message again
slave_dev->name is only populated at this stage if it was specified
through a label in the device tree. However that is not mandatory.
When it isn't, the error message looks like this:
[ 5.037057] fsl_enetc 0000:00:00.2 eth2: error -19 setting up slave PHY for eth%d
[ 5.044672] fsl_enetc 0000:00:00.2 eth2: error -19 setting up slave PHY for eth%d
[ 5.052275] fsl_enetc 0000:00:00.2 eth2: error -19 setting up slave PHY for eth%d
[ 5.059877] fsl_enetc 0000:00:00.2 eth2: error -19 setting up slave PHY for eth%d
which is especially confusing since the error gets printed on behalf of
the DSA master (fsl_enetc in this case).
Printing an error message that contains a valid reference to the DSA
port's name is difficult at this point in the initialization stage, so
at least we should print some info that is more reliable, even if less
user-friendly. That may be the driver name and the hardware port index.
After this change, the error is printed as:
[ 6.051587] mscc_felix 0000:00:00.5: error -19 setting up PHY for tree 0, switch 0, port 0
[ 6.061192] mscc_felix 0000:00:00.5: error -19 setting up PHY for tree 0, switch 0, port 1
[ 6.070765] mscc_felix 0000:00:00.5: error -19 setting up PHY for tree 0, switch 0, port 2
[ 6.080324] mscc_felix 0000:00:00.5: error -19 setting up PHY for tree 0, switch 0, port 3
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-09-08 07:06:56 +08:00
|
|
|
netdev_err(slave_dev,
|
|
|
|
|
"error %d setting up PHY for tree %d, switch %d, port %d\n",
|
|
|
|
|
ret, ds->dst->index, ds->index, port->index);
|
2020-04-21 21:41:08 +08:00
|
|
|
goto out_gcells;
|
2017-09-26 06:55:53 +08:00
|
|
|
}
|
|
|
|
|
|
net: dsa: link interfaces with the DSA master to get rid of lockdep warnings
Since commit 845e0ebb4408 ("net: change addr_list_lock back to static
key"), cascaded DSA setups (DSA switch port as DSA master for another
DSA switch port) are emitting this lockdep warning:
============================================
WARNING: possible recursive locking detected
5.8.0-rc1-00133-g923e4b5032dd-dirty #208 Not tainted
--------------------------------------------
dhcpcd/323 is trying to acquire lock:
ffff000066dd4268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
but task is already holding lock:
ffff00006608c268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(&dsa_master_addr_list_lock_key/1);
lock(&dsa_master_addr_list_lock_key/1);
*** DEADLOCK ***
May be due to missing lock nesting notation
3 locks held by dhcpcd/323:
#0: ffffdbd1381dda18 (rtnl_mutex){+.+.}-{3:3}, at: rtnl_lock+0x24/0x30
#1: ffff00006614b268 (_xmit_ETHER){+...}-{2:2}, at: dev_set_rx_mode+0x28/0x48
#2: ffff00006608c268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
stack backtrace:
Call trace:
dump_backtrace+0x0/0x1e0
show_stack+0x20/0x30
dump_stack+0xec/0x158
__lock_acquire+0xca0/0x2398
lock_acquire+0xe8/0x440
_raw_spin_lock_nested+0x64/0x90
dev_mc_sync+0x44/0x90
dsa_slave_set_rx_mode+0x34/0x50
__dev_set_rx_mode+0x60/0xa0
dev_mc_sync+0x84/0x90
dsa_slave_set_rx_mode+0x34/0x50
__dev_set_rx_mode+0x60/0xa0
dev_set_rx_mode+0x30/0x48
__dev_open+0x10c/0x180
__dev_change_flags+0x170/0x1c8
dev_change_flags+0x2c/0x70
devinet_ioctl+0x774/0x878
inet_ioctl+0x348/0x3b0
sock_do_ioctl+0x50/0x310
sock_ioctl+0x1f8/0x580
ksys_ioctl+0xb0/0xf0
__arm64_sys_ioctl+0x28/0x38
el0_svc_common.constprop.0+0x7c/0x180
do_el0_svc+0x2c/0x98
el0_sync_handler+0x9c/0x1b8
el0_sync+0x158/0x180
Since DSA never made use of the netdev API for describing links between
upper devices and lower devices, the dev->lower_level value of a DSA
switch interface would be 1, which would warn when it is a DSA master.
We can use netdev_upper_dev_link() to describe the relationship between
a DSA slave and a DSA master. To be precise, a DSA "slave" (switch port)
is an "upper" to a DSA "master" (host port). The relationship is "many
uppers to one lower", like in the case of VLAN. So, for that reason, we
use the same function as VLAN uses.
There might be a chance that somebody will try to take hold of this
interface and use it immediately after register_netdev() and before
netdev_upper_dev_link(). To avoid that, we do the registration and
linkage while holding the RTNL, and we use the RTNL-locked cousin of
register_netdev(), which is register_netdevice().
Since this warning was not there when lockdep was using dynamic keys for
addr_list_lock, we are blaming the lockdep patch itself. The network
stack _has_ been using static lockdep keys before, and it _is_ likely
that stacked DSA setups have been triggering these lockdep warnings
since forever, however I can't test very old kernels on this particular
stacked DSA setup, to ensure I'm not in fact introducing regressions.
Fixes: 845e0ebb4408 ("net: change addr_list_lock back to static key")
Suggested-by: Cong Wang <xiyou.wangcong@gmail.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-08 07:48:42 +08:00
|
|
|
rtnl_lock();
|
|
|
|
|
|
|
|
|
|
ret = register_netdevice(slave_dev);
|
2017-09-26 06:55:53 +08:00
|
|
|
if (ret) {
|
|
|
|
|
netdev_err(master, "error %d registering interface %s\n",
|
|
|
|
|
ret, slave_dev->name);
|
net: dsa: link interfaces with the DSA master to get rid of lockdep warnings
Since commit 845e0ebb4408 ("net: change addr_list_lock back to static
key"), cascaded DSA setups (DSA switch port as DSA master for another
DSA switch port) are emitting this lockdep warning:
============================================
WARNING: possible recursive locking detected
5.8.0-rc1-00133-g923e4b5032dd-dirty #208 Not tainted
--------------------------------------------
dhcpcd/323 is trying to acquire lock:
ffff000066dd4268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
but task is already holding lock:
ffff00006608c268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(&dsa_master_addr_list_lock_key/1);
lock(&dsa_master_addr_list_lock_key/1);
*** DEADLOCK ***
May be due to missing lock nesting notation
3 locks held by dhcpcd/323:
#0: ffffdbd1381dda18 (rtnl_mutex){+.+.}-{3:3}, at: rtnl_lock+0x24/0x30
#1: ffff00006614b268 (_xmit_ETHER){+...}-{2:2}, at: dev_set_rx_mode+0x28/0x48
#2: ffff00006608c268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
stack backtrace:
Call trace:
dump_backtrace+0x0/0x1e0
show_stack+0x20/0x30
dump_stack+0xec/0x158
__lock_acquire+0xca0/0x2398
lock_acquire+0xe8/0x440
_raw_spin_lock_nested+0x64/0x90
dev_mc_sync+0x44/0x90
dsa_slave_set_rx_mode+0x34/0x50
__dev_set_rx_mode+0x60/0xa0
dev_mc_sync+0x84/0x90
dsa_slave_set_rx_mode+0x34/0x50
__dev_set_rx_mode+0x60/0xa0
dev_set_rx_mode+0x30/0x48
__dev_open+0x10c/0x180
__dev_change_flags+0x170/0x1c8
dev_change_flags+0x2c/0x70
devinet_ioctl+0x774/0x878
inet_ioctl+0x348/0x3b0
sock_do_ioctl+0x50/0x310
sock_ioctl+0x1f8/0x580
ksys_ioctl+0xb0/0xf0
__arm64_sys_ioctl+0x28/0x38
el0_svc_common.constprop.0+0x7c/0x180
do_el0_svc+0x2c/0x98
el0_sync_handler+0x9c/0x1b8
el0_sync+0x158/0x180
Since DSA never made use of the netdev API for describing links between
upper devices and lower devices, the dev->lower_level value of a DSA
switch interface would be 1, which would warn when it is a DSA master.
We can use netdev_upper_dev_link() to describe the relationship between
a DSA slave and a DSA master. To be precise, a DSA "slave" (switch port)
is an "upper" to a DSA "master" (host port). The relationship is "many
uppers to one lower", like in the case of VLAN. So, for that reason, we
use the same function as VLAN uses.
There might be a chance that somebody will try to take hold of this
interface and use it immediately after register_netdev() and before
netdev_upper_dev_link(). To avoid that, we do the registration and
linkage while holding the RTNL, and we use the RTNL-locked cousin of
register_netdev(), which is register_netdevice().
Since this warning was not there when lockdep was using dynamic keys for
addr_list_lock, we are blaming the lockdep patch itself. The network
stack _has_ been using static lockdep keys before, and it _is_ likely
that stacked DSA setups have been triggering these lockdep warnings
since forever, however I can't test very old kernels on this particular
stacked DSA setup, to ensure I'm not in fact introducing regressions.
Fixes: 845e0ebb4408 ("net: change addr_list_lock back to static key")
Suggested-by: Cong Wang <xiyou.wangcong@gmail.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-08 07:48:42 +08:00
|
|
|
rtnl_unlock();
|
2017-09-26 06:55:53 +08:00
|
|
|
goto out_phy;
|
2016-01-07 03:11:20 +08:00
|
|
|
}
|
|
|
|
|
|
net: dsa: link interfaces with the DSA master to get rid of lockdep warnings
Since commit 845e0ebb4408 ("net: change addr_list_lock back to static
key"), cascaded DSA setups (DSA switch port as DSA master for another
DSA switch port) are emitting this lockdep warning:
============================================
WARNING: possible recursive locking detected
5.8.0-rc1-00133-g923e4b5032dd-dirty #208 Not tainted
--------------------------------------------
dhcpcd/323 is trying to acquire lock:
ffff000066dd4268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
but task is already holding lock:
ffff00006608c268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(&dsa_master_addr_list_lock_key/1);
lock(&dsa_master_addr_list_lock_key/1);
*** DEADLOCK ***
May be due to missing lock nesting notation
3 locks held by dhcpcd/323:
#0: ffffdbd1381dda18 (rtnl_mutex){+.+.}-{3:3}, at: rtnl_lock+0x24/0x30
#1: ffff00006614b268 (_xmit_ETHER){+...}-{2:2}, at: dev_set_rx_mode+0x28/0x48
#2: ffff00006608c268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
stack backtrace:
Call trace:
dump_backtrace+0x0/0x1e0
show_stack+0x20/0x30
dump_stack+0xec/0x158
__lock_acquire+0xca0/0x2398
lock_acquire+0xe8/0x440
_raw_spin_lock_nested+0x64/0x90
dev_mc_sync+0x44/0x90
dsa_slave_set_rx_mode+0x34/0x50
__dev_set_rx_mode+0x60/0xa0
dev_mc_sync+0x84/0x90
dsa_slave_set_rx_mode+0x34/0x50
__dev_set_rx_mode+0x60/0xa0
dev_set_rx_mode+0x30/0x48
__dev_open+0x10c/0x180
__dev_change_flags+0x170/0x1c8
dev_change_flags+0x2c/0x70
devinet_ioctl+0x774/0x878
inet_ioctl+0x348/0x3b0
sock_do_ioctl+0x50/0x310
sock_ioctl+0x1f8/0x580
ksys_ioctl+0xb0/0xf0
__arm64_sys_ioctl+0x28/0x38
el0_svc_common.constprop.0+0x7c/0x180
do_el0_svc+0x2c/0x98
el0_sync_handler+0x9c/0x1b8
el0_sync+0x158/0x180
Since DSA never made use of the netdev API for describing links between
upper devices and lower devices, the dev->lower_level value of a DSA
switch interface would be 1, which would warn when it is a DSA master.
We can use netdev_upper_dev_link() to describe the relationship between
a DSA slave and a DSA master. To be precise, a DSA "slave" (switch port)
is an "upper" to a DSA "master" (host port). The relationship is "many
uppers to one lower", like in the case of VLAN. So, for that reason, we
use the same function as VLAN uses.
There might be a chance that somebody will try to take hold of this
interface and use it immediately after register_netdev() and before
netdev_upper_dev_link(). To avoid that, we do the registration and
linkage while holding the RTNL, and we use the RTNL-locked cousin of
register_netdev(), which is register_netdevice().
Since this warning was not there when lockdep was using dynamic keys for
addr_list_lock, we are blaming the lockdep patch itself. The network
stack _has_ been using static lockdep keys before, and it _is_ likely
that stacked DSA setups have been triggering these lockdep warnings
since forever, however I can't test very old kernels on this particular
stacked DSA setup, to ensure I'm not in fact introducing regressions.
Fixes: 845e0ebb4408 ("net: change addr_list_lock back to static key")
Suggested-by: Cong Wang <xiyou.wangcong@gmail.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-08 07:48:42 +08:00
|
|
|
ret = netdev_upper_dev_link(master, slave_dev, NULL);
|
|
|
|
|
|
|
|
|
|
rtnl_unlock();
|
|
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
|
goto out_unregister;
|
|
|
|
|
|
2015-02-25 05:15:32 +08:00
|
|
|
return 0;
|
2017-09-26 06:55:53 +08:00
|
|
|
|
net: dsa: link interfaces with the DSA master to get rid of lockdep warnings
Since commit 845e0ebb4408 ("net: change addr_list_lock back to static
key"), cascaded DSA setups (DSA switch port as DSA master for another
DSA switch port) are emitting this lockdep warning:
============================================
WARNING: possible recursive locking detected
5.8.0-rc1-00133-g923e4b5032dd-dirty #208 Not tainted
--------------------------------------------
dhcpcd/323 is trying to acquire lock:
ffff000066dd4268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
but task is already holding lock:
ffff00006608c268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(&dsa_master_addr_list_lock_key/1);
lock(&dsa_master_addr_list_lock_key/1);
*** DEADLOCK ***
May be due to missing lock nesting notation
3 locks held by dhcpcd/323:
#0: ffffdbd1381dda18 (rtnl_mutex){+.+.}-{3:3}, at: rtnl_lock+0x24/0x30
#1: ffff00006614b268 (_xmit_ETHER){+...}-{2:2}, at: dev_set_rx_mode+0x28/0x48
#2: ffff00006608c268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
stack backtrace:
Call trace:
dump_backtrace+0x0/0x1e0
show_stack+0x20/0x30
dump_stack+0xec/0x158
__lock_acquire+0xca0/0x2398
lock_acquire+0xe8/0x440
_raw_spin_lock_nested+0x64/0x90
dev_mc_sync+0x44/0x90
dsa_slave_set_rx_mode+0x34/0x50
__dev_set_rx_mode+0x60/0xa0
dev_mc_sync+0x84/0x90
dsa_slave_set_rx_mode+0x34/0x50
__dev_set_rx_mode+0x60/0xa0
dev_set_rx_mode+0x30/0x48
__dev_open+0x10c/0x180
__dev_change_flags+0x170/0x1c8
dev_change_flags+0x2c/0x70
devinet_ioctl+0x774/0x878
inet_ioctl+0x348/0x3b0
sock_do_ioctl+0x50/0x310
sock_ioctl+0x1f8/0x580
ksys_ioctl+0xb0/0xf0
__arm64_sys_ioctl+0x28/0x38
el0_svc_common.constprop.0+0x7c/0x180
do_el0_svc+0x2c/0x98
el0_sync_handler+0x9c/0x1b8
el0_sync+0x158/0x180
Since DSA never made use of the netdev API for describing links between
upper devices and lower devices, the dev->lower_level value of a DSA
switch interface would be 1, which would warn when it is a DSA master.
We can use netdev_upper_dev_link() to describe the relationship between
a DSA slave and a DSA master. To be precise, a DSA "slave" (switch port)
is an "upper" to a DSA "master" (host port). The relationship is "many
uppers to one lower", like in the case of VLAN. So, for that reason, we
use the same function as VLAN uses.
There might be a chance that somebody will try to take hold of this
interface and use it immediately after register_netdev() and before
netdev_upper_dev_link(). To avoid that, we do the registration and
linkage while holding the RTNL, and we use the RTNL-locked cousin of
register_netdev(), which is register_netdevice().
Since this warning was not there when lockdep was using dynamic keys for
addr_list_lock, we are blaming the lockdep patch itself. The network
stack _has_ been using static lockdep keys before, and it _is_ likely
that stacked DSA setups have been triggering these lockdep warnings
since forever, however I can't test very old kernels on this particular
stacked DSA setup, to ensure I'm not in fact introducing regressions.
Fixes: 845e0ebb4408 ("net: change addr_list_lock back to static key")
Suggested-by: Cong Wang <xiyou.wangcong@gmail.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-08 07:48:42 +08:00
|
|
|
out_unregister:
|
|
|
|
|
unregister_netdev(slave_dev);
|
2017-09-26 06:55:53 +08:00
|
|
|
out_phy:
|
2018-05-11 04:17:36 +08:00
|
|
|
rtnl_lock();
|
|
|
|
|
phylink_disconnect_phy(p->dp->pl);
|
|
|
|
|
rtnl_unlock();
|
|
|
|
|
phylink_destroy(p->dp->pl);
|
2020-04-21 21:41:08 +08:00
|
|
|
out_gcells:
|
|
|
|
|
gro_cells_destroy(&p->gcells);
|
2017-09-26 06:55:53 +08:00
|
|
|
out_free:
|
2020-11-08 04:49:46 +08:00
|
|
|
free_percpu(slave_dev->tstats);
|
2017-09-26 06:55:53 +08:00
|
|
|
free_netdev(slave_dev);
|
2017-10-16 23:12:18 +08:00
|
|
|
port->slave = NULL;
|
2017-09-26 06:55:53 +08:00
|
|
|
return ret;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 21:44:02 +08:00
|
|
|
}
|
2015-02-25 05:15:33 +08:00
|
|
|
|
2015-12-07 20:57:35 +08:00
|
|
|
void dsa_slave_destroy(struct net_device *slave_dev)
|
|
|
|
|
{
|
net: dsa: link interfaces with the DSA master to get rid of lockdep warnings
Since commit 845e0ebb4408 ("net: change addr_list_lock back to static
key"), cascaded DSA setups (DSA switch port as DSA master for another
DSA switch port) are emitting this lockdep warning:
============================================
WARNING: possible recursive locking detected
5.8.0-rc1-00133-g923e4b5032dd-dirty #208 Not tainted
--------------------------------------------
dhcpcd/323 is trying to acquire lock:
ffff000066dd4268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
but task is already holding lock:
ffff00006608c268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(&dsa_master_addr_list_lock_key/1);
lock(&dsa_master_addr_list_lock_key/1);
*** DEADLOCK ***
May be due to missing lock nesting notation
3 locks held by dhcpcd/323:
#0: ffffdbd1381dda18 (rtnl_mutex){+.+.}-{3:3}, at: rtnl_lock+0x24/0x30
#1: ffff00006614b268 (_xmit_ETHER){+...}-{2:2}, at: dev_set_rx_mode+0x28/0x48
#2: ffff00006608c268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
stack backtrace:
Call trace:
dump_backtrace+0x0/0x1e0
show_stack+0x20/0x30
dump_stack+0xec/0x158
__lock_acquire+0xca0/0x2398
lock_acquire+0xe8/0x440
_raw_spin_lock_nested+0x64/0x90
dev_mc_sync+0x44/0x90
dsa_slave_set_rx_mode+0x34/0x50
__dev_set_rx_mode+0x60/0xa0
dev_mc_sync+0x84/0x90
dsa_slave_set_rx_mode+0x34/0x50
__dev_set_rx_mode+0x60/0xa0
dev_set_rx_mode+0x30/0x48
__dev_open+0x10c/0x180
__dev_change_flags+0x170/0x1c8
dev_change_flags+0x2c/0x70
devinet_ioctl+0x774/0x878
inet_ioctl+0x348/0x3b0
sock_do_ioctl+0x50/0x310
sock_ioctl+0x1f8/0x580
ksys_ioctl+0xb0/0xf0
__arm64_sys_ioctl+0x28/0x38
el0_svc_common.constprop.0+0x7c/0x180
do_el0_svc+0x2c/0x98
el0_sync_handler+0x9c/0x1b8
el0_sync+0x158/0x180
Since DSA never made use of the netdev API for describing links between
upper devices and lower devices, the dev->lower_level value of a DSA
switch interface would be 1, which would warn when it is a DSA master.
We can use netdev_upper_dev_link() to describe the relationship between
a DSA slave and a DSA master. To be precise, a DSA "slave" (switch port)
is an "upper" to a DSA "master" (host port). The relationship is "many
uppers to one lower", like in the case of VLAN. So, for that reason, we
use the same function as VLAN uses.
There might be a chance that somebody will try to take hold of this
interface and use it immediately after register_netdev() and before
netdev_upper_dev_link(). To avoid that, we do the registration and
linkage while holding the RTNL, and we use the RTNL-locked cousin of
register_netdev(), which is register_netdevice().
Since this warning was not there when lockdep was using dynamic keys for
addr_list_lock, we are blaming the lockdep patch itself. The network
stack _has_ been using static lockdep keys before, and it _is_ likely
that stacked DSA setups have been triggering these lockdep warnings
since forever, however I can't test very old kernels on this particular
stacked DSA setup, to ensure I'm not in fact introducing regressions.
Fixes: 845e0ebb4408 ("net: change addr_list_lock back to static key")
Suggested-by: Cong Wang <xiyou.wangcong@gmail.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-08 07:48:42 +08:00
|
|
|
struct net_device *master = dsa_slave_to_master(slave_dev);
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(slave_dev);
|
2015-12-07 20:57:35 +08:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(slave_dev);
|
|
|
|
|
|
|
|
|
|
netif_carrier_off(slave_dev);
|
2018-05-11 04:17:36 +08:00
|
|
|
rtnl_lock();
|
net: dsa: link interfaces with the DSA master to get rid of lockdep warnings
Since commit 845e0ebb4408 ("net: change addr_list_lock back to static
key"), cascaded DSA setups (DSA switch port as DSA master for another
DSA switch port) are emitting this lockdep warning:
============================================
WARNING: possible recursive locking detected
5.8.0-rc1-00133-g923e4b5032dd-dirty #208 Not tainted
--------------------------------------------
dhcpcd/323 is trying to acquire lock:
ffff000066dd4268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
but task is already holding lock:
ffff00006608c268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(&dsa_master_addr_list_lock_key/1);
lock(&dsa_master_addr_list_lock_key/1);
*** DEADLOCK ***
May be due to missing lock nesting notation
3 locks held by dhcpcd/323:
#0: ffffdbd1381dda18 (rtnl_mutex){+.+.}-{3:3}, at: rtnl_lock+0x24/0x30
#1: ffff00006614b268 (_xmit_ETHER){+...}-{2:2}, at: dev_set_rx_mode+0x28/0x48
#2: ffff00006608c268 (&dsa_master_addr_list_lock_key/1){+...}-{2:2}, at: dev_mc_sync+0x44/0x90
stack backtrace:
Call trace:
dump_backtrace+0x0/0x1e0
show_stack+0x20/0x30
dump_stack+0xec/0x158
__lock_acquire+0xca0/0x2398
lock_acquire+0xe8/0x440
_raw_spin_lock_nested+0x64/0x90
dev_mc_sync+0x44/0x90
dsa_slave_set_rx_mode+0x34/0x50
__dev_set_rx_mode+0x60/0xa0
dev_mc_sync+0x84/0x90
dsa_slave_set_rx_mode+0x34/0x50
__dev_set_rx_mode+0x60/0xa0
dev_set_rx_mode+0x30/0x48
__dev_open+0x10c/0x180
__dev_change_flags+0x170/0x1c8
dev_change_flags+0x2c/0x70
devinet_ioctl+0x774/0x878
inet_ioctl+0x348/0x3b0
sock_do_ioctl+0x50/0x310
sock_ioctl+0x1f8/0x580
ksys_ioctl+0xb0/0xf0
__arm64_sys_ioctl+0x28/0x38
el0_svc_common.constprop.0+0x7c/0x180
do_el0_svc+0x2c/0x98
el0_sync_handler+0x9c/0x1b8
el0_sync+0x158/0x180
Since DSA never made use of the netdev API for describing links between
upper devices and lower devices, the dev->lower_level value of a DSA
switch interface would be 1, which would warn when it is a DSA master.
We can use netdev_upper_dev_link() to describe the relationship between
a DSA slave and a DSA master. To be precise, a DSA "slave" (switch port)
is an "upper" to a DSA "master" (host port). The relationship is "many
uppers to one lower", like in the case of VLAN. So, for that reason, we
use the same function as VLAN uses.
There might be a chance that somebody will try to take hold of this
interface and use it immediately after register_netdev() and before
netdev_upper_dev_link(). To avoid that, we do the registration and
linkage while holding the RTNL, and we use the RTNL-locked cousin of
register_netdev(), which is register_netdevice().
Since this warning was not there when lockdep was using dynamic keys for
addr_list_lock, we are blaming the lockdep patch itself. The network
stack _has_ been using static lockdep keys before, and it _is_ likely
that stacked DSA setups have been triggering these lockdep warnings
since forever, however I can't test very old kernels on this particular
stacked DSA setup, to ensure I'm not in fact introducing regressions.
Fixes: 845e0ebb4408 ("net: change addr_list_lock back to static key")
Suggested-by: Cong Wang <xiyou.wangcong@gmail.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-08 07:48:42 +08:00
|
|
|
netdev_upper_dev_unlink(master, slave_dev);
|
|
|
|
|
unregister_netdevice(slave_dev);
|
2018-05-11 04:17:36 +08:00
|
|
|
phylink_disconnect_phy(dp->pl);
|
|
|
|
|
rtnl_unlock();
|
2016-11-29 02:25:09 +08:00
|
|
|
|
2018-05-11 04:17:36 +08:00
|
|
|
phylink_destroy(dp->pl);
|
2020-04-21 21:41:08 +08:00
|
|
|
gro_cells_destroy(&p->gcells);
|
2020-11-08 04:49:46 +08:00
|
|
|
free_percpu(slave_dev->tstats);
|
2015-12-07 20:57:35 +08:00
|
|
|
free_netdev(slave_dev);
|
|
|
|
|
}
|
|
|
|
|
|
2020-01-08 13:06:05 +08:00
|
|
|
bool dsa_slave_dev_check(const struct net_device *dev)
|
2015-02-25 05:15:33 +08:00
|
|
|
{
|
|
|
|
|
return dev->netdev_ops == &dsa_slave_netdev_ops;
|
|
|
|
|
}
|
2021-01-07 09:24:01 +08:00
|
|
|
EXPORT_SYMBOL_GPL(dsa_slave_dev_check);
|
2015-02-25 05:15:33 +08:00
|
|
|
|
2017-02-04 02:20:17 +08:00
|
|
|
static int dsa_slave_changeupper(struct net_device *dev,
|
|
|
|
|
struct netdev_notifier_changeupper_info *info)
|
2015-02-25 05:15:33 +08:00
|
|
|
{
|
2017-10-16 23:12:15 +08:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2017-02-04 02:20:17 +08:00
|
|
|
int err = NOTIFY_DONE;
|
2015-02-25 05:15:33 +08:00
|
|
|
|
2017-02-04 02:20:17 +08:00
|
|
|
if (netif_is_bridge_master(info->upper_dev)) {
|
|
|
|
|
if (info->linking) {
|
2017-05-20 05:00:38 +08:00
|
|
|
err = dsa_port_bridge_join(dp, info->upper_dev);
|
net: dsa: implement auto-normalization of MTU for bridge hardware datapath
Many switches don't have an explicit knob for configuring the MTU
(maximum transmission unit per interface). Instead, they do the
length-based packet admission checks on the ingress interface, for
reasons that are easy to understand (why would you accept a packet in
the queuing subsystem if you know you're going to drop it anyway).
So it is actually the MRU that these switches permit configuring.
In Linux there only exists the IFLA_MTU netlink attribute and the
associated dev_set_mtu function. The comments like to play blind and say
that it's changing the "maximum transfer unit", which is to say that
there isn't any directionality in the meaning of the MTU word. So that
is the interpretation that this patch is giving to things: MTU == MRU.
When 2 interfaces having different MTUs are bridged, the bridge driver
MTU auto-adjustment logic kicks in: what br_mtu_auto_adjust() does is it
adjusts the MTU of the bridge net device itself (and not that of the
slave net devices) to the minimum value of all slave interfaces, in
order for forwarded packets to not exceed the MTU regardless of the
interface they are received and send on.
The idea behind this behavior, and why the slave MTUs are not adjusted,
is that normal termination from Linux over the L2 forwarding domain
should happen over the bridge net device, which _is_ properly limited by
the minimum MTU. And termination over individual slave devices is
possible even if those are bridged. But that is not "forwarding", so
there's no reason to do normalization there, since only a single
interface sees that packet.
The problem with those switches that can only control the MRU is with
the offloaded data path, where a packet received on an interface with
MRU 9000 would still be forwarded to an interface with MRU 1500. And the
br_mtu_auto_adjust() function does not really help, since the MTU
configured on the bridge net device is ignored.
In order to enforce the de-facto MTU == MRU rule for these switches, we
need to do MTU normalization, which means: in order for no packet larger
than the MTU configured on this port to be sent, then we need to limit
the MRU on all ports that this packet could possibly come from. AKA
since we are configuring the MRU via MTU, it means that all ports within
a bridge forwarding domain should have the same MTU.
And that is exactly what this patch is trying to do.
>From an implementation perspective, we try to follow the intent of the
user, otherwise there is a risk that we might livelock them (they try to
change the MTU on an already-bridged interface, but we just keep
changing it back in an attempt to keep the MTU normalized). So the MTU
that the bridge is normalized to is either:
- The most recently changed one:
ip link set dev swp0 master br0
ip link set dev swp1 master br0
ip link set dev swp0 mtu 1400
This sequence will make swp1 inherit MTU 1400 from swp0.
- The one of the most recently added interface to the bridge:
ip link set dev swp0 master br0
ip link set dev swp1 mtu 1400
ip link set dev swp1 master br0
The above sequence will make swp0 inherit MTU 1400 as well.
Suggested-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-28 03:55:43 +08:00
|
|
|
if (!err)
|
|
|
|
|
dsa_bridge_mtu_normalization(dp);
|
2017-02-04 02:20:17 +08:00
|
|
|
err = notifier_from_errno(err);
|
|
|
|
|
} else {
|
2017-05-20 05:00:38 +08:00
|
|
|
dsa_port_bridge_leave(dp, info->upper_dev);
|
2017-02-04 02:20:17 +08:00
|
|
|
err = NOTIFY_OK;
|
2016-03-14 04:21:34 +08:00
|
|
|
}
|
|
|
|
|
}
|
2015-02-25 05:15:33 +08:00
|
|
|
|
2017-02-04 02:20:17 +08:00
|
|
|
return err;
|
2016-03-14 04:21:34 +08:00
|
|
|
}
|
2015-02-25 05:15:33 +08:00
|
|
|
|
2020-09-21 08:10:24 +08:00
|
|
|
static int
|
|
|
|
|
dsa_prevent_bridging_8021q_upper(struct net_device *dev,
|
|
|
|
|
struct netdev_notifier_changeupper_info *info)
|
2019-02-21 06:35:38 +08:00
|
|
|
{
|
|
|
|
|
struct netlink_ext_ack *ext_ack;
|
|
|
|
|
struct net_device *slave;
|
|
|
|
|
struct dsa_port *dp;
|
|
|
|
|
|
|
|
|
|
ext_ack = netdev_notifier_info_to_extack(&info->info);
|
|
|
|
|
|
|
|
|
|
if (!is_vlan_dev(dev))
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
|
|
slave = vlan_dev_real_dev(dev);
|
|
|
|
|
if (!dsa_slave_dev_check(slave))
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
|
|
dp = dsa_slave_to_port(slave);
|
|
|
|
|
if (!dp->bridge_dev)
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
|
|
/* Deny enslaving a VLAN device into a VLAN-aware bridge */
|
|
|
|
|
if (br_vlan_enabled(dp->bridge_dev) &&
|
|
|
|
|
netif_is_bridge_master(info->upper_dev) && info->linking) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(ext_ack,
|
|
|
|
|
"Cannot enslave VLAN device into VLAN aware bridge");
|
|
|
|
|
return notifier_from_errno(-EINVAL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-21 08:10:25 +08:00
|
|
|
static int
|
|
|
|
|
dsa_slave_check_8021q_upper(struct net_device *dev,
|
|
|
|
|
struct netdev_notifier_changeupper_info *info)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
struct net_device *br = dp->bridge_dev;
|
|
|
|
|
struct bridge_vlan_info br_info;
|
|
|
|
|
struct netlink_ext_ack *extack;
|
|
|
|
|
int err = NOTIFY_DONE;
|
|
|
|
|
u16 vid;
|
|
|
|
|
|
2020-09-21 08:10:28 +08:00
|
|
|
if (!br || !br_vlan_enabled(br))
|
2020-09-21 08:10:25 +08:00
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
|
|
extack = netdev_notifier_info_to_extack(&info->info);
|
|
|
|
|
vid = vlan_dev_vlan_id(info->upper_dev);
|
|
|
|
|
|
|
|
|
|
/* br_vlan_get_info() returns -EINVAL or -ENOENT if the
|
|
|
|
|
* device, respectively the VID is not found, returning
|
|
|
|
|
* 0 means success, which is a failure for us here.
|
|
|
|
|
*/
|
|
|
|
|
err = br_vlan_get_info(br, vid, &br_info);
|
|
|
|
|
if (err == 0) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack,
|
|
|
|
|
"This VLAN is already configured by the bridge");
|
|
|
|
|
return notifier_from_errno(-EBUSY);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-04 02:20:16 +08:00
|
|
|
static int dsa_slave_netdevice_event(struct notifier_block *nb,
|
|
|
|
|
unsigned long event, void *ptr)
|
2016-03-14 04:21:34 +08:00
|
|
|
{
|
|
|
|
|
struct net_device *dev = netdev_notifier_info_to_dev(ptr);
|
|
|
|
|
|
2020-09-21 08:10:23 +08:00
|
|
|
switch (event) {
|
2020-09-21 08:10:25 +08:00
|
|
|
case NETDEV_PRECHANGEUPPER: {
|
|
|
|
|
struct netdev_notifier_changeupper_info *info = ptr;
|
2020-11-03 15:10:55 +08:00
|
|
|
struct dsa_switch *ds;
|
|
|
|
|
struct dsa_port *dp;
|
|
|
|
|
int err;
|
2020-09-21 08:10:25 +08:00
|
|
|
|
2019-02-21 06:35:38 +08:00
|
|
|
if (!dsa_slave_dev_check(dev))
|
2020-09-21 08:10:24 +08:00
|
|
|
return dsa_prevent_bridging_8021q_upper(dev, ptr);
|
2020-09-21 08:10:25 +08:00
|
|
|
|
2020-11-03 15:10:55 +08:00
|
|
|
dp = dsa_slave_to_port(dev);
|
|
|
|
|
ds = dp->ds;
|
|
|
|
|
|
|
|
|
|
if (ds->ops->port_prechangeupper) {
|
|
|
|
|
err = ds->ops->port_prechangeupper(ds, dp->index, info);
|
|
|
|
|
if (err)
|
|
|
|
|
return notifier_from_errno(err);
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-21 08:10:25 +08:00
|
|
|
if (is_vlan_dev(info->upper_dev))
|
|
|
|
|
return dsa_slave_check_8021q_upper(dev, ptr);
|
2020-09-21 08:10:23 +08:00
|
|
|
break;
|
2020-09-21 08:10:25 +08:00
|
|
|
}
|
2020-09-21 08:10:23 +08:00
|
|
|
case NETDEV_CHANGEUPPER:
|
|
|
|
|
if (!dsa_slave_dev_check(dev))
|
|
|
|
|
return NOTIFY_DONE;
|
2017-02-04 02:20:17 +08:00
|
|
|
|
|
|
|
|
return dsa_slave_changeupper(dev, ptr);
|
2019-02-21 06:35:38 +08:00
|
|
|
}
|
2015-02-25 05:15:33 +08:00
|
|
|
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
}
|
2017-02-04 02:20:16 +08:00
|
|
|
|
2021-01-06 17:51:32 +08:00
|
|
|
static void
|
|
|
|
|
dsa_fdb_offload_notify(struct dsa_switchdev_event_work *switchdev_work)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_switch *ds = switchdev_work->ds;
|
|
|
|
|
struct switchdev_notifier_fdb_info info;
|
|
|
|
|
struct dsa_port *dp;
|
|
|
|
|
|
|
|
|
|
if (!dsa_is_user_port(ds, switchdev_work->port))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
info.addr = switchdev_work->addr;
|
|
|
|
|
info.vid = switchdev_work->vid;
|
|
|
|
|
info.offloaded = true;
|
|
|
|
|
dp = dsa_to_port(ds, switchdev_work->port);
|
|
|
|
|
call_switchdev_notifiers(SWITCHDEV_FDB_OFFLOADED,
|
|
|
|
|
dp->slave, &info.info, NULL);
|
|
|
|
|
}
|
2017-08-06 21:15:42 +08:00
|
|
|
|
|
|
|
|
static void dsa_slave_switchdev_event_work(struct work_struct *work)
|
|
|
|
|
{
|
|
|
|
|
struct dsa_switchdev_event_work *switchdev_work =
|
|
|
|
|
container_of(work, struct dsa_switchdev_event_work, work);
|
2021-01-06 17:51:32 +08:00
|
|
|
struct dsa_switch *ds = switchdev_work->ds;
|
|
|
|
|
struct dsa_port *dp;
|
2017-08-06 21:15:42 +08:00
|
|
|
int err;
|
|
|
|
|
|
2021-01-06 17:51:32 +08:00
|
|
|
dp = dsa_to_port(ds, switchdev_work->port);
|
|
|
|
|
|
2017-08-06 21:15:42 +08:00
|
|
|
rtnl_lock();
|
|
|
|
|
switch (switchdev_work->event) {
|
|
|
|
|
case SWITCHDEV_FDB_ADD_TO_DEVICE:
|
2021-01-06 17:51:32 +08:00
|
|
|
err = dsa_port_fdb_add(dp, switchdev_work->addr,
|
|
|
|
|
switchdev_work->vid);
|
2017-08-06 21:15:42 +08:00
|
|
|
if (err) {
|
2021-01-06 17:51:32 +08:00
|
|
|
dev_err(ds->dev,
|
|
|
|
|
"port %d failed to add %pM vid %d to fdb: %d\n",
|
|
|
|
|
dp->index, switchdev_work->addr,
|
|
|
|
|
switchdev_work->vid, err);
|
2017-08-06 21:15:42 +08:00
|
|
|
break;
|
|
|
|
|
}
|
2021-01-06 17:51:32 +08:00
|
|
|
dsa_fdb_offload_notify(switchdev_work);
|
2017-08-06 21:15:42 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case SWITCHDEV_FDB_DEL_TO_DEVICE:
|
2021-01-06 17:51:32 +08:00
|
|
|
err = dsa_port_fdb_del(dp, switchdev_work->addr,
|
|
|
|
|
switchdev_work->vid);
|
2017-08-06 21:15:42 +08:00
|
|
|
if (err) {
|
2021-01-06 17:51:32 +08:00
|
|
|
dev_err(ds->dev,
|
|
|
|
|
"port %d failed to delete %pM vid %d from fdb: %d\n",
|
|
|
|
|
dp->index, switchdev_work->addr,
|
|
|
|
|
switchdev_work->vid, err);
|
2017-08-06 21:15:42 +08:00
|
|
|
}
|
2021-01-06 17:51:31 +08:00
|
|
|
|
2017-08-06 21:15:42 +08:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
rtnl_unlock();
|
|
|
|
|
|
|
|
|
|
kfree(switchdev_work);
|
2021-01-06 17:51:32 +08:00
|
|
|
if (dsa_is_user_port(ds, dp->index))
|
|
|
|
|
dev_put(dp->slave);
|
2017-08-06 21:15:42 +08:00
|
|
|
}
|
|
|
|
|
|
net: dsa: listen for SWITCHDEV_{FDB,DEL}_ADD_TO_DEVICE on foreign bridge neighbors
Some DSA switches (and not only) cannot learn source MAC addresses from
packets injected from the CPU. They only perform hardware address
learning from inbound traffic.
This can be problematic when we have a bridge spanning some DSA switch
ports and some non-DSA ports (which we'll call "foreign interfaces" from
DSA's perspective).
There are 2 classes of problems created by the lack of learning on
CPU-injected traffic:
- excessive flooding, due to the fact that DSA treats those addresses as
unknown
- the risk of stale routes, which can lead to temporary packet loss
To illustrate the second class, consider the following situation, which
is common in production equipment (wireless access points, where there
is a WLAN interface and an Ethernet switch, and these form a single
bridging domain).
AP 1:
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
| ^ ^
| | |
| | |
| Client A Client B
|
|
|
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
AP 2
- br0 of AP 1 will know that Clients A and B are reachable via wlan0
- the hardware fdb of a DSA switch driver today is not kept in sync with
the software entries on other bridge ports, so it will not know that
clients A and B are reachable via the CPU port UNLESS the hardware
switch itself performs SA learning from traffic injected from the CPU.
Nonetheless, a substantial number of switches don't.
- the hardware fdb of the DSA switch on AP 2 may autonomously learn that
Client A and B are reachable through swp0. Therefore, the software br0
of AP 2 also may or may not learn this. In the example we're
illustrating, some Ethernet traffic has been going on, and br0 from AP
2 has indeed learnt that it can reach Client B through swp0.
One of the wireless clients, say Client B, disconnects from AP 1 and
roams to AP 2. The topology now looks like this:
AP 1:
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
| ^
| |
| Client A
|
|
| Client B
| |
| v
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
AP 2
- br0 of AP 1 still knows that Client A is reachable via wlan0 (no change)
- br0 of AP 1 will (possibly) know that Client B has left wlan0. There
are cases where it might never find out though. Either way, DSA today
does not process that notification in any way.
- the hardware FDB of the DSA switch on AP 1 may learn autonomously that
Client B can be reached via swp0, if it receives any packet with
Client 1's source MAC address over Ethernet.
- the hardware FDB of the DSA switch on AP 2 still thinks that Client B
can be reached via swp0. It does not know that it has roamed to wlan0,
because it doesn't perform SA learning from the CPU port.
Now Client A contacts Client B.
AP 1 routes the packet fine towards swp0 and delivers it on the Ethernet
segment.
AP 2 sees a frame on swp0 and its fdb says that the destination is swp0.
Hairpinning is disabled => drop.
This problem comes from the fact that these switches have a 'blind spot'
for addresses coming from software bridging. The generic solution is not
to assume that hardware learning can be enabled somehow, but to listen
to more bridge learning events. It turns out that the bridge driver does
learn in software from all inbound frames, in __br_handle_local_finish.
A proper SWITCHDEV_FDB_ADD_TO_DEVICE notification is emitted for the
addresses serviced by the bridge on 'foreign' interfaces. The software
bridge also does the right thing on migration, by notifying that the old
entry is deleted, so that does not need to be special-cased in DSA. When
it is deleted, we just need to delete our static FDB entry towards the
CPU too, and wait.
The problem is that DSA currently only cares about SWITCHDEV_FDB_ADD_TO_DEVICE
events received on its own interfaces, such as static FDB entries.
Luckily we can change that, and DSA can listen to all switchdev FDB
add/del events in the system and figure out if those events were emitted
by a bridge that spans at least one of DSA's own ports. In case that is
true, DSA will also offload that address towards its own CPU port, in
the eventuality that there might be bridge clients attached to the DSA
switch who want to talk to the station connected to the foreign
interface.
In terms of implementation, we need to keep the fdb_info->added_by_user
check for the case where the switchdev event was targeted directly at a
DSA switch port. But we don't need to look at that flag for snooped
events. So the check is currently too late, we need to move it earlier.
This also simplifies the code a bit, since we avoid uselessly allocating
and freeing switchdev_work.
We could probably do some improvements in the future. For example,
multi-bridge support is rudimentary at the moment. If there are two
bridges spanning a DSA switch's ports, and both of them need to service
the same MAC address, then what will happen is that the migration of one
of those stations will trigger the deletion of the FDB entry from the
CPU port while it is still used by other bridge. That could be improved
with reference counting but is left for another time.
This behavior needs to be enabled at driver level by setting
ds->assisted_learning_on_cpu_port = true. This is because we don't want
to inflict a potential performance penalty (accesses through
MDIO/I2C/SPI are expensive) to hardware that really doesn't need it
because address learning on the CPU port works there.
Reported-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-01-06 17:51:35 +08:00
|
|
|
static int dsa_lower_dev_walk(struct net_device *lower_dev,
|
|
|
|
|
struct netdev_nested_priv *priv)
|
|
|
|
|
{
|
|
|
|
|
if (dsa_slave_dev_check(lower_dev)) {
|
|
|
|
|
priv->data = (void *)netdev_priv(lower_dev);
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct dsa_slave_priv *dsa_slave_dev_lower_find(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct netdev_nested_priv priv = {
|
|
|
|
|
.data = NULL,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
netdev_walk_all_lower_dev_rcu(dev, dsa_lower_dev_walk, &priv);
|
|
|
|
|
|
|
|
|
|
return (struct dsa_slave_priv *)priv.data;
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-06 21:15:42 +08:00
|
|
|
/* Called under rcu_read_lock() */
|
|
|
|
|
static int dsa_slave_switchdev_event(struct notifier_block *unused,
|
|
|
|
|
unsigned long event, void *ptr)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
|
2021-01-06 17:51:32 +08:00
|
|
|
const struct switchdev_notifier_fdb_info *fdb_info;
|
2017-08-06 21:15:42 +08:00
|
|
|
struct dsa_switchdev_event_work *switchdev_work;
|
2021-01-06 17:51:32 +08:00
|
|
|
struct dsa_port *dp;
|
2019-06-15 01:49:22 +08:00
|
|
|
int err;
|
|
|
|
|
|
2021-01-06 17:51:33 +08:00
|
|
|
switch (event) {
|
|
|
|
|
case SWITCHDEV_PORT_ATTR_SET:
|
2019-06-15 01:49:22 +08:00
|
|
|
err = switchdev_handle_port_attr_set(dev, ptr,
|
|
|
|
|
dsa_slave_dev_check,
|
|
|
|
|
dsa_slave_port_attr_set);
|
|
|
|
|
return notifier_from_errno(err);
|
2021-01-06 17:51:33 +08:00
|
|
|
case SWITCHDEV_FDB_ADD_TO_DEVICE:
|
|
|
|
|
case SWITCHDEV_FDB_DEL_TO_DEVICE:
|
net: dsa: listen for SWITCHDEV_{FDB,DEL}_ADD_TO_DEVICE on foreign bridge neighbors
Some DSA switches (and not only) cannot learn source MAC addresses from
packets injected from the CPU. They only perform hardware address
learning from inbound traffic.
This can be problematic when we have a bridge spanning some DSA switch
ports and some non-DSA ports (which we'll call "foreign interfaces" from
DSA's perspective).
There are 2 classes of problems created by the lack of learning on
CPU-injected traffic:
- excessive flooding, due to the fact that DSA treats those addresses as
unknown
- the risk of stale routes, which can lead to temporary packet loss
To illustrate the second class, consider the following situation, which
is common in production equipment (wireless access points, where there
is a WLAN interface and an Ethernet switch, and these form a single
bridging domain).
AP 1:
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
| ^ ^
| | |
| | |
| Client A Client B
|
|
|
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
AP 2
- br0 of AP 1 will know that Clients A and B are reachable via wlan0
- the hardware fdb of a DSA switch driver today is not kept in sync with
the software entries on other bridge ports, so it will not know that
clients A and B are reachable via the CPU port UNLESS the hardware
switch itself performs SA learning from traffic injected from the CPU.
Nonetheless, a substantial number of switches don't.
- the hardware fdb of the DSA switch on AP 2 may autonomously learn that
Client A and B are reachable through swp0. Therefore, the software br0
of AP 2 also may or may not learn this. In the example we're
illustrating, some Ethernet traffic has been going on, and br0 from AP
2 has indeed learnt that it can reach Client B through swp0.
One of the wireless clients, say Client B, disconnects from AP 1 and
roams to AP 2. The topology now looks like this:
AP 1:
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
| ^
| |
| Client A
|
|
| Client B
| |
| v
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
AP 2
- br0 of AP 1 still knows that Client A is reachable via wlan0 (no change)
- br0 of AP 1 will (possibly) know that Client B has left wlan0. There
are cases where it might never find out though. Either way, DSA today
does not process that notification in any way.
- the hardware FDB of the DSA switch on AP 1 may learn autonomously that
Client B can be reached via swp0, if it receives any packet with
Client 1's source MAC address over Ethernet.
- the hardware FDB of the DSA switch on AP 2 still thinks that Client B
can be reached via swp0. It does not know that it has roamed to wlan0,
because it doesn't perform SA learning from the CPU port.
Now Client A contacts Client B.
AP 1 routes the packet fine towards swp0 and delivers it on the Ethernet
segment.
AP 2 sees a frame on swp0 and its fdb says that the destination is swp0.
Hairpinning is disabled => drop.
This problem comes from the fact that these switches have a 'blind spot'
for addresses coming from software bridging. The generic solution is not
to assume that hardware learning can be enabled somehow, but to listen
to more bridge learning events. It turns out that the bridge driver does
learn in software from all inbound frames, in __br_handle_local_finish.
A proper SWITCHDEV_FDB_ADD_TO_DEVICE notification is emitted for the
addresses serviced by the bridge on 'foreign' interfaces. The software
bridge also does the right thing on migration, by notifying that the old
entry is deleted, so that does not need to be special-cased in DSA. When
it is deleted, we just need to delete our static FDB entry towards the
CPU too, and wait.
The problem is that DSA currently only cares about SWITCHDEV_FDB_ADD_TO_DEVICE
events received on its own interfaces, such as static FDB entries.
Luckily we can change that, and DSA can listen to all switchdev FDB
add/del events in the system and figure out if those events were emitted
by a bridge that spans at least one of DSA's own ports. In case that is
true, DSA will also offload that address towards its own CPU port, in
the eventuality that there might be bridge clients attached to the DSA
switch who want to talk to the station connected to the foreign
interface.
In terms of implementation, we need to keep the fdb_info->added_by_user
check for the case where the switchdev event was targeted directly at a
DSA switch port. But we don't need to look at that flag for snooped
events. So the check is currently too late, we need to move it earlier.
This also simplifies the code a bit, since we avoid uselessly allocating
and freeing switchdev_work.
We could probably do some improvements in the future. For example,
multi-bridge support is rudimentary at the moment. If there are two
bridges spanning a DSA switch's ports, and both of them need to service
the same MAC address, then what will happen is that the migration of one
of those stations will trigger the deletion of the FDB entry from the
CPU port while it is still used by other bridge. That could be improved
with reference counting but is left for another time.
This behavior needs to be enabled at driver level by setting
ds->assisted_learning_on_cpu_port = true. This is because we don't want
to inflict a potential performance penalty (accesses through
MDIO/I2C/SPI are expensive) to hardware that really doesn't need it
because address learning on the CPU port works there.
Reported-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-01-06 17:51:35 +08:00
|
|
|
fdb_info = ptr;
|
2017-08-06 21:15:42 +08:00
|
|
|
|
net: dsa: listen for SWITCHDEV_{FDB,DEL}_ADD_TO_DEVICE on foreign bridge neighbors
Some DSA switches (and not only) cannot learn source MAC addresses from
packets injected from the CPU. They only perform hardware address
learning from inbound traffic.
This can be problematic when we have a bridge spanning some DSA switch
ports and some non-DSA ports (which we'll call "foreign interfaces" from
DSA's perspective).
There are 2 classes of problems created by the lack of learning on
CPU-injected traffic:
- excessive flooding, due to the fact that DSA treats those addresses as
unknown
- the risk of stale routes, which can lead to temporary packet loss
To illustrate the second class, consider the following situation, which
is common in production equipment (wireless access points, where there
is a WLAN interface and an Ethernet switch, and these form a single
bridging domain).
AP 1:
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
| ^ ^
| | |
| | |
| Client A Client B
|
|
|
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
AP 2
- br0 of AP 1 will know that Clients A and B are reachable via wlan0
- the hardware fdb of a DSA switch driver today is not kept in sync with
the software entries on other bridge ports, so it will not know that
clients A and B are reachable via the CPU port UNLESS the hardware
switch itself performs SA learning from traffic injected from the CPU.
Nonetheless, a substantial number of switches don't.
- the hardware fdb of the DSA switch on AP 2 may autonomously learn that
Client A and B are reachable through swp0. Therefore, the software br0
of AP 2 also may or may not learn this. In the example we're
illustrating, some Ethernet traffic has been going on, and br0 from AP
2 has indeed learnt that it can reach Client B through swp0.
One of the wireless clients, say Client B, disconnects from AP 1 and
roams to AP 2. The topology now looks like this:
AP 1:
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
| ^
| |
| Client A
|
|
| Client B
| |
| v
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
AP 2
- br0 of AP 1 still knows that Client A is reachable via wlan0 (no change)
- br0 of AP 1 will (possibly) know that Client B has left wlan0. There
are cases where it might never find out though. Either way, DSA today
does not process that notification in any way.
- the hardware FDB of the DSA switch on AP 1 may learn autonomously that
Client B can be reached via swp0, if it receives any packet with
Client 1's source MAC address over Ethernet.
- the hardware FDB of the DSA switch on AP 2 still thinks that Client B
can be reached via swp0. It does not know that it has roamed to wlan0,
because it doesn't perform SA learning from the CPU port.
Now Client A contacts Client B.
AP 1 routes the packet fine towards swp0 and delivers it on the Ethernet
segment.
AP 2 sees a frame on swp0 and its fdb says that the destination is swp0.
Hairpinning is disabled => drop.
This problem comes from the fact that these switches have a 'blind spot'
for addresses coming from software bridging. The generic solution is not
to assume that hardware learning can be enabled somehow, but to listen
to more bridge learning events. It turns out that the bridge driver does
learn in software from all inbound frames, in __br_handle_local_finish.
A proper SWITCHDEV_FDB_ADD_TO_DEVICE notification is emitted for the
addresses serviced by the bridge on 'foreign' interfaces. The software
bridge also does the right thing on migration, by notifying that the old
entry is deleted, so that does not need to be special-cased in DSA. When
it is deleted, we just need to delete our static FDB entry towards the
CPU too, and wait.
The problem is that DSA currently only cares about SWITCHDEV_FDB_ADD_TO_DEVICE
events received on its own interfaces, such as static FDB entries.
Luckily we can change that, and DSA can listen to all switchdev FDB
add/del events in the system and figure out if those events were emitted
by a bridge that spans at least one of DSA's own ports. In case that is
true, DSA will also offload that address towards its own CPU port, in
the eventuality that there might be bridge clients attached to the DSA
switch who want to talk to the station connected to the foreign
interface.
In terms of implementation, we need to keep the fdb_info->added_by_user
check for the case where the switchdev event was targeted directly at a
DSA switch port. But we don't need to look at that flag for snooped
events. So the check is currently too late, we need to move it earlier.
This also simplifies the code a bit, since we avoid uselessly allocating
and freeing switchdev_work.
We could probably do some improvements in the future. For example,
multi-bridge support is rudimentary at the moment. If there are two
bridges spanning a DSA switch's ports, and both of them need to service
the same MAC address, then what will happen is that the migration of one
of those stations will trigger the deletion of the FDB entry from the
CPU port while it is still used by other bridge. That could be improved
with reference counting but is left for another time.
This behavior needs to be enabled at driver level by setting
ds->assisted_learning_on_cpu_port = true. This is because we don't want
to inflict a potential performance penalty (accesses through
MDIO/I2C/SPI are expensive) to hardware that really doesn't need it
because address learning on the CPU port works there.
Reported-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-01-06 17:51:35 +08:00
|
|
|
if (dsa_slave_dev_check(dev)) {
|
|
|
|
|
if (!fdb_info->added_by_user)
|
|
|
|
|
return NOTIFY_OK;
|
|
|
|
|
|
|
|
|
|
dp = dsa_slave_to_port(dev);
|
|
|
|
|
} else {
|
|
|
|
|
/* Snoop addresses learnt on foreign interfaces
|
|
|
|
|
* bridged with us, for switches that don't
|
|
|
|
|
* automatically learn SA from CPU-injected traffic
|
|
|
|
|
*/
|
|
|
|
|
struct net_device *br_dev;
|
|
|
|
|
struct dsa_slave_priv *p;
|
|
|
|
|
|
|
|
|
|
br_dev = netdev_master_upper_dev_get_rcu(dev);
|
|
|
|
|
if (!br_dev)
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
|
|
if (!netif_is_bridge_master(br_dev))
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
|
|
p = dsa_slave_dev_lower_find(br_dev);
|
|
|
|
|
if (!p)
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
|
|
dp = p->dp->cpu_dp;
|
|
|
|
|
|
|
|
|
|
if (!dp->ds->assisted_learning_on_cpu_port)
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
}
|
2021-01-06 17:51:32 +08:00
|
|
|
|
2021-01-06 17:51:34 +08:00
|
|
|
if (!dp->ds->ops->port_fdb_add || !dp->ds->ops->port_fdb_del)
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
2021-01-06 17:51:33 +08:00
|
|
|
switchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC);
|
|
|
|
|
if (!switchdev_work)
|
|
|
|
|
return NOTIFY_BAD;
|
2017-08-06 21:15:42 +08:00
|
|
|
|
2021-01-06 17:51:33 +08:00
|
|
|
INIT_WORK(&switchdev_work->work,
|
|
|
|
|
dsa_slave_switchdev_event_work);
|
|
|
|
|
switchdev_work->ds = dp->ds;
|
|
|
|
|
switchdev_work->port = dp->index;
|
|
|
|
|
switchdev_work->event = event;
|
2017-08-06 21:15:42 +08:00
|
|
|
|
2021-01-06 17:51:32 +08:00
|
|
|
ether_addr_copy(switchdev_work->addr,
|
|
|
|
|
fdb_info->addr);
|
|
|
|
|
switchdev_work->vid = fdb_info->vid;
|
|
|
|
|
|
net: dsa: listen for SWITCHDEV_{FDB,DEL}_ADD_TO_DEVICE on foreign bridge neighbors
Some DSA switches (and not only) cannot learn source MAC addresses from
packets injected from the CPU. They only perform hardware address
learning from inbound traffic.
This can be problematic when we have a bridge spanning some DSA switch
ports and some non-DSA ports (which we'll call "foreign interfaces" from
DSA's perspective).
There are 2 classes of problems created by the lack of learning on
CPU-injected traffic:
- excessive flooding, due to the fact that DSA treats those addresses as
unknown
- the risk of stale routes, which can lead to temporary packet loss
To illustrate the second class, consider the following situation, which
is common in production equipment (wireless access points, where there
is a WLAN interface and an Ethernet switch, and these form a single
bridging domain).
AP 1:
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
| ^ ^
| | |
| | |
| Client A Client B
|
|
|
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
AP 2
- br0 of AP 1 will know that Clients A and B are reachable via wlan0
- the hardware fdb of a DSA switch driver today is not kept in sync with
the software entries on other bridge ports, so it will not know that
clients A and B are reachable via the CPU port UNLESS the hardware
switch itself performs SA learning from traffic injected from the CPU.
Nonetheless, a substantial number of switches don't.
- the hardware fdb of the DSA switch on AP 2 may autonomously learn that
Client A and B are reachable through swp0. Therefore, the software br0
of AP 2 also may or may not learn this. In the example we're
illustrating, some Ethernet traffic has been going on, and br0 from AP
2 has indeed learnt that it can reach Client B through swp0.
One of the wireless clients, say Client B, disconnects from AP 1 and
roams to AP 2. The topology now looks like this:
AP 1:
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
| ^
| |
| Client A
|
|
| Client B
| |
| v
+------------+ +------------+ +------------+ +------------+ +------------+
| swp0 | | swp1 | | swp2 | | swp3 | | wlan0 |
+------------+ +------------+ +------------+ +------------+ +------------+
+------------------------------------------------------------------------+
| br0 |
+------------------------------------------------------------------------+
AP 2
- br0 of AP 1 still knows that Client A is reachable via wlan0 (no change)
- br0 of AP 1 will (possibly) know that Client B has left wlan0. There
are cases where it might never find out though. Either way, DSA today
does not process that notification in any way.
- the hardware FDB of the DSA switch on AP 1 may learn autonomously that
Client B can be reached via swp0, if it receives any packet with
Client 1's source MAC address over Ethernet.
- the hardware FDB of the DSA switch on AP 2 still thinks that Client B
can be reached via swp0. It does not know that it has roamed to wlan0,
because it doesn't perform SA learning from the CPU port.
Now Client A contacts Client B.
AP 1 routes the packet fine towards swp0 and delivers it on the Ethernet
segment.
AP 2 sees a frame on swp0 and its fdb says that the destination is swp0.
Hairpinning is disabled => drop.
This problem comes from the fact that these switches have a 'blind spot'
for addresses coming from software bridging. The generic solution is not
to assume that hardware learning can be enabled somehow, but to listen
to more bridge learning events. It turns out that the bridge driver does
learn in software from all inbound frames, in __br_handle_local_finish.
A proper SWITCHDEV_FDB_ADD_TO_DEVICE notification is emitted for the
addresses serviced by the bridge on 'foreign' interfaces. The software
bridge also does the right thing on migration, by notifying that the old
entry is deleted, so that does not need to be special-cased in DSA. When
it is deleted, we just need to delete our static FDB entry towards the
CPU too, and wait.
The problem is that DSA currently only cares about SWITCHDEV_FDB_ADD_TO_DEVICE
events received on its own interfaces, such as static FDB entries.
Luckily we can change that, and DSA can listen to all switchdev FDB
add/del events in the system and figure out if those events were emitted
by a bridge that spans at least one of DSA's own ports. In case that is
true, DSA will also offload that address towards its own CPU port, in
the eventuality that there might be bridge clients attached to the DSA
switch who want to talk to the station connected to the foreign
interface.
In terms of implementation, we need to keep the fdb_info->added_by_user
check for the case where the switchdev event was targeted directly at a
DSA switch port. But we don't need to look at that flag for snooped
events. So the check is currently too late, we need to move it earlier.
This also simplifies the code a bit, since we avoid uselessly allocating
and freeing switchdev_work.
We could probably do some improvements in the future. For example,
multi-bridge support is rudimentary at the moment. If there are two
bridges spanning a DSA switch's ports, and both of them need to service
the same MAC address, then what will happen is that the migration of one
of those stations will trigger the deletion of the FDB entry from the
CPU port while it is still used by other bridge. That could be improved
with reference counting but is left for another time.
This behavior needs to be enabled at driver level by setting
ds->assisted_learning_on_cpu_port = true. This is because we don't want
to inflict a potential performance penalty (accesses through
MDIO/I2C/SPI are expensive) to hardware that really doesn't need it
because address learning on the CPU port works there.
Reported-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-01-06 17:51:35 +08:00
|
|
|
/* Hold a reference on the slave for dsa_fdb_offload_notify */
|
|
|
|
|
if (dsa_is_user_port(dp->ds, dp->index))
|
|
|
|
|
dev_hold(dev);
|
2021-01-06 17:51:33 +08:00
|
|
|
dsa_schedule_work(&switchdev_work->work);
|
2017-08-06 21:15:42 +08:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return NOTIFY_OK;
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-23 07:29:05 +08:00
|
|
|
static int dsa_slave_switchdev_blocking_event(struct notifier_block *unused,
|
|
|
|
|
unsigned long event, void *ptr)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
|
2019-06-15 01:49:22 +08:00
|
|
|
int err;
|
2018-11-23 07:29:05 +08:00
|
|
|
|
|
|
|
|
switch (event) {
|
2019-06-15 01:49:22 +08:00
|
|
|
case SWITCHDEV_PORT_OBJ_ADD:
|
|
|
|
|
err = switchdev_handle_port_obj_add(dev, ptr,
|
|
|
|
|
dsa_slave_dev_check,
|
|
|
|
|
dsa_slave_port_obj_add);
|
|
|
|
|
return notifier_from_errno(err);
|
2018-11-23 07:29:05 +08:00
|
|
|
case SWITCHDEV_PORT_OBJ_DEL:
|
2019-06-15 01:49:22 +08:00
|
|
|
err = switchdev_handle_port_obj_del(dev, ptr,
|
|
|
|
|
dsa_slave_dev_check,
|
|
|
|
|
dsa_slave_port_obj_del);
|
|
|
|
|
return notifier_from_errno(err);
|
2019-02-28 03:44:27 +08:00
|
|
|
case SWITCHDEV_PORT_ATTR_SET:
|
2019-06-15 01:49:22 +08:00
|
|
|
err = switchdev_handle_port_attr_set(dev, ptr,
|
|
|
|
|
dsa_slave_dev_check,
|
|
|
|
|
dsa_slave_port_attr_set);
|
|
|
|
|
return notifier_from_errno(err);
|
2018-11-23 07:29:05 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-04 02:20:16 +08:00
|
|
|
static struct notifier_block dsa_slave_nb __read_mostly = {
|
2017-08-06 21:15:42 +08:00
|
|
|
.notifier_call = dsa_slave_netdevice_event,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct notifier_block dsa_slave_switchdev_notifier = {
|
|
|
|
|
.notifier_call = dsa_slave_switchdev_event,
|
2017-02-04 02:20:16 +08:00
|
|
|
};
|
|
|
|
|
|
2018-11-23 07:29:05 +08:00
|
|
|
static struct notifier_block dsa_slave_switchdev_blocking_notifier = {
|
|
|
|
|
.notifier_call = dsa_slave_switchdev_blocking_event,
|
|
|
|
|
};
|
|
|
|
|
|
2017-02-04 02:20:16 +08:00
|
|
|
int dsa_slave_register_notifier(void)
|
|
|
|
|
{
|
2018-11-23 07:29:05 +08:00
|
|
|
struct notifier_block *nb;
|
2017-08-06 21:15:42 +08:00
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = register_netdevice_notifier(&dsa_slave_nb);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
err = register_switchdev_notifier(&dsa_slave_switchdev_notifier);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_switchdev_nb;
|
|
|
|
|
|
2018-11-23 07:29:05 +08:00
|
|
|
nb = &dsa_slave_switchdev_blocking_notifier;
|
|
|
|
|
err = register_switchdev_blocking_notifier(nb);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_switchdev_blocking_nb;
|
|
|
|
|
|
2017-08-06 21:15:42 +08:00
|
|
|
return 0;
|
|
|
|
|
|
2018-11-23 07:29:05 +08:00
|
|
|
err_switchdev_blocking_nb:
|
|
|
|
|
unregister_switchdev_notifier(&dsa_slave_switchdev_notifier);
|
2017-08-06 21:15:42 +08:00
|
|
|
err_switchdev_nb:
|
|
|
|
|
unregister_netdevice_notifier(&dsa_slave_nb);
|
|
|
|
|
return err;
|
2017-02-04 02:20:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void dsa_slave_unregister_notifier(void)
|
|
|
|
|
{
|
2018-11-23 07:29:05 +08:00
|
|
|
struct notifier_block *nb;
|
2017-02-04 02:20:16 +08:00
|
|
|
int err;
|
|
|
|
|
|
2018-11-23 07:29:05 +08:00
|
|
|
nb = &dsa_slave_switchdev_blocking_notifier;
|
|
|
|
|
err = unregister_switchdev_blocking_notifier(nb);
|
|
|
|
|
if (err)
|
|
|
|
|
pr_err("DSA: failed to unregister switchdev blocking notifier (%d)\n", err);
|
|
|
|
|
|
2017-08-06 21:15:42 +08:00
|
|
|
err = unregister_switchdev_notifier(&dsa_slave_switchdev_notifier);
|
|
|
|
|
if (err)
|
|
|
|
|
pr_err("DSA: failed to unregister switchdev notifier (%d)\n", err);
|
|
|
|
|
|
2017-02-04 02:20:16 +08:00
|
|
|
err = unregister_netdevice_notifier(&dsa_slave_nb);
|
|
|
|
|
if (err)
|
|
|
|
|
pr_err("DSA: failed to unregister slave notifier (%d)\n", err);
|
|
|
|
|
}
|
