2019-05-29 00:57:21 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2013-01-08 23:36:42 +08:00
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/*
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* Copyright (C) Overkiz SAS 2012
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*
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* Author: Boris BREZILLON <b.brezillon@overkiz.com>
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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2020-10-31 02:36:56 +08:00
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#include <linux/mfd/syscon.h>
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2013-01-08 23:36:42 +08:00
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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2023-07-15 01:48:50 +08:00
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#include <linux/of.h>
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2020-10-31 02:36:56 +08:00
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#include <linux/regmap.h>
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2013-01-08 23:36:42 +08:00
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#include <linux/slab.h>
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2019-04-27 05:47:10 +08:00
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#include <soc/at91/atmel_tcb.h>
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2013-01-08 23:36:42 +08:00
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2020-10-31 02:36:56 +08:00
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#define NPWM 2
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2013-01-08 23:36:42 +08:00
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#define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \
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ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
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#define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \
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ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
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struct atmel_tcb_pwm_device {
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unsigned div; /* PWM clock divider */
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unsigned duty; /* PWM duty expressed in clk cycles */
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unsigned period; /* PWM period expressed in clk cycles */
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};
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2017-10-20 00:44:10 +08:00
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struct atmel_tcb_channel {
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u32 enabled;
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u32 cmr;
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u32 ra;
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u32 rb;
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u32 rc;
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};
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2013-01-08 23:36:42 +08:00
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struct atmel_tcb_pwm_chip {
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struct pwm_chip chip;
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spinlock_t lock;
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2020-10-31 02:36:56 +08:00
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u8 channel;
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u8 width;
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struct regmap *regmap;
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struct clk *clk;
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2020-10-31 02:36:57 +08:00
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struct clk *gclk;
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2020-10-31 02:36:56 +08:00
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struct clk *slow_clk;
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2023-07-20 03:20:11 +08:00
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struct atmel_tcb_pwm_device pwms[NPWM];
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2020-10-31 02:36:56 +08:00
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struct atmel_tcb_channel bkup;
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2013-01-08 23:36:42 +08:00
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};
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2022-04-08 23:29:10 +08:00
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static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };
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2020-10-31 02:36:56 +08:00
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2013-01-08 23:36:42 +08:00
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static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct atmel_tcb_pwm_chip, chip);
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}
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static int atmel_tcb_pwm_request(struct pwm_chip *chip,
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struct pwm_device *pwm)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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2023-07-20 03:20:11 +08:00
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struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
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2013-01-08 23:36:42 +08:00
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unsigned cmr;
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int ret;
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2020-10-31 02:36:56 +08:00
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ret = clk_prepare_enable(tcbpwmc->clk);
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2023-07-20 03:20:11 +08:00
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if (ret)
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2013-01-08 23:36:42 +08:00
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return ret;
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tcbpwm->duty = 0;
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tcbpwm->period = 0;
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tcbpwm->div = 0;
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spin_lock(&tcbpwmc->lock);
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2020-10-31 02:36:56 +08:00
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regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
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2013-01-08 23:36:42 +08:00
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/*
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* Get init config from Timer Counter registers if
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* Timer Counter is already configured as a PWM generator.
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*/
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if (cmr & ATMEL_TC_WAVE) {
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2020-10-31 02:36:56 +08:00
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if (pwm->hwpwm == 0)
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regmap_read(tcbpwmc->regmap,
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ATMEL_TC_REG(tcbpwmc->channel, RA),
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&tcbpwm->duty);
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2013-01-08 23:36:42 +08:00
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else
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2020-10-31 02:36:56 +08:00
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regmap_read(tcbpwmc->regmap,
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ATMEL_TC_REG(tcbpwmc->channel, RB),
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&tcbpwm->duty);
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2013-01-08 23:36:42 +08:00
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tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
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2020-10-31 02:36:56 +08:00
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regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
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&tcbpwm->period);
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2013-01-08 23:36:42 +08:00
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cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
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ATMEL_TC_BCMR_MASK);
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} else
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cmr = 0;
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cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
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2020-10-31 02:36:56 +08:00
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regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
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2013-01-08 23:36:42 +08:00
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spin_unlock(&tcbpwmc->lock);
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return 0;
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}
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static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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2020-10-31 02:36:56 +08:00
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clk_disable_unprepare(tcbpwmc->clk);
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2013-01-08 23:36:42 +08:00
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}
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2023-07-20 03:20:13 +08:00
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static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
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enum pwm_polarity polarity)
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2013-01-08 23:36:42 +08:00
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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2023-07-20 03:20:11 +08:00
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struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
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2013-01-08 23:36:42 +08:00
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unsigned cmr;
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/*
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* If duty is 0 the timer will be stopped and we have to
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* configure the output correctly on software trigger:
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* - set output to high if PWM_POLARITY_INVERSED
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* - set output to low if PWM_POLARITY_NORMAL
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*
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* This is why we're reverting polarity in this case.
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*/
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if (tcbpwm->duty == 0)
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polarity = !polarity;
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spin_lock(&tcbpwmc->lock);
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2020-10-31 02:36:56 +08:00
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regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
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2013-01-08 23:36:42 +08:00
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/* flush old setting and set the new one */
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2020-10-31 02:36:56 +08:00
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if (pwm->hwpwm == 0) {
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2013-01-08 23:36:42 +08:00
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cmr &= ~ATMEL_TC_ACMR_MASK;
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_ASWTRG_CLEAR;
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else
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cmr |= ATMEL_TC_ASWTRG_SET;
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} else {
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cmr &= ~ATMEL_TC_BCMR_MASK;
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_BSWTRG_CLEAR;
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else
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cmr |= ATMEL_TC_BSWTRG_SET;
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}
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2020-10-31 02:36:56 +08:00
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regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
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2013-01-08 23:36:42 +08:00
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/*
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* Use software trigger to apply the new setting.
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* If both PWM devices in this group are disabled we stop the clock.
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*/
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2017-10-20 00:44:10 +08:00
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if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
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2020-10-31 02:36:56 +08:00
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regmap_write(tcbpwmc->regmap,
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ATMEL_TC_REG(tcbpwmc->channel, CCR),
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ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS);
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tcbpwmc->bkup.enabled = 1;
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2017-10-20 00:44:10 +08:00
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} else {
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2020-10-31 02:36:56 +08:00
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regmap_write(tcbpwmc->regmap,
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ATMEL_TC_REG(tcbpwmc->channel, CCR),
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ATMEL_TC_SWTRG);
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tcbpwmc->bkup.enabled = 0;
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2017-10-20 00:44:10 +08:00
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}
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2013-01-08 23:36:42 +08:00
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spin_unlock(&tcbpwmc->lock);
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}
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2023-07-20 03:20:13 +08:00
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static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
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enum pwm_polarity polarity)
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2013-01-08 23:36:42 +08:00
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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2023-07-20 03:20:11 +08:00
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struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
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2013-01-08 23:36:42 +08:00
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u32 cmr;
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/*
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* If duty is 0 the timer will be stopped and we have to
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* configure the output correctly on software trigger:
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* - set output to high if PWM_POLARITY_INVERSED
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* - set output to low if PWM_POLARITY_NORMAL
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*
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* This is why we're reverting polarity in this case.
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*/
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if (tcbpwm->duty == 0)
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polarity = !polarity;
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spin_lock(&tcbpwmc->lock);
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2020-10-31 02:36:56 +08:00
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regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
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2013-01-08 23:36:42 +08:00
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/* flush old setting and set the new one */
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cmr &= ~ATMEL_TC_TCCLKS;
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2020-10-31 02:36:56 +08:00
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if (pwm->hwpwm == 0) {
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2013-01-08 23:36:42 +08:00
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cmr &= ~ATMEL_TC_ACMR_MASK;
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/* Set CMR flags according to given polarity */
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_ASWTRG_CLEAR;
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else
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cmr |= ATMEL_TC_ASWTRG_SET;
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} else {
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cmr &= ~ATMEL_TC_BCMR_MASK;
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_BSWTRG_CLEAR;
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else
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cmr |= ATMEL_TC_BSWTRG_SET;
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}
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/*
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* If duty is 0 or equal to period there's no need to register
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* a specific action on RA/RB and RC compare.
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* The output will be configured on software trigger and keep
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* this config till next config call.
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*/
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if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
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2020-10-31 02:36:56 +08:00
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if (pwm->hwpwm == 0) {
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2013-01-08 23:36:42 +08:00
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
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else
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cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
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} else {
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if (polarity == PWM_POLARITY_INVERSED)
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cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
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else
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cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
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}
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}
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2013-09-18 23:06:05 +08:00
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cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);
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2020-10-31 02:36:56 +08:00
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regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
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2013-01-08 23:36:42 +08:00
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2020-10-31 02:36:56 +08:00
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if (pwm->hwpwm == 0)
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regmap_write(tcbpwmc->regmap,
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ATMEL_TC_REG(tcbpwmc->channel, RA),
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tcbpwm->duty);
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2013-01-08 23:36:42 +08:00
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else
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2020-10-31 02:36:56 +08:00
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regmap_write(tcbpwmc->regmap,
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ATMEL_TC_REG(tcbpwmc->channel, RB),
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tcbpwm->duty);
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2013-01-08 23:36:42 +08:00
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2020-10-31 02:36:56 +08:00
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regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
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tcbpwm->period);
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2013-01-08 23:36:42 +08:00
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/* Use software trigger to apply the new setting */
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2020-10-31 02:36:56 +08:00
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regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
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ATMEL_TC_SWTRG | ATMEL_TC_CLKEN);
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tcbpwmc->bkup.enabled = 1;
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2013-01-08 23:36:42 +08:00
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spin_unlock(&tcbpwmc->lock);
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return 0;
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}
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static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
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2023-07-20 03:20:11 +08:00
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struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
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2013-01-08 23:36:42 +08:00
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struct atmel_tcb_pwm_device *atcbpwm = NULL;
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2020-10-31 02:36:57 +08:00
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int i = 0;
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2013-01-08 23:36:42 +08:00
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int slowclk = 0;
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unsigned period;
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unsigned duty;
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2020-10-31 02:36:56 +08:00
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unsigned rate = clk_get_rate(tcbpwmc->clk);
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2013-01-08 23:36:42 +08:00
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unsigned long long min;
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unsigned long long max;
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/*
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* Find best clk divisor:
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* the smallest divisor which can fulfill the period_ns requirements.
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2022-05-21 19:10:32 +08:00
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* If there is a gclk, the first divisor is actually the gclk selector
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2013-01-08 23:36:42 +08:00
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*/
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2020-10-31 02:36:57 +08:00
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if (tcbpwmc->gclk)
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i = 1;
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for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
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2020-10-31 02:36:56 +08:00
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|
if (atmel_tcb_divisors[i] == 0) {
|
2013-01-08 23:36:42 +08:00
|
|
|
slowclk = i;
|
|
|
|
continue;
|
|
|
|
}
|
2020-10-31 02:36:56 +08:00
|
|
|
min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
|
|
|
|
max = min << tcbpwmc->width;
|
2013-01-08 23:36:42 +08:00
|
|
|
if (max >= period_ns)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If none of the divisor are small enough to represent period_ns
|
|
|
|
* take slow clock (32KHz).
|
|
|
|
*/
|
2020-10-31 02:36:56 +08:00
|
|
|
if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
|
2013-01-08 23:36:42 +08:00
|
|
|
i = slowclk;
|
2020-10-31 02:36:56 +08:00
|
|
|
rate = clk_get_rate(tcbpwmc->slow_clk);
|
2013-01-08 23:36:42 +08:00
|
|
|
min = div_u64(NSEC_PER_SEC, rate);
|
2020-10-31 02:36:56 +08:00
|
|
|
max = min << tcbpwmc->width;
|
2013-01-08 23:36:42 +08:00
|
|
|
|
|
|
|
/* If period is too big return ERANGE error */
|
|
|
|
if (max < period_ns)
|
|
|
|
return -ERANGE;
|
|
|
|
}
|
|
|
|
|
|
|
|
duty = div_u64(duty_ns, min);
|
|
|
|
period = div_u64(period_ns, min);
|
|
|
|
|
2020-10-31 02:36:56 +08:00
|
|
|
if (pwm->hwpwm == 0)
|
2023-07-20 03:20:11 +08:00
|
|
|
atcbpwm = &tcbpwmc->pwms[1];
|
2013-01-08 23:36:42 +08:00
|
|
|
else
|
2023-07-20 03:20:11 +08:00
|
|
|
atcbpwm = &tcbpwmc->pwms[0];
|
2013-01-08 23:36:42 +08:00
|
|
|
|
|
|
|
/*
|
2020-10-31 02:36:56 +08:00
|
|
|
* PWM devices provided by the TCB driver are grouped by 2.
|
2013-01-08 23:36:42 +08:00
|
|
|
* PWM devices in a given group must be configured with the
|
|
|
|
* same period_ns.
|
|
|
|
*
|
|
|
|
* We're checking the period value of the second PWM device
|
|
|
|
* in this group before applying the new config.
|
|
|
|
*/
|
|
|
|
if ((atcbpwm && atcbpwm->duty > 0 &&
|
|
|
|
atcbpwm->duty != atcbpwm->period) &&
|
|
|
|
(atcbpwm->div != i || atcbpwm->period != period)) {
|
|
|
|
dev_err(chip->dev,
|
|
|
|
"failed to configure period_ns: PWM group already configured with a different value\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
tcbpwm->period = period;
|
|
|
|
tcbpwm->div = i;
|
|
|
|
tcbpwm->duty = duty;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-03-08 17:50:12 +08:00
|
|
|
static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
|
|
|
|
const struct pwm_state *state)
|
|
|
|
{
|
|
|
|
int duty_cycle, period;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!state->enabled) {
|
2023-07-20 03:20:13 +08:00
|
|
|
atmel_tcb_pwm_disable(chip, pwm, state->polarity);
|
2021-03-08 17:50:12 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
period = state->period < INT_MAX ? state->period : INT_MAX;
|
|
|
|
duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX;
|
|
|
|
|
|
|
|
ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2023-07-20 03:20:13 +08:00
|
|
|
return atmel_tcb_pwm_enable(chip, pwm, state->polarity);
|
2021-03-08 17:50:12 +08:00
|
|
|
}
|
|
|
|
|
2013-01-08 23:36:42 +08:00
|
|
|
static const struct pwm_ops atmel_tcb_pwm_ops = {
|
|
|
|
.request = atmel_tcb_pwm_request,
|
|
|
|
.free = atmel_tcb_pwm_free,
|
2021-03-08 17:50:12 +08:00
|
|
|
.apply = atmel_tcb_pwm_apply,
|
2013-01-08 23:36:42 +08:00
|
|
|
};
|
|
|
|
|
2020-10-31 02:36:56 +08:00
|
|
|
static struct atmel_tcb_config tcb_rm9200_config = {
|
|
|
|
.counter_width = 16,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct atmel_tcb_config tcb_sam9x5_config = {
|
|
|
|
.counter_width = 32,
|
|
|
|
};
|
|
|
|
|
2020-10-31 02:36:57 +08:00
|
|
|
static struct atmel_tcb_config tcb_sama5d2_config = {
|
|
|
|
.counter_width = 32,
|
|
|
|
.has_gclk = 1,
|
|
|
|
};
|
|
|
|
|
2020-10-31 02:36:56 +08:00
|
|
|
static const struct of_device_id atmel_tcb_of_match[] = {
|
|
|
|
{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
|
|
|
|
{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
|
2020-10-31 02:36:57 +08:00
|
|
|
{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
|
2020-10-31 02:36:56 +08:00
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
|
2013-01-08 23:36:42 +08:00
|
|
|
static int atmel_tcb_pwm_probe(struct platform_device *pdev)
|
|
|
|
{
|
2020-10-31 02:36:56 +08:00
|
|
|
const struct of_device_id *match;
|
2013-01-08 23:36:42 +08:00
|
|
|
struct atmel_tcb_pwm_chip *tcbpwm;
|
2020-10-31 02:36:56 +08:00
|
|
|
const struct atmel_tcb_config *config;
|
2013-01-08 23:36:42 +08:00
|
|
|
struct device_node *np = pdev->dev.of_node;
|
2020-10-31 02:36:56 +08:00
|
|
|
char clk_name[] = "t0_clk";
|
2013-01-08 23:36:42 +08:00
|
|
|
int err;
|
2020-10-31 02:36:56 +08:00
|
|
|
int channel;
|
2013-01-08 23:36:42 +08:00
|
|
|
|
2023-07-20 03:20:09 +08:00
|
|
|
tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
|
|
|
|
if (tcbpwm == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2020-10-31 02:36:56 +08:00
|
|
|
err = of_property_read_u32(np, "reg", &channel);
|
2013-01-08 23:36:42 +08:00
|
|
|
if (err < 0) {
|
|
|
|
dev_err(&pdev->dev,
|
2020-10-31 02:36:56 +08:00
|
|
|
"failed to get Timer Counter Block channel from device tree (error: %d)\n",
|
2013-01-08 23:36:42 +08:00
|
|
|
err);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2023-07-20 03:20:09 +08:00
|
|
|
tcbpwm->regmap = syscon_node_to_regmap(np->parent);
|
|
|
|
if (IS_ERR(tcbpwm->regmap))
|
|
|
|
return PTR_ERR(tcbpwm->regmap);
|
2020-10-31 02:36:56 +08:00
|
|
|
|
2023-07-20 03:20:09 +08:00
|
|
|
tcbpwm->slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
|
|
|
|
if (IS_ERR(tcbpwm->slow_clk))
|
|
|
|
return PTR_ERR(tcbpwm->slow_clk);
|
2020-10-31 02:36:56 +08:00
|
|
|
|
|
|
|
clk_name[1] += channel;
|
2023-07-20 03:20:09 +08:00
|
|
|
tcbpwm->clk = of_clk_get_by_name(np->parent, clk_name);
|
|
|
|
if (IS_ERR(tcbpwm->clk))
|
|
|
|
tcbpwm->clk = of_clk_get_by_name(np->parent, "t0_clk");
|
2023-07-20 03:20:10 +08:00
|
|
|
if (IS_ERR(tcbpwm->clk)) {
|
|
|
|
err = PTR_ERR(tcbpwm->clk);
|
|
|
|
goto err_slow_clk;
|
|
|
|
}
|
2020-10-31 02:36:56 +08:00
|
|
|
|
|
|
|
match = of_match_node(atmel_tcb_of_match, np->parent);
|
|
|
|
config = match->data;
|
2013-01-08 23:36:42 +08:00
|
|
|
|
2020-10-31 02:36:57 +08:00
|
|
|
if (config->has_gclk) {
|
2023-07-20 03:20:09 +08:00
|
|
|
tcbpwm->gclk = of_clk_get_by_name(np->parent, "gclk");
|
2023-07-20 03:20:10 +08:00
|
|
|
if (IS_ERR(tcbpwm->gclk)) {
|
|
|
|
err = PTR_ERR(tcbpwm->gclk);
|
|
|
|
goto err_clk;
|
|
|
|
}
|
2013-01-08 23:36:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
tcbpwm->chip.dev = &pdev->dev;
|
|
|
|
tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
|
|
|
|
tcbpwm->chip.npwm = NPWM;
|
2020-10-31 02:36:56 +08:00
|
|
|
tcbpwm->channel = channel;
|
|
|
|
tcbpwm->width = config->counter_width;
|
2013-01-08 23:36:42 +08:00
|
|
|
|
2023-07-20 03:20:09 +08:00
|
|
|
err = clk_prepare_enable(tcbpwm->slow_clk);
|
2015-08-16 17:23:46 +08:00
|
|
|
if (err)
|
2023-07-20 03:20:10 +08:00
|
|
|
goto err_gclk;
|
2015-08-16 17:23:46 +08:00
|
|
|
|
2013-01-08 23:36:42 +08:00
|
|
|
spin_lock_init(&tcbpwm->lock);
|
|
|
|
|
|
|
|
err = pwmchip_add(&tcbpwm->chip);
|
2015-08-16 17:23:46 +08:00
|
|
|
if (err < 0)
|
|
|
|
goto err_disable_clk;
|
2013-01-08 23:36:42 +08:00
|
|
|
|
|
|
|
platform_set_drvdata(pdev, tcbpwm);
|
|
|
|
|
|
|
|
return 0;
|
2015-08-16 17:23:46 +08:00
|
|
|
|
|
|
|
err_disable_clk:
|
2020-10-31 02:36:56 +08:00
|
|
|
clk_disable_unprepare(tcbpwm->slow_clk);
|
2015-08-16 17:23:46 +08:00
|
|
|
|
2023-07-20 03:20:10 +08:00
|
|
|
err_gclk:
|
|
|
|
clk_put(tcbpwm->gclk);
|
|
|
|
|
|
|
|
err_clk:
|
|
|
|
clk_put(tcbpwm->clk);
|
|
|
|
|
2020-10-31 02:36:56 +08:00
|
|
|
err_slow_clk:
|
2023-07-20 03:20:09 +08:00
|
|
|
clk_put(tcbpwm->slow_clk);
|
2015-08-16 17:23:46 +08:00
|
|
|
|
|
|
|
return err;
|
2013-01-08 23:36:42 +08:00
|
|
|
}
|
|
|
|
|
2023-03-04 02:54:17 +08:00
|
|
|
static void atmel_tcb_pwm_remove(struct platform_device *pdev)
|
2013-01-08 23:36:42 +08:00
|
|
|
{
|
|
|
|
struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
|
|
|
|
|
2021-07-08 00:28:22 +08:00
|
|
|
pwmchip_remove(&tcbpwm->chip);
|
2013-01-08 23:36:42 +08:00
|
|
|
|
2021-03-08 17:51:50 +08:00
|
|
|
clk_disable_unprepare(tcbpwm->slow_clk);
|
2023-07-20 03:20:10 +08:00
|
|
|
clk_put(tcbpwm->gclk);
|
2021-03-08 17:51:50 +08:00
|
|
|
clk_put(tcbpwm->clk);
|
2023-07-20 03:20:10 +08:00
|
|
|
clk_put(tcbpwm->slow_clk);
|
2013-01-08 23:36:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
|
|
|
|
{ .compatible = "atmel,tcb-pwm", },
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
|
|
|
|
|
2017-10-20 00:44:10 +08:00
|
|
|
static int atmel_tcb_pwm_suspend(struct device *dev)
|
|
|
|
{
|
2018-04-19 22:06:13 +08:00
|
|
|
struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
|
2020-10-31 02:36:56 +08:00
|
|
|
struct atmel_tcb_channel *chan = &tcbpwm->bkup;
|
|
|
|
unsigned int channel = tcbpwm->channel;
|
2017-10-20 00:44:10 +08:00
|
|
|
|
2020-10-31 02:36:56 +08:00
|
|
|
regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
|
|
|
|
regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
|
|
|
|
regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
|
|
|
|
regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);
|
2017-10-20 00:44:10 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int atmel_tcb_pwm_resume(struct device *dev)
|
|
|
|
{
|
2018-04-19 22:06:13 +08:00
|
|
|
struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
|
2020-10-31 02:36:56 +08:00
|
|
|
struct atmel_tcb_channel *chan = &tcbpwm->bkup;
|
|
|
|
unsigned int channel = tcbpwm->channel;
|
2017-10-20 00:44:10 +08:00
|
|
|
|
2020-10-31 02:36:56 +08:00
|
|
|
regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
|
|
|
|
regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
|
|
|
|
regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
|
|
|
|
regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), chan->rc);
|
|
|
|
|
|
|
|
if (chan->enabled)
|
|
|
|
regmap_write(tcbpwm->regmap,
|
|
|
|
ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
|
|
|
|
ATMEL_TC_REG(channel, CCR));
|
2017-10-20 00:44:10 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2023-10-24 01:46:19 +08:00
|
|
|
static DEFINE_SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
|
|
|
|
atmel_tcb_pwm_resume);
|
2017-10-20 00:44:10 +08:00
|
|
|
|
2013-01-08 23:36:42 +08:00
|
|
|
static struct platform_driver atmel_tcb_pwm_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "atmel-tcb-pwm",
|
|
|
|
.of_match_table = atmel_tcb_pwm_dt_ids,
|
2023-10-24 01:46:19 +08:00
|
|
|
.pm = pm_ptr(&atmel_tcb_pwm_pm_ops),
|
2013-01-08 23:36:42 +08:00
|
|
|
},
|
|
|
|
.probe = atmel_tcb_pwm_probe,
|
2023-03-04 02:54:17 +08:00
|
|
|
.remove_new = atmel_tcb_pwm_remove,
|
2013-01-08 23:36:42 +08:00
|
|
|
};
|
|
|
|
module_platform_driver(atmel_tcb_pwm_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
|
|
|
|
MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|