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974 lines
21 KiB
C
974 lines
21 KiB
C
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/* DVB compliant Linux driver for the DVB-S si2109/2110 demodulator
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*
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* Copyright (C) 2008 Igor M. Liplianin (liplianin@me.by)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/jiffies.h>
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#include <asm/div64.h>
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#include "dvb_frontend.h"
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#include "si21xx.h"
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#define REVISION_REG 0x00
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#define SYSTEM_MODE_REG 0x01
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#define TS_CTRL_REG_1 0x02
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#define TS_CTRL_REG_2 0x03
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#define PIN_CTRL_REG_1 0x04
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#define PIN_CTRL_REG_2 0x05
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#define LOCK_STATUS_REG_1 0x0f
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#define LOCK_STATUS_REG_2 0x10
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#define ACQ_STATUS_REG 0x11
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#define ACQ_CTRL_REG_1 0x13
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#define ACQ_CTRL_REG_2 0x14
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#define PLL_DIVISOR_REG 0x15
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#define COARSE_TUNE_REG 0x16
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#define FINE_TUNE_REG_L 0x17
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#define FINE_TUNE_REG_H 0x18
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#define ANALOG_AGC_POWER_LEVEL_REG 0x28
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#define CFO_ESTIMATOR_CTRL_REG_1 0x29
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#define CFO_ESTIMATOR_CTRL_REG_2 0x2a
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#define CFO_ESTIMATOR_CTRL_REG_3 0x2b
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#define SYM_RATE_ESTIMATE_REG_L 0x31
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#define SYM_RATE_ESTIMATE_REG_M 0x32
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#define SYM_RATE_ESTIMATE_REG_H 0x33
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#define CFO_ESTIMATOR_OFFSET_REG_L 0x36
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#define CFO_ESTIMATOR_OFFSET_REG_H 0x37
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#define CFO_ERROR_REG_L 0x38
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#define CFO_ERROR_REG_H 0x39
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#define SYM_RATE_ESTIMATOR_CTRL_REG 0x3a
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#define SYM_RATE_REG_L 0x3f
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#define SYM_RATE_REG_M 0x40
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#define SYM_RATE_REG_H 0x41
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#define SYM_RATE_ESTIMATOR_MAXIMUM_REG 0x42
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#define SYM_RATE_ESTIMATOR_MINIMUM_REG 0x43
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#define C_N_ESTIMATOR_CTRL_REG 0x7c
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#define C_N_ESTIMATOR_THRSHLD_REG 0x7d
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#define C_N_ESTIMATOR_LEVEL_REG_L 0x7e
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#define C_N_ESTIMATOR_LEVEL_REG_H 0x7f
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#define BLIND_SCAN_CTRL_REG 0x80
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#define LSA_CTRL_REG_1 0x8D
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#define SPCTRM_TILT_CORR_THRSHLD_REG 0x8f
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#define ONE_DB_BNDWDTH_THRSHLD_REG 0x90
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#define TWO_DB_BNDWDTH_THRSHLD_REG 0x91
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#define THREE_DB_BNDWDTH_THRSHLD_REG 0x92
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#define INBAND_POWER_THRSHLD_REG 0x93
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#define REF_NOISE_LVL_MRGN_THRSHLD_REG 0x94
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#define VIT_SRCH_CTRL_REG_1 0xa0
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#define VIT_SRCH_CTRL_REG_2 0xa1
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#define VIT_SRCH_CTRL_REG_3 0xa2
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#define VIT_SRCH_STATUS_REG 0xa3
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#define VITERBI_BER_COUNT_REG_L 0xab
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#define REED_SOLOMON_CTRL_REG 0xb0
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#define REED_SOLOMON_ERROR_COUNT_REG_L 0xb1
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#define PRBS_CTRL_REG 0xb5
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#define LNB_CTRL_REG_1 0xc0
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#define LNB_CTRL_REG_2 0xc1
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#define LNB_CTRL_REG_3 0xc2
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#define LNB_CTRL_REG_4 0xc3
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#define LNB_CTRL_STATUS_REG 0xc4
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#define LNB_FIFO_REGS_0 0xc5
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#define LNB_FIFO_REGS_1 0xc6
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#define LNB_FIFO_REGS_2 0xc7
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#define LNB_FIFO_REGS_3 0xc8
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#define LNB_FIFO_REGS_4 0xc9
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#define LNB_FIFO_REGS_5 0xca
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#define LNB_SUPPLY_CTRL_REG_1 0xcb
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#define LNB_SUPPLY_CTRL_REG_2 0xcc
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#define LNB_SUPPLY_CTRL_REG_3 0xcd
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#define LNB_SUPPLY_CTRL_REG_4 0xce
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#define LNB_SUPPLY_STATUS_REG 0xcf
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#define FALSE 0
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#define TRUE 1
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#define FAIL -1
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#define PASS 0
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#define ALLOWABLE_FS_COUNT 10
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#define STATUS_BER 0
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#define STATUS_UCBLOCKS 1
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static int debug;
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#define dprintk(args...) \
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do { \
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if (debug) \
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printk(KERN_DEBUG "si21xx: " args); \
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} while (0)
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enum {
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ACTIVE_HIGH,
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ACTIVE_LOW
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};
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enum {
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BYTE_WIDE,
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BIT_WIDE
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};
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enum {
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CLK_GAPPED_MODE,
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CLK_CONTINUOUS_MODE
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};
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enum {
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RISING_EDGE,
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FALLING_EDGE
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};
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enum {
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MSB_FIRST,
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LSB_FIRST
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};
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enum {
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SERIAL,
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PARALLEL
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};
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struct si21xx_state {
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struct i2c_adapter *i2c;
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const struct si21xx_config *config;
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struct dvb_frontend frontend;
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u8 initialised:1;
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int errmode;
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int fs; /*Sampling rate of the ADC in MHz*/
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};
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/* register default initialization */
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static u8 serit_sp1511lhb_inittab[] = {
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0x01, 0x28, /* set i2c_inc_disable */
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0x20, 0x03,
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0x27, 0x20,
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0xe0, 0x45,
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0xe1, 0x08,
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0xfe, 0x01,
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0x01, 0x28,
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0x89, 0x09,
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0x04, 0x80,
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0x05, 0x01,
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0x06, 0x00,
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0x20, 0x03,
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0x24, 0x88,
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0x29, 0x09,
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0x2a, 0x0f,
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0x2c, 0x10,
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0x2d, 0x19,
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0x2e, 0x08,
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0x2f, 0x10,
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0x30, 0x19,
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0x34, 0x20,
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0x35, 0x03,
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0x45, 0x02,
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0x46, 0x45,
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0x47, 0xd0,
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0x48, 0x00,
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0x49, 0x40,
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0x4a, 0x03,
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0x4c, 0xfd,
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0x4f, 0x2e,
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0x50, 0x2e,
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0x51, 0x10,
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0x52, 0x10,
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0x56, 0x92,
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0x59, 0x00,
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0x5a, 0x2d,
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0x5b, 0x33,
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0x5c, 0x1f,
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0x5f, 0x76,
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0x62, 0xc0,
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0x63, 0xc0,
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0x64, 0xf3,
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0x65, 0xf3,
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0x79, 0x40,
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0x6a, 0x40,
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0x6b, 0x0a,
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0x6c, 0x80,
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0x6d, 0x27,
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0x71, 0x06,
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0x75, 0x60,
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0x78, 0x00,
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0x79, 0xb5,
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0x7c, 0x05,
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0x7d, 0x1a,
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0x87, 0x55,
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0x88, 0x72,
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0x8f, 0x08,
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0x90, 0xe0,
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0x94, 0x40,
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0xa0, 0x3f,
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0xa1, 0xc0,
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0xa4, 0xcc,
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0xa5, 0x66,
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0xa6, 0x66,
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0xa7, 0x7b,
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0xa8, 0x7b,
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0xa9, 0x7b,
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0xaa, 0x9a,
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0xed, 0x04,
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0xad, 0x00,
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0xae, 0x03,
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0xcc, 0xab,
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0x01, 0x08,
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0xff, 0xff
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};
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/* low level read/writes */
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static int si21_writeregs(struct si21xx_state *state, u8 reg1,
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u8 *data, int len)
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{
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int ret;
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u8 buf[60];/* = { reg1, data };*/
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struct i2c_msg msg = {
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.addr = state->config->demod_address,
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.flags = 0,
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.buf = buf,
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.len = len + 1
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};
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msg.buf[0] = reg1;
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memcpy(msg.buf + 1, data, len);
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ret = i2c_transfer(state->i2c, &msg, 1);
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if (ret != 1)
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dprintk("%s: writereg error (reg1 == 0x%02x, data == 0x%02x, "
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"ret == %i)\n", __func__, reg1, data[0], ret);
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return (ret != 1) ? -EREMOTEIO : 0;
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}
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static int si21_writereg(struct si21xx_state *state, u8 reg, u8 data)
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{
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int ret;
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u8 buf[] = { reg, data };
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struct i2c_msg msg = {
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.addr = state->config->demod_address,
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.flags = 0,
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.buf = buf,
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.len = 2
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};
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ret = i2c_transfer(state->i2c, &msg, 1);
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if (ret != 1)
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dprintk("%s: writereg error (reg == 0x%02x, data == 0x%02x, "
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"ret == %i)\n", __func__, reg, data, ret);
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return (ret != 1) ? -EREMOTEIO : 0;
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}
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static int si21_write(struct dvb_frontend *fe, u8 *buf, int len)
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{
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struct si21xx_state *state = fe->demodulator_priv;
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if (len != 2)
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return -EINVAL;
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return si21_writereg(state, buf[0], buf[1]);
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}
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static u8 si21_readreg(struct si21xx_state *state, u8 reg)
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{
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int ret;
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u8 b0[] = { reg };
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u8 b1[] = { 0 };
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struct i2c_msg msg[] = {
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{
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.addr = state->config->demod_address,
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.flags = 0,
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.buf = b0,
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.len = 1
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}, {
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.addr = state->config->demod_address,
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.flags = I2C_M_RD,
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.buf = b1,
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.len = 1
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}
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};
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2)
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dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n",
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__func__, reg, ret);
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return b1[0];
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}
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static int si21_readregs(struct si21xx_state *state, u8 reg1, u8 *b, u8 len)
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{
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int ret;
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struct i2c_msg msg[] = {
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{
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.addr = state->config->demod_address,
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.flags = 0,
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.buf = ®1,
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.len = 1
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}, {
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.addr = state->config->demod_address,
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.flags = I2C_M_RD,
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.buf = b,
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.len = len
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}
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};
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2)
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dprintk("%s: readreg error (ret == %i)\n", __func__, ret);
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return ret == 2 ? 0 : -1;
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}
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static int si21xx_wait_diseqc_idle(struct si21xx_state *state, int timeout)
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{
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unsigned long start = jiffies;
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dprintk("%s\n", __func__);
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while ((si21_readreg(state, LNB_CTRL_REG_1) & 0x8) == 8) {
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if (jiffies - start > timeout) {
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dprintk("%s: timeout!!\n", __func__);
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return -ETIMEDOUT;
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}
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msleep(10);
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};
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return 0;
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}
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static int si21xx_set_symbolrate(struct dvb_frontend *fe, u32 srate)
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{
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struct si21xx_state *state = fe->demodulator_priv;
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u32 sym_rate, data_rate;
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int i;
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u8 sym_rate_bytes[3];
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dprintk("%s : srate = %i\n", __func__ , srate);
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if ((srate < 1000000) || (srate > 45000000))
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return -EINVAL;
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data_rate = srate;
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sym_rate = 0;
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for (i = 0; i < 4; ++i) {
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sym_rate /= 100;
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sym_rate = sym_rate + ((data_rate % 100) * 0x800000) /
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state->fs;
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data_rate /= 100;
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}
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for (i = 0; i < 3; ++i)
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sym_rate_bytes[i] = (u8)((sym_rate >> (i * 8)) & 0xff);
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si21_writeregs(state, SYM_RATE_REG_L, sym_rate_bytes, 0x03);
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return 0;
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}
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static int si21xx_send_diseqc_msg(struct dvb_frontend *fe,
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struct dvb_diseqc_master_cmd *m)
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{
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struct si21xx_state *state = fe->demodulator_priv;
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u8 lnb_status;
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u8 LNB_CTRL_1;
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int status;
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dprintk("%s\n", __func__);
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status = PASS;
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LNB_CTRL_1 = 0;
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status |= si21_readregs(state, LNB_CTRL_STATUS_REG, &lnb_status, 0x01);
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status |= si21_readregs(state, LNB_CTRL_REG_1, &lnb_status, 0x01);
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/*fill the FIFO*/
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status |= si21_writeregs(state, LNB_FIFO_REGS_0, m->msg, m->msg_len);
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LNB_CTRL_1 = (lnb_status & 0x70);
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LNB_CTRL_1 |= m->msg_len;
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LNB_CTRL_1 |= 0x80; /* begin LNB signaling */
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status |= si21_writeregs(state, LNB_CTRL_REG_1, &LNB_CTRL_1, 0x01);
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return status;
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}
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static int si21xx_send_diseqc_burst(struct dvb_frontend *fe,
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fe_sec_mini_cmd_t burst)
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{
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struct si21xx_state *state = fe->demodulator_priv;
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||
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u8 val;
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dprintk("%s\n", __func__);
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if (si21xx_wait_diseqc_idle(state, 100) < 0)
|
||
|
return -ETIMEDOUT;
|
||
|
|
||
|
val = (0x80 | si21_readreg(state, 0xc1));
|
||
|
if (si21_writereg(state, LNB_CTRL_REG_1,
|
||
|
burst == SEC_MINI_A ? (val & ~0x10) : (val | 0x10)))
|
||
|
return -EREMOTEIO;
|
||
|
|
||
|
if (si21xx_wait_diseqc_idle(state, 100) < 0)
|
||
|
return -ETIMEDOUT;
|
||
|
|
||
|
if (si21_writereg(state, LNB_CTRL_REG_1, val))
|
||
|
return -EREMOTEIO;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
/* 30.06.2008 */
|
||
|
static int si21xx_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
|
||
|
{
|
||
|
struct si21xx_state *state = fe->demodulator_priv;
|
||
|
u8 val;
|
||
|
|
||
|
dprintk("%s\n", __func__);
|
||
|
val = (0x80 | si21_readreg(state, LNB_CTRL_REG_1));
|
||
|
|
||
|
switch (tone) {
|
||
|
case SEC_TONE_ON:
|
||
|
return si21_writereg(state, LNB_CTRL_REG_1, val | 0x20);
|
||
|
|
||
|
case SEC_TONE_OFF:
|
||
|
return si21_writereg(state, LNB_CTRL_REG_1, (val & ~0x20));
|
||
|
|
||
|
default:
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static int si21xx_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t volt)
|
||
|
{
|
||
|
struct si21xx_state *state = fe->demodulator_priv;
|
||
|
|
||
|
u8 val;
|
||
|
dprintk("%s: %s\n", __func__,
|
||
|
volt == SEC_VOLTAGE_13 ? "SEC_VOLTAGE_13" :
|
||
|
volt == SEC_VOLTAGE_18 ? "SEC_VOLTAGE_18" : "??");
|
||
|
|
||
|
|
||
|
val = (0x80 | si21_readreg(state, LNB_CTRL_REG_1));
|
||
|
|
||
|
switch (volt) {
|
||
|
case SEC_VOLTAGE_18:
|
||
|
return si21_writereg(state, LNB_CTRL_REG_1, val | 0x40);
|
||
|
break;
|
||
|
case SEC_VOLTAGE_13:
|
||
|
return si21_writereg(state, LNB_CTRL_REG_1, (val & ~0x40));
|
||
|
break;
|
||
|
default:
|
||
|
return -EINVAL;
|
||
|
};
|
||
|
}
|
||
|
|
||
|
static int si21xx_init(struct dvb_frontend *fe)
|
||
|
{
|
||
|
struct si21xx_state *state = fe->demodulator_priv;
|
||
|
int i;
|
||
|
int status = 0;
|
||
|
u8 reg1;
|
||
|
u8 val;
|
||
|
u8 reg2[2];
|
||
|
|
||
|
dprintk("%s\n", __func__);
|
||
|
|
||
|
for (i = 0; ; i += 2) {
|
||
|
reg1 = serit_sp1511lhb_inittab[i];
|
||
|
val = serit_sp1511lhb_inittab[i+1];
|
||
|
if (reg1 == 0xff && val == 0xff)
|
||
|
break;
|
||
|
si21_writeregs(state, reg1, &val, 1);
|
||
|
}
|
||
|
|
||
|
/*DVB QPSK SYSTEM MODE REG*/
|
||
|
reg1 = 0x08;
|
||
|
si21_writeregs(state, SYSTEM_MODE_REG, ®1, 0x01);
|
||
|
|
||
|
/*transport stream config*/
|
||
|
/*
|
||
|
mode = PARALLEL;
|
||
|
sdata_form = LSB_FIRST;
|
||
|
clk_edge = FALLING_EDGE;
|
||
|
clk_mode = CLK_GAPPED_MODE;
|
||
|
strt_len = BYTE_WIDE;
|
||
|
sync_pol = ACTIVE_HIGH;
|
||
|
val_pol = ACTIVE_HIGH;
|
||
|
err_pol = ACTIVE_HIGH;
|
||
|
sclk_rate = 0x00;
|
||
|
parity = 0x00 ;
|
||
|
data_delay = 0x00;
|
||
|
clk_delay = 0x00;
|
||
|
pclk_smooth = 0x00;
|
||
|
*/
|
||
|
reg2[0] =
|
||
|
PARALLEL + (LSB_FIRST << 1)
|
||
|
+ (FALLING_EDGE << 2) + (CLK_GAPPED_MODE << 3)
|
||
|
+ (BYTE_WIDE << 4) + (ACTIVE_HIGH << 5)
|
||
|
+ (ACTIVE_HIGH << 6) + (ACTIVE_HIGH << 7);
|
||
|
|
||
|
reg2[1] = 0;
|
||
|
/* sclk_rate + (parity << 2)
|
||
|
+ (data_delay << 3) + (clk_delay << 4)
|
||
|
+ (pclk_smooth << 5);
|
||
|
*/
|
||
|
status |= si21_writeregs(state, TS_CTRL_REG_1, reg2, 0x02);
|
||
|
if (status != 0)
|
||
|
dprintk(" %s : TS Set Error\n", __func__);
|
||
|
|
||
|
return 0;
|
||
|
|
||
|
}
|
||
|
|
||
|
static int si21_read_status(struct dvb_frontend *fe, fe_status_t *status)
|
||
|
{
|
||
|
struct si21xx_state *state = fe->demodulator_priv;
|
||
|
u8 regs_read[2];
|
||
|
u8 reg_read;
|
||
|
u8 i;
|
||
|
u8 lock;
|
||
|
u8 signal = si21_readreg(state, ANALOG_AGC_POWER_LEVEL_REG);
|
||
|
|
||
|
si21_readregs(state, LOCK_STATUS_REG_1, regs_read, 0x02);
|
||
|
reg_read = 0;
|
||
|
|
||
|
for (i = 0; i < 7; ++i)
|
||
|
reg_read |= ((regs_read[0] >> i) & 0x01) << (6 - i);
|
||
|
|
||
|
lock = ((reg_read & 0x7f) | (regs_read[1] & 0x80));
|
||
|
|
||
|
dprintk("%s : FE_READ_STATUS : VSTATUS: 0x%02x\n", __func__, lock);
|
||
|
*status = 0;
|
||
|
|
||
|
if (signal > 10)
|
||
|
*status |= FE_HAS_SIGNAL;
|
||
|
|
||
|
if (lock & 0x2)
|
||
|
*status |= FE_HAS_CARRIER;
|
||
|
|
||
|
if (lock & 0x20)
|
||
|
*status |= FE_HAS_VITERBI;
|
||
|
|
||
|
if (lock & 0x40)
|
||
|
*status |= FE_HAS_SYNC;
|
||
|
|
||
|
if ((lock & 0x7b) == 0x7b)
|
||
|
*status |= FE_HAS_LOCK;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int si21_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
|
||
|
{
|
||
|
struct si21xx_state *state = fe->demodulator_priv;
|
||
|
|
||
|
/*status = si21_readreg(state, ANALOG_AGC_POWER_LEVEL_REG,
|
||
|
(u8*)agclevel, 0x01);*/
|
||
|
|
||
|
u16 signal = (3 * si21_readreg(state, 0x27) *
|
||
|
si21_readreg(state, 0x28));
|
||
|
|
||
|
dprintk("%s : AGCPWR: 0x%02x%02x, signal=0x%04x\n", __func__,
|
||
|
si21_readreg(state, 0x27),
|
||
|
si21_readreg(state, 0x28), (int) signal);
|
||
|
|
||
|
signal <<= 4;
|
||
|
*strength = signal;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int si21_read_ber(struct dvb_frontend *fe, u32 *ber)
|
||
|
{
|
||
|
struct si21xx_state *state = fe->demodulator_priv;
|
||
|
|
||
|
dprintk("%s\n", __func__);
|
||
|
|
||
|
if (state->errmode != STATUS_BER)
|
||
|
return 0;
|
||
|
|
||
|
*ber = (si21_readreg(state, 0x1d) << 8) |
|
||
|
si21_readreg(state, 0x1e);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int si21_read_snr(struct dvb_frontend *fe, u16 *snr)
|
||
|
{
|
||
|
struct si21xx_state *state = fe->demodulator_priv;
|
||
|
|
||
|
s32 xsnr = 0xffff - ((si21_readreg(state, 0x24) << 8) |
|
||
|
si21_readreg(state, 0x25));
|
||
|
xsnr = 3 * (xsnr - 0xa100);
|
||
|
*snr = (xsnr > 0xffff) ? 0xffff : (xsnr < 0) ? 0 : xsnr;
|
||
|
|
||
|
dprintk("%s\n", __func__);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int si21_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
|
||
|
{
|
||
|
struct si21xx_state *state = fe->demodulator_priv;
|
||
|
|
||
|
dprintk("%s\n", __func__);
|
||
|
|
||
|
if (state->errmode != STATUS_UCBLOCKS)
|
||
|
*ucblocks = 0;
|
||
|
else
|
||
|
*ucblocks = (si21_readreg(state, 0x1d) << 8) |
|
||
|
si21_readreg(state, 0x1e);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
/* initiates a channel acquisition sequence
|
||
|
using the specified symbol rate and code rate */
|
||
|
static int si21xx_setacquire(struct dvb_frontend *fe, int symbrate,
|
||
|
fe_code_rate_t crate)
|
||
|
{
|
||
|
|
||
|
struct si21xx_state *state = fe->demodulator_priv;
|
||
|
u8 coderates[] = {
|
||
|
0x0, 0x01, 0x02, 0x04, 0x00,
|
||
|
0x8, 0x10, 0x20, 0x00, 0x3f
|
||
|
};
|
||
|
|
||
|
u8 coderate_ptr;
|
||
|
int status;
|
||
|
u8 start_acq = 0x80;
|
||
|
u8 reg, regs[3];
|
||
|
|
||
|
dprintk("%s\n", __func__);
|
||
|
|
||
|
status = PASS;
|
||
|
coderate_ptr = coderates[crate];
|
||
|
|
||
|
si21xx_set_symbolrate(fe, symbrate);
|
||
|
|
||
|
/* write code rates to use in the Viterbi search */
|
||
|
status |= si21_writeregs(state,
|
||
|
VIT_SRCH_CTRL_REG_1,
|
||
|
&coderate_ptr, 0x01);
|
||
|
|
||
|
/* clear acq_start bit */
|
||
|
status |= si21_readregs(state, ACQ_CTRL_REG_2, ®, 0x01);
|
||
|
reg &= ~start_acq;
|
||
|
status |= si21_writeregs(state, ACQ_CTRL_REG_2, ®, 0x01);
|
||
|
|
||
|
/* use new Carrier Frequency Offset Estimator (QuickLock) */
|
||
|
regs[0] = 0xCB;
|
||
|
regs[1] = 0x40;
|
||
|
regs[2] = 0xCB;
|
||
|
|
||
|
status |= si21_writeregs(state,
|
||
|
TWO_DB_BNDWDTH_THRSHLD_REG,
|
||
|
®s[0], 0x03);
|
||
|
reg = 0x56;
|
||
|
status |= si21_writeregs(state,
|
||
|
LSA_CTRL_REG_1, ®, 1);
|
||
|
reg = 0x05;
|
||
|
status |= si21_writeregs(state,
|
||
|
BLIND_SCAN_CTRL_REG, ®, 1);
|
||
|
/* start automatic acq */
|
||
|
status |= si21_writeregs(state,
|
||
|
ACQ_CTRL_REG_2, &start_acq, 0x01);
|
||
|
|
||
|
return status;
|
||
|
}
|
||
|
|
||
|
static int si21xx_set_property(struct dvb_frontend *fe, struct dtv_property *p)
|
||
|
{
|
||
|
dprintk("%s(..)\n", __func__);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int si21xx_get_property(struct dvb_frontend *fe, struct dtv_property *p)
|
||
|
{
|
||
|
dprintk("%s(..)\n", __func__);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int si21xx_set_frontend(struct dvb_frontend *fe,
|
||
|
struct dvb_frontend_parameters *dfp)
|
||
|
{
|
||
|
struct si21xx_state *state = fe->demodulator_priv;
|
||
|
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
||
|
|
||
|
/* freq Channel carrier frequency in KHz (i.e. 1550000 KHz)
|
||
|
datarate Channel symbol rate in Sps (i.e. 22500000 Sps)*/
|
||
|
|
||
|
/* in MHz */
|
||
|
unsigned char coarse_tune_freq;
|
||
|
int fine_tune_freq;
|
||
|
unsigned char sample_rate = 0;
|
||
|
/* boolean */
|
||
|
unsigned int inband_interferer_ind;
|
||
|
|
||
|
/* INTERMEDIATE VALUES */
|
||
|
int icoarse_tune_freq; /* MHz */
|
||
|
int ifine_tune_freq; /* MHz */
|
||
|
unsigned int band_high;
|
||
|
unsigned int band_low;
|
||
|
unsigned int x1;
|
||
|
unsigned int x2;
|
||
|
int i;
|
||
|
unsigned int inband_interferer_div2[ALLOWABLE_FS_COUNT] = {
|
||
|
FALSE, FALSE, FALSE, FALSE, FALSE,
|
||
|
FALSE, FALSE, FALSE, FALSE, FALSE
|
||
|
};
|
||
|
unsigned int inband_interferer_div4[ALLOWABLE_FS_COUNT] = {
|
||
|
FALSE, FALSE, FALSE, FALSE, FALSE,
|
||
|
FALSE, FALSE, FALSE, FALSE, FALSE
|
||
|
};
|
||
|
|
||
|
int status;
|
||
|
|
||
|
/* allowable sample rates for ADC in MHz */
|
||
|
int afs[ALLOWABLE_FS_COUNT] = { 200, 192, 193, 194, 195,
|
||
|
196, 204, 205, 206, 207
|
||
|
};
|
||
|
/* in MHz */
|
||
|
int if_limit_high;
|
||
|
int if_limit_low;
|
||
|
int lnb_lo;
|
||
|
int lnb_uncertanity;
|
||
|
|
||
|
int rf_freq;
|
||
|
int data_rate;
|
||
|
unsigned char regs[4];
|
||
|
|
||
|
dprintk("%s : FE_SET_FRONTEND\n", __func__);
|
||
|
|
||
|
if (c->delivery_system != SYS_DVBS) {
|
||
|
dprintk("%s: unsupported delivery system selected (%d)\n",
|
||
|
__func__, c->delivery_system);
|
||
|
return -EOPNOTSUPP;
|
||
|
}
|
||
|
|
||
|
for (i = 0; i < ALLOWABLE_FS_COUNT; ++i)
|
||
|
inband_interferer_div2[i] = inband_interferer_div4[i] = FALSE;
|
||
|
|
||
|
if_limit_high = -700000;
|
||
|
if_limit_low = -100000;
|
||
|
/* in MHz */
|
||
|
lnb_lo = 0;
|
||
|
lnb_uncertanity = 0;
|
||
|
|
||
|
rf_freq = 10 * c->frequency ;
|
||
|
data_rate = c->symbol_rate / 100;
|
||
|
|
||
|
status = PASS;
|
||
|
|
||
|
band_low = (rf_freq - lnb_lo) - ((lnb_uncertanity * 200)
|
||
|
+ (data_rate * 135)) / 200;
|
||
|
|
||
|
band_high = (rf_freq - lnb_lo) + ((lnb_uncertanity * 200)
|
||
|
+ (data_rate * 135)) / 200;
|
||
|
|
||
|
|
||
|
icoarse_tune_freq = 100000 *
|
||
|
(((rf_freq - lnb_lo) -
|
||
|
(if_limit_low + if_limit_high) / 2)
|
||
|
/ 100000);
|
||
|
|
||
|
ifine_tune_freq = (rf_freq - lnb_lo) - icoarse_tune_freq ;
|
||
|
|
||
|
for (i = 0; i < ALLOWABLE_FS_COUNT; ++i) {
|
||
|
x1 = ((rf_freq - lnb_lo) / (afs[i] * 2500)) *
|
||
|
(afs[i] * 2500) + afs[i] * 2500;
|
||
|
|
||
|
x2 = ((rf_freq - lnb_lo) / (afs[i] * 2500)) *
|
||
|
(afs[i] * 2500);
|
||
|
|
||
|
if (((band_low < x1) && (x1 < band_high)) ||
|
||
|
((band_low < x2) && (x2 < band_high)))
|
||
|
inband_interferer_div4[i] = TRUE;
|
||
|
|
||
|
}
|
||
|
|
||
|
for (i = 0; i < ALLOWABLE_FS_COUNT; ++i) {
|
||
|
x1 = ((rf_freq - lnb_lo) / (afs[i] * 5000)) *
|
||
|
(afs[i] * 5000) + afs[i] * 5000;
|
||
|
|
||
|
x2 = ((rf_freq - lnb_lo) / (afs[i] * 5000)) *
|
||
|
(afs[i] * 5000);
|
||
|
|
||
|
if (((band_low < x1) && (x1 < band_high)) ||
|
||
|
((band_low < x2) && (x2 < band_high)))
|
||
|
inband_interferer_div2[i] = TRUE;
|
||
|
}
|
||
|
|
||
|
inband_interferer_ind = TRUE;
|
||
|
for (i = 0; i < ALLOWABLE_FS_COUNT; ++i)
|
||
|
inband_interferer_ind &= inband_interferer_div2[i] |
|
||
|
inband_interferer_div4[i];
|
||
|
|
||
|
if (inband_interferer_ind) {
|
||
|
for (i = 0; i < ALLOWABLE_FS_COUNT; ++i) {
|
||
|
if (inband_interferer_div2[i] == FALSE) {
|
||
|
sample_rate = (u8) afs[i];
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
} else {
|
||
|
for (i = 0; i < ALLOWABLE_FS_COUNT; ++i) {
|
||
|
if ((inband_interferer_div2[i] |
|
||
|
inband_interferer_div4[i]) == FALSE) {
|
||
|
sample_rate = (u8) afs[i];
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
}
|
||
|
|
||
|
if (sample_rate > 207 || sample_rate < 192)
|
||
|
sample_rate = 200;
|
||
|
|
||
|
fine_tune_freq = ((0x4000 * (ifine_tune_freq / 10)) /
|
||
|
((sample_rate) * 1000));
|
||
|
|
||
|
coarse_tune_freq = (u8)(icoarse_tune_freq / 100000);
|
||
|
|
||
|
regs[0] = sample_rate;
|
||
|
regs[1] = coarse_tune_freq;
|
||
|
regs[2] = fine_tune_freq & 0xFF;
|
||
|
regs[3] = fine_tune_freq >> 8 & 0xFF;
|
||
|
|
||
|
status |= si21_writeregs(state, PLL_DIVISOR_REG, ®s[0], 0x04);
|
||
|
|
||
|
state->fs = sample_rate;/*ADC MHz*/
|
||
|
si21xx_setacquire(fe, c->symbol_rate, c->fec_inner);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int si21xx_sleep(struct dvb_frontend *fe)
|
||
|
{
|
||
|
struct si21xx_state *state = fe->demodulator_priv;
|
||
|
u8 regdata;
|
||
|
|
||
|
dprintk("%s\n", __func__);
|
||
|
|
||
|
si21_readregs(state, SYSTEM_MODE_REG, ®data, 0x01);
|
||
|
regdata |= 1 << 6;
|
||
|
si21_writeregs(state, SYSTEM_MODE_REG, ®data, 0x01);
|
||
|
state->initialised = 0;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static void si21xx_release(struct dvb_frontend *fe)
|
||
|
{
|
||
|
struct si21xx_state *state = fe->demodulator_priv;
|
||
|
|
||
|
dprintk("%s\n", __func__);
|
||
|
|
||
|
kfree(state);
|
||
|
}
|
||
|
|
||
|
static struct dvb_frontend_ops si21xx_ops = {
|
||
|
|
||
|
.info = {
|
||
|
.name = "SL SI21XX DVB-S",
|
||
|
.type = FE_QPSK,
|
||
|
.frequency_min = 950000,
|
||
|
.frequency_max = 2150000,
|
||
|
.frequency_stepsize = 125, /* kHz for QPSK frontends */
|
||
|
.frequency_tolerance = 0,
|
||
|
.symbol_rate_min = 1000000,
|
||
|
.symbol_rate_max = 45000000,
|
||
|
.symbol_rate_tolerance = 500, /* ppm */
|
||
|
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
||
|
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
|
||
|
FE_CAN_QPSK |
|
||
|
FE_CAN_FEC_AUTO
|
||
|
},
|
||
|
|
||
|
.release = si21xx_release,
|
||
|
.init = si21xx_init,
|
||
|
.sleep = si21xx_sleep,
|
||
|
.write = si21_write,
|
||
|
.read_status = si21_read_status,
|
||
|
.read_ber = si21_read_ber,
|
||
|
.read_signal_strength = si21_read_signal_strength,
|
||
|
.read_snr = si21_read_snr,
|
||
|
.read_ucblocks = si21_read_ucblocks,
|
||
|
.diseqc_send_master_cmd = si21xx_send_diseqc_msg,
|
||
|
.diseqc_send_burst = si21xx_send_diseqc_burst,
|
||
|
.set_tone = si21xx_set_tone,
|
||
|
.set_voltage = si21xx_set_voltage,
|
||
|
|
||
|
.set_property = si21xx_set_property,
|
||
|
.get_property = si21xx_get_property,
|
||
|
.set_frontend = si21xx_set_frontend,
|
||
|
};
|
||
|
|
||
|
struct dvb_frontend *si21xx_attach(const struct si21xx_config *config,
|
||
|
struct i2c_adapter *i2c)
|
||
|
{
|
||
|
struct si21xx_state *state = NULL;
|
||
|
int id;
|
||
|
|
||
|
dprintk("%s\n", __func__);
|
||
|
|
||
|
/* allocate memory for the internal state */
|
||
|
state = kmalloc(sizeof(struct si21xx_state), GFP_KERNEL);
|
||
|
if (state == NULL)
|
||
|
goto error;
|
||
|
|
||
|
/* setup the state */
|
||
|
state->config = config;
|
||
|
state->i2c = i2c;
|
||
|
state->initialised = 0;
|
||
|
state->errmode = STATUS_BER;
|
||
|
|
||
|
/* check if the demod is there */
|
||
|
id = si21_readreg(state, SYSTEM_MODE_REG);
|
||
|
si21_writereg(state, SYSTEM_MODE_REG, id | 0x40); /* standby off */
|
||
|
msleep(200);
|
||
|
id = si21_readreg(state, 0x00);
|
||
|
|
||
|
/* register 0x00 contains:
|
||
|
0x34 for SI2107
|
||
|
0x24 for SI2108
|
||
|
0x14 for SI2109
|
||
|
0x04 for SI2110
|
||
|
*/
|
||
|
if (id != 0x04 && id != 0x14)
|
||
|
goto error;
|
||
|
|
||
|
/* create dvb_frontend */
|
||
|
memcpy(&state->frontend.ops, &si21xx_ops,
|
||
|
sizeof(struct dvb_frontend_ops));
|
||
|
state->frontend.demodulator_priv = state;
|
||
|
return &state->frontend;
|
||
|
|
||
|
error:
|
||
|
kfree(state);
|
||
|
return NULL;
|
||
|
}
|
||
|
EXPORT_SYMBOL(si21xx_attach);
|
||
|
|
||
|
module_param(debug, int, 0644);
|
||
|
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
|
||
|
|
||
|
MODULE_DESCRIPTION("SL SI21XX DVB Demodulator driver");
|
||
|
MODULE_AUTHOR("Igor M. Liplianin");
|
||
|
MODULE_LICENSE("GPL");
|