2018-11-15 17:14:47 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2018-09-28 11:10:04 +08:00
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/*
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2018-11-15 17:14:47 +08:00
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* nau8822.h -- NAU8822 ALSA SoC Audio driver
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*
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* Copyright 2017 Nuvoton Technology Crop.
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2018-09-28 11:10:04 +08:00
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*
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* Author: David Lin <ctlin0@nuvoton.com>
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2018-11-15 17:49:13 +08:00
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* Co-author: John Hsu <kchsu0@nuvoton.com>
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2018-09-28 11:10:04 +08:00
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* Co-author: Seven Li <wtli@nuvoton.com>
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*/
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#ifndef __NAU8822_H__
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#define __NAU8822_H__
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#define NAU8822_REG_RESET 0x00
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#define NAU8822_REG_POWER_MANAGEMENT_1 0x01
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#define NAU8822_REG_POWER_MANAGEMENT_2 0x02
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#define NAU8822_REG_POWER_MANAGEMENT_3 0x03
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#define NAU8822_REG_AUDIO_INTERFACE 0x04
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#define NAU8822_REG_COMPANDING_CONTROL 0x05
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#define NAU8822_REG_CLOCKING 0x06
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#define NAU8822_REG_ADDITIONAL_CONTROL 0x07
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#define NAU8822_REG_GPIO_CONTROL 0x08
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#define NAU8822_REG_JACK_DETECT_CONTROL_1 0x09
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#define NAU8822_REG_DAC_CONTROL 0x0A
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#define NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME 0x0B
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#define NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME 0x0C
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#define NAU8822_REG_JACK_DETECT_CONTROL_2 0x0D
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#define NAU8822_REG_ADC_CONTROL 0x0E
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#define NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME 0x0F
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#define NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME 0x10
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#define NAU8822_REG_EQ1 0x12
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#define NAU8822_REG_EQ2 0x13
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#define NAU8822_REG_EQ3 0x14
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#define NAU8822_REG_EQ4 0x15
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#define NAU8822_REG_EQ5 0x16
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#define NAU8822_REG_DAC_LIMITER_1 0x18
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#define NAU8822_REG_DAC_LIMITER_2 0x19
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#define NAU8822_REG_NOTCH_FILTER_1 0x1B
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#define NAU8822_REG_NOTCH_FILTER_2 0x1C
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#define NAU8822_REG_NOTCH_FILTER_3 0x1D
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#define NAU8822_REG_NOTCH_FILTER_4 0x1E
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#define NAU8822_REG_ALC_CONTROL_1 0x20
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#define NAU8822_REG_ALC_CONTROL_2 0x21
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#define NAU8822_REG_ALC_CONTROL_3 0x22
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#define NAU8822_REG_NOISE_GATE 0x23
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#define NAU8822_REG_PLL_N 0x24
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#define NAU8822_REG_PLL_K1 0x25
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#define NAU8822_REG_PLL_K2 0x26
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#define NAU8822_REG_PLL_K3 0x27
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#define NAU8822_REG_3D_CONTROL 0x29
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#define NAU8822_REG_RIGHT_SPEAKER_CONTROL 0x2B
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#define NAU8822_REG_INPUT_CONTROL 0x2C
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#define NAU8822_REG_LEFT_INP_PGA_CONTROL 0x2D
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#define NAU8822_REG_RIGHT_INP_PGA_CONTROL 0x2E
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#define NAU8822_REG_LEFT_ADC_BOOST_CONTROL 0x2F
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#define NAU8822_REG_RIGHT_ADC_BOOST_CONTROL 0x30
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#define NAU8822_REG_OUTPUT_CONTROL 0x31
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#define NAU8822_REG_LEFT_MIXER_CONTROL 0x32
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#define NAU8822_REG_RIGHT_MIXER_CONTROL 0x33
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#define NAU8822_REG_LHP_VOLUME 0x34
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#define NAU8822_REG_RHP_VOLUME 0x35
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#define NAU8822_REG_LSPKOUT_VOLUME 0x36
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#define NAU8822_REG_RSPKOUT_VOLUME 0x37
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#define NAU8822_REG_AUX2_MIXER 0x38
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#define NAU8822_REG_AUX1_MIXER 0x39
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#define NAU8822_REG_POWER_MANAGEMENT_4 0x3A
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#define NAU8822_REG_LEFT_TIME_SLOT 0x3B
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#define NAU8822_REG_MISC 0x3C
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#define NAU8822_REG_RIGHT_TIME_SLOT 0x3D
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#define NAU8822_REG_DEVICE_REVISION 0x3E
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#define NAU8822_REG_DEVICE_ID 0x3F
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#define NAU8822_REG_DAC_DITHER 0x41
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#define NAU8822_REG_ALC_ENHANCE_1 0x46
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#define NAU8822_REG_ALC_ENHANCE_2 0x47
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#define NAU8822_REG_192KHZ_SAMPLING 0x48
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#define NAU8822_REG_MISC_CONTROL 0x49
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#define NAU8822_REG_INPUT_TIEOFF 0x4A
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#define NAU8822_REG_POWER_REDUCTION 0x4B
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#define NAU8822_REG_AGC_PEAK2PEAK 0x4C
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#define NAU8822_REG_AGC_PEAK_DETECT 0x4D
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#define NAU8822_REG_AUTOMUTE_CONTROL 0x4E
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#define NAU8822_REG_OUTPUT_TIEOFF 0x4F
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#define NAU8822_REG_MAX_REGISTER NAU8822_REG_OUTPUT_TIEOFF
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/* NAU8822_REG_POWER_MANAGEMENT_1 (0x1) */
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#define NAU8822_REFIMP_MASK 0x3
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#define NAU8822_REFIMP_80K 0x1
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#define NAU8822_REFIMP_300K 0x2
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#define NAU8822_REFIMP_3K 0x3
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#define NAU8822_IOBUF_EN (0x1 << 2)
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#define NAU8822_ABIAS_EN (0x1 << 3)
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/* NAU8822_REG_AUDIO_INTERFACE (0x4) */
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#define NAU8822_AIFMT_MASK (0x3 << 3)
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#define NAU8822_WLEN_MASK (0x3 << 5)
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#define NAU8822_WLEN_20 (0x1 << 5)
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#define NAU8822_WLEN_24 (0x2 << 5)
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#define NAU8822_WLEN_32 (0x3 << 5)
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#define NAU8822_LRP_MASK (0x1 << 7)
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#define NAU8822_BCLKP_MASK (0x1 << 8)
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/* NAU8822_REG_COMPANDING_CONTROL (0x5) */
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#define NAU8822_ADDAP_SFT 0
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#define NAU8822_ADCCM_SFT 1
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#define NAU8822_DACCM_SFT 3
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/* NAU8822_REG_CLOCKING (0x6) */
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#define NAU8822_CLKIOEN_MASK 0x1
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2019-06-10 11:05:23 +08:00
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#define NAU8822_CLK_MASTER 0x1
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#define NAU8822_CLK_SLAVE 0x0
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2018-09-28 11:10:04 +08:00
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#define NAU8822_MCLKSEL_SFT 5
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#define NAU8822_MCLKSEL_MASK (0x7 << 5)
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#define NAU8822_BCLKSEL_SFT 2
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#define NAU8822_BCLKSEL_MASK (0x7 << 2)
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2019-06-10 11:05:23 +08:00
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#define NAU8822_BCLKDIV_1 (0x0 << 2)
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#define NAU8822_BCLKDIV_2 (0x1 << 2)
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#define NAU8822_BCLKDIV_4 (0x2 << 2)
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#define NAU8822_BCLKDIV_8 (0x3 << 2)
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#define NAU8822_BCLKDIV_16 (0x4 << 2)
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2018-09-28 11:10:04 +08:00
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#define NAU8822_CLKM_MASK (0x1 << 8)
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#define NAU8822_CLKM_MCLK (0x0 << 8)
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#define NAU8822_CLKM_PLL (0x1 << 8)
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/* NAU8822_REG_ADDITIONAL_CONTROL (0x08) */
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#define NAU8822_SMPLR_SFT 1
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#define NAU8822_SMPLR_MASK (0x7 << 1)
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#define NAU8822_SMPLR_48K (0x0 << 1)
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#define NAU8822_SMPLR_32K (0x1 << 1)
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#define NAU8822_SMPLR_24K (0x2 << 1)
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#define NAU8822_SMPLR_16K (0x3 << 1)
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#define NAU8822_SMPLR_12K (0x4 << 1)
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#define NAU8822_SMPLR_8K (0x5 << 1)
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/* NAU8822_REG_EQ1 (0x12) */
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#define NAU8822_EQ1GC_SFT 0
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#define NAU8822_EQ1CF_SFT 5
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#define NAU8822_EQM_SFT 8
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/* NAU8822_REG_EQ2 (0x13) */
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#define NAU8822_EQ2GC_SFT 0
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#define NAU8822_EQ2CF_SFT 5
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#define NAU8822_EQ2BW_SFT 8
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/* NAU8822_REG_EQ3 (0x14) */
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#define NAU8822_EQ3GC_SFT 0
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#define NAU8822_EQ3CF_SFT 5
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#define NAU8822_EQ3BW_SFT 8
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/* NAU8822_REG_EQ4 (0x15) */
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#define NAU8822_EQ4GC_SFT 0
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#define NAU8822_EQ4CF_SFT 5
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#define NAU8822_EQ4BW_SFT 8
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/* NAU8822_REG_EQ5 (0x16) */
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#define NAU8822_EQ5GC_SFT 0
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#define NAU8822_EQ5CF_SFT 5
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/* NAU8822_REG_ALC_CONTROL_1 (0x20) */
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#define NAU8822_ALCMINGAIN_SFT 0
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#define NAU8822_ALCMXGAIN_SFT 3
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#define NAU8822_ALCEN_SFT 7
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/* NAU8822_REG_ALC_CONTROL_2 (0x21) */
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#define NAU8822_ALCSL_SFT 0
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#define NAU8822_ALCHT_SFT 4
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/* NAU8822_REG_ALC_CONTROL_3 (0x22) */
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#define NAU8822_ALCATK_SFT 0
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#define NAU8822_ALCDCY_SFT 4
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#define NAU8822_ALCM_SFT 8
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/* NAU8822_REG_PLL_N (0x24) */
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#define NAU8822_PLLMCLK_DIV2 (0x1 << 4)
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#define NAU8822_PLLN_MASK 0xF
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#define NAU8822_PLLK1_SFT 18
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#define NAU8822_PLLK1_MASK 0x3F
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/* NAU8822_REG_PLL_K2 (0x26) */
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#define NAU8822_PLLK2_SFT 9
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#define NAU8822_PLLK2_MASK 0x1FF
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/* NAU8822_REG_PLL_K3 (0x27) */
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#define NAU8822_PLLK3_MASK 0x1FF
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/* System Clock Source */
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enum {
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NAU8822_CLK_MCLK,
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NAU8822_CLK_PLL,
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};
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struct nau8822_pll {
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int pre_factor;
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int mclk_scaler;
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int pll_frac;
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int pll_int;
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};
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/* Codec Private Data */
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struct nau8822 {
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struct device *dev;
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struct regmap *regmap;
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int mclk_idx;
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struct nau8822_pll pll;
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int sysclk;
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int div_id;
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};
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#endif /* __NAU8822_H__ */
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