2019-05-29 22:18:02 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2015-03-24 22:54:56 +08:00
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/*
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* Copyright © 2015 Intel Corporation.
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*
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* Authors: David Woodhouse <dwmw2@infradead.org>
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*/
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#include <linux/intel-iommu.h>
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2015-09-09 18:40:47 +08:00
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#include <linux/mmu_notifier.h>
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#include <linux/sched.h>
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2017-02-09 01:51:29 +08:00
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#include <linux/sched/mm.h>
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2015-09-09 18:40:47 +08:00
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#include <linux/slab.h>
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#include <linux/intel-svm.h>
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#include <linux/rculist.h>
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#include <linux/pci.h>
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#include <linux/pci-ats.h>
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2015-10-08 06:35:18 +08:00
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#include <linux/dmar.h>
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#include <linux/interrupt.h>
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2018-08-18 06:44:47 +08:00
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#include <linux/mm_types.h>
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2021-06-10 10:00:58 +08:00
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#include <linux/xarray.h>
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2020-01-02 08:18:08 +08:00
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#include <linux/ioasid.h>
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2017-08-09 04:29:27 +08:00
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#include <asm/page.h>
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2020-09-16 00:30:13 +08:00
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#include <asm/fpu/api.h>
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2021-06-10 10:01:04 +08:00
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#include <trace/events/intel_iommu.h>
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2015-10-08 06:35:18 +08:00
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2020-07-24 09:49:25 +08:00
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#include "pasid.h"
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2021-06-10 10:01:08 +08:00
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#include "perf.h"
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2021-06-10 10:00:59 +08:00
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#include "../iommu-sva-lib.h"
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2018-07-14 15:46:56 +08:00
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2015-10-08 06:35:18 +08:00
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static irqreturn_t prq_event_thread(int irq, void *d);
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2020-09-16 00:30:05 +08:00
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static void intel_svm_drain_prq(struct device *dev, u32 pasid);
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2021-06-10 10:00:59 +08:00
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#define to_intel_svm_dev(handle) container_of(handle, struct intel_svm_dev, sva)
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2015-09-09 18:40:47 +08:00
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2021-06-10 10:00:58 +08:00
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static DEFINE_XARRAY_ALLOC(pasid_private_array);
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static int pasid_private_add(ioasid_t pasid, void *priv)
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{
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return xa_alloc(&pasid_private_array, &pasid, priv,
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XA_LIMIT(pasid, pasid), GFP_ATOMIC);
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}
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static void pasid_private_remove(ioasid_t pasid)
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{
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xa_erase(&pasid_private_array, pasid);
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}
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static void *pasid_private_find(ioasid_t pasid)
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{
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return xa_load(&pasid_private_array, pasid);
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}
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2021-06-10 10:01:00 +08:00
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static struct intel_svm_dev *
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svm_lookup_device_by_sid(struct intel_svm *svm, u16 sid)
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{
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struct intel_svm_dev *sdev = NULL, *t;
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rcu_read_lock();
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list_for_each_entry_rcu(t, &svm->devs, list) {
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if (t->sid == sid) {
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sdev = t;
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break;
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}
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}
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rcu_read_unlock();
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return sdev;
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}
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static struct intel_svm_dev *
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svm_lookup_device_by_dev(struct intel_svm *svm, struct device *dev)
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{
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struct intel_svm_dev *sdev = NULL, *t;
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rcu_read_lock();
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list_for_each_entry_rcu(t, &svm->devs, list) {
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if (t->dev == dev) {
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sdev = t;
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break;
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}
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}
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rcu_read_unlock();
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return sdev;
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}
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2015-10-08 06:35:18 +08:00
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int intel_svm_enable_prq(struct intel_iommu *iommu)
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{
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2021-06-10 10:01:02 +08:00
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struct iopf_queue *iopfq;
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2015-10-08 06:35:18 +08:00
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struct page *pages;
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int irq, ret;
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pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
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if (!pages) {
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pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
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iommu->name);
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return -ENOMEM;
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}
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iommu->prq = page_address(pages);
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irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
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if (irq <= 0) {
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pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
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iommu->name);
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ret = -EINVAL;
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2021-06-10 10:01:02 +08:00
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goto free_prq;
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2015-10-08 06:35:18 +08:00
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}
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iommu->pr_irq = irq;
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2021-06-10 10:01:02 +08:00
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snprintf(iommu->iopfq_name, sizeof(iommu->iopfq_name),
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"dmar%d-iopfq", iommu->seq_id);
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iopfq = iopf_queue_alloc(iommu->iopfq_name);
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if (!iopfq) {
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pr_err("IOMMU: %s: Failed to allocate iopf queue\n", iommu->name);
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ret = -ENOMEM;
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goto free_hwirq;
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}
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iommu->iopf_queue = iopfq;
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2015-10-08 06:35:18 +08:00
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snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
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ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
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iommu->prq_name, iommu);
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if (ret) {
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pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
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iommu->name);
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2021-06-10 10:01:02 +08:00
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goto free_iopfq;
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2015-10-08 06:35:18 +08:00
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}
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dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
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2020-05-16 14:20:58 +08:00
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init_completion(&iommu->prq_complete);
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2015-10-08 06:35:18 +08:00
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return 0;
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2021-06-10 10:01:02 +08:00
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free_iopfq:
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iopf_queue_free(iommu->iopf_queue);
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iommu->iopf_queue = NULL;
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free_hwirq:
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dmar_free_hwirq(irq);
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iommu->pr_irq = 0;
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free_prq:
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free_pages((unsigned long)iommu->prq, PRQ_ORDER);
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iommu->prq = NULL;
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return ret;
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2015-10-08 06:35:18 +08:00
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}
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int intel_svm_finish_prq(struct intel_iommu *iommu)
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{
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dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
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2017-12-21 00:48:56 +08:00
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if (iommu->pr_irq) {
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free_irq(iommu->pr_irq, iommu);
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dmar_free_hwirq(iommu->pr_irq);
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iommu->pr_irq = 0;
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}
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2015-10-08 06:35:18 +08:00
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2021-06-10 10:01:02 +08:00
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if (iommu->iopf_queue) {
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iopf_queue_free(iommu->iopf_queue);
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iommu->iopf_queue = NULL;
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}
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2015-10-08 06:35:18 +08:00
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free_pages((unsigned long)iommu->prq, PRQ_ORDER);
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iommu->prq = NULL;
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return 0;
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}
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2020-01-02 08:18:03 +08:00
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void intel_svm_check(struct intel_iommu *iommu)
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{
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if (!pasid_supported(iommu))
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return;
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if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
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!cap_fl1gp_support(iommu->cap)) {
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pr_err("%s SVM disabled, incompatible 1GB page capability\n",
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iommu->name);
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return;
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}
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if (cpu_feature_enabled(X86_FEATURE_LA57) &&
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!cap_5lp_support(iommu->cap)) {
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pr_err("%s SVM disabled, incompatible paging mode\n",
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iommu->name);
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return;
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}
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iommu->flags |= VTD_FLAG_SVM_CAPABLE;
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}
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2020-12-31 08:53:20 +08:00
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static void __flush_svm_range_dev(struct intel_svm *svm,
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struct intel_svm_dev *sdev,
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unsigned long address,
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unsigned long pages, int ih)
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2015-09-09 18:40:47 +08:00
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{
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2022-03-01 10:01:52 +08:00
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struct device_domain_info *info = dev_iommu_priv_get(sdev->dev);
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2021-01-14 16:50:21 +08:00
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if (WARN_ON(!pages))
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return;
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qi_flush_piotlb(sdev->iommu, sdev->did, svm->pasid, address, pages, ih);
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if (info->ats_enabled)
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qi_flush_dev_iotlb_pasid(sdev->iommu, sdev->sid, info->pfsid,
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svm->pasid, sdev->qdep, address,
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order_base_2(pages));
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2015-09-09 18:40:47 +08:00
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}
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2020-12-31 08:53:20 +08:00
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static void intel_flush_svm_range_dev(struct intel_svm *svm,
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struct intel_svm_dev *sdev,
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unsigned long address,
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unsigned long pages, int ih)
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{
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unsigned long shift = ilog2(__roundup_pow_of_two(pages));
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unsigned long align = (1ULL << (VTD_PAGE_SHIFT + shift));
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unsigned long start = ALIGN_DOWN(address, align);
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unsigned long end = ALIGN(address + (pages << VTD_PAGE_SHIFT), align);
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while (start < end) {
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__flush_svm_range_dev(svm, sdev, start, align >> VTD_PAGE_SHIFT, ih);
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start += align;
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}
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}
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2015-09-09 18:40:47 +08:00
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static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
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2019-08-26 23:53:29 +08:00
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unsigned long pages, int ih)
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2015-09-09 18:40:47 +08:00
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{
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struct intel_svm_dev *sdev;
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rcu_read_lock();
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list_for_each_entry_rcu(sdev, &svm->devs, list)
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2019-08-26 23:53:29 +08:00
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intel_flush_svm_range_dev(svm, sdev, address, pages, ih);
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2015-09-09 18:40:47 +08:00
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rcu_read_unlock();
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}
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/* Pages have been freed at this point */
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static void intel_invalidate_range(struct mmu_notifier *mn,
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struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
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intel_flush_svm_range(svm, start,
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2019-08-26 23:53:29 +08:00
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(end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0);
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2015-09-09 18:40:47 +08:00
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}
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static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
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{
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struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
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iommu/vt-d: Fix mm refcounting to hold mm_count not mm_users
Holding mm_users works OK for graphics, which was the first user of SVM
with VT-d. However, it works less well for other devices, where we actually
do a mmap() from the file descriptor to which the SVM PASID state is tied.
In this case on process exit we end up with a recursive reference count:
- The MM remains alive until the file is closed and the driver's release()
call ends up unbinding the PASID.
- The VMA corresponding to the mmap() remains intact until the MM is
destroyed.
- Thus the file isn't closed, even when exit_files() runs, because the
VMA is still holding a reference to it. And the MM remains alive…
To address this issue, we *stop* holding mm_users while the PASID is bound.
We already hold mm_count by virtue of the MMU notifier, and that can be
made to be sufficient.
It means that for a period during process exit, the fun part of mmput()
has happened and exit_mmap() has been called so the MM is basically
defunct. But the PGD still exists and the PASID is still bound to it.
During this period, we have to be very careful — exit_mmap() doesn't use
mm->mmap_sem because it doesn't expect anyone else to be touching the MM
(quite reasonably, since mm_users is zero). So we also need to fix the
fault handler to just report failure if mm_users is already zero, and to
temporarily bump mm_users while handling any faults.
Additionally, exit_mmap() calls mmu_notifier_release() *before* it tears
down the page tables, which is too early for us to flush the IOTLB for
this PASID. And __mmu_notifier_release() removes every notifier from the
list, so when exit_mmap() finally *does* tear down the mappings and
clear the page tables, we don't get notified. So we work around this by
clearing the PASID table entry in our MMU notifier release() callback.
That way, the hardware *can't* get any pages back from the page tables
before they get cleared.
Hardware designers have confirmed that the resulting 'PASID not present'
faults should be handled just as gracefully as 'page not present' faults,
the important criterion being that they don't perturb the operation for
any *other* PASID in the system.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Cc: stable@vger.kernel.org
2016-01-13 03:18:06 +08:00
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struct intel_svm_dev *sdev;
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2015-09-09 18:40:47 +08:00
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iommu/vt-d: Fix mm refcounting to hold mm_count not mm_users
Holding mm_users works OK for graphics, which was the first user of SVM
with VT-d. However, it works less well for other devices, where we actually
do a mmap() from the file descriptor to which the SVM PASID state is tied.
In this case on process exit we end up with a recursive reference count:
- The MM remains alive until the file is closed and the driver's release()
call ends up unbinding the PASID.
- The VMA corresponding to the mmap() remains intact until the MM is
destroyed.
- Thus the file isn't closed, even when exit_files() runs, because the
VMA is still holding a reference to it. And the MM remains alive…
To address this issue, we *stop* holding mm_users while the PASID is bound.
We already hold mm_count by virtue of the MMU notifier, and that can be
made to be sufficient.
It means that for a period during process exit, the fun part of mmput()
has happened and exit_mmap() has been called so the MM is basically
defunct. But the PGD still exists and the PASID is still bound to it.
During this period, we have to be very careful — exit_mmap() doesn't use
mm->mmap_sem because it doesn't expect anyone else to be touching the MM
(quite reasonably, since mm_users is zero). So we also need to fix the
fault handler to just report failure if mm_users is already zero, and to
temporarily bump mm_users while handling any faults.
Additionally, exit_mmap() calls mmu_notifier_release() *before* it tears
down the page tables, which is too early for us to flush the IOTLB for
this PASID. And __mmu_notifier_release() removes every notifier from the
list, so when exit_mmap() finally *does* tear down the mappings and
clear the page tables, we don't get notified. So we work around this by
clearing the PASID table entry in our MMU notifier release() callback.
That way, the hardware *can't* get any pages back from the page tables
before they get cleared.
Hardware designers have confirmed that the resulting 'PASID not present'
faults should be handled just as gracefully as 'page not present' faults,
the important criterion being that they don't perturb the operation for
any *other* PASID in the system.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Cc: stable@vger.kernel.org
2016-01-13 03:18:06 +08:00
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/* This might end up being called from exit_mmap(), *before* the page
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* tables are cleared. And __mmu_notifier_release() will delete us from
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* the list of notifiers so that our invalidate_range() callback doesn't
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* get called when the page tables are cleared. So we need to protect
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* against hardware accessing those page tables.
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*
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* We do it by clearing the entry in the PASID table and then flushing
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* the IOTLB and the PASID table caches. This might upset hardware;
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* perhaps we'll want to point the PASID to a dummy PGD (like the zero
|
|
|
|
* page) so that we end up taking a fault that the hardware really
|
|
|
|
* *has* to handle gracefully without affecting other processes.
|
|
|
|
*/
|
|
|
|
rcu_read_lock();
|
2020-05-16 14:20:59 +08:00
|
|
|
list_for_each_entry_rcu(sdev, &svm->devs, list)
|
2021-01-07 00:03:55 +08:00
|
|
|
intel_pasid_tear_down_entry(sdev->iommu, sdev->dev,
|
2020-05-16 14:20:57 +08:00
|
|
|
svm->pasid, true);
|
iommu/vt-d: Fix mm refcounting to hold mm_count not mm_users
Holding mm_users works OK for graphics, which was the first user of SVM
with VT-d. However, it works less well for other devices, where we actually
do a mmap() from the file descriptor to which the SVM PASID state is tied.
In this case on process exit we end up with a recursive reference count:
- The MM remains alive until the file is closed and the driver's release()
call ends up unbinding the PASID.
- The VMA corresponding to the mmap() remains intact until the MM is
destroyed.
- Thus the file isn't closed, even when exit_files() runs, because the
VMA is still holding a reference to it. And the MM remains alive…
To address this issue, we *stop* holding mm_users while the PASID is bound.
We already hold mm_count by virtue of the MMU notifier, and that can be
made to be sufficient.
It means that for a period during process exit, the fun part of mmput()
has happened and exit_mmap() has been called so the MM is basically
defunct. But the PGD still exists and the PASID is still bound to it.
During this period, we have to be very careful — exit_mmap() doesn't use
mm->mmap_sem because it doesn't expect anyone else to be touching the MM
(quite reasonably, since mm_users is zero). So we also need to fix the
fault handler to just report failure if mm_users is already zero, and to
temporarily bump mm_users while handling any faults.
Additionally, exit_mmap() calls mmu_notifier_release() *before* it tears
down the page tables, which is too early for us to flush the IOTLB for
this PASID. And __mmu_notifier_release() removes every notifier from the
list, so when exit_mmap() finally *does* tear down the mappings and
clear the page tables, we don't get notified. So we work around this by
clearing the PASID table entry in our MMU notifier release() callback.
That way, the hardware *can't* get any pages back from the page tables
before they get cleared.
Hardware designers have confirmed that the resulting 'PASID not present'
faults should be handled just as gracefully as 'page not present' faults,
the important criterion being that they don't perturb the operation for
any *other* PASID in the system.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Cc: stable@vger.kernel.org
2016-01-13 03:18:06 +08:00
|
|
|
rcu_read_unlock();
|
2015-09-09 18:40:47 +08:00
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct mmu_notifier_ops intel_mmuops = {
|
|
|
|
.release = intel_mm_release,
|
|
|
|
.invalidate_range = intel_invalidate_range,
|
|
|
|
};
|
|
|
|
|
|
|
|
static DEFINE_MUTEX(pasid_mutex);
|
|
|
|
|
2020-07-24 09:49:22 +08:00
|
|
|
static int pasid_to_svm_sdev(struct device *dev, unsigned int pasid,
|
|
|
|
struct intel_svm **rsvm,
|
|
|
|
struct intel_svm_dev **rsdev)
|
|
|
|
{
|
2021-06-10 10:01:00 +08:00
|
|
|
struct intel_svm_dev *sdev = NULL;
|
2020-07-24 09:49:22 +08:00
|
|
|
struct intel_svm *svm;
|
|
|
|
|
|
|
|
/* The caller should hold the pasid_mutex lock */
|
|
|
|
if (WARN_ON(!mutex_is_locked(&pasid_mutex)))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (pasid == INVALID_IOASID || pasid >= PASID_MAX)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2021-06-10 10:00:58 +08:00
|
|
|
svm = pasid_private_find(pasid);
|
2020-07-24 09:49:22 +08:00
|
|
|
if (IS_ERR(svm))
|
|
|
|
return PTR_ERR(svm);
|
|
|
|
|
|
|
|
if (!svm)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we found svm for the PASID, there must be at least one device
|
|
|
|
* bond.
|
|
|
|
*/
|
|
|
|
if (WARN_ON(list_empty(&svm->devs)))
|
|
|
|
return -EINVAL;
|
2021-06-10 10:01:00 +08:00
|
|
|
sdev = svm_lookup_device_by_dev(svm, dev);
|
2020-07-24 09:49:22 +08:00
|
|
|
|
|
|
|
out:
|
|
|
|
*rsvm = svm;
|
|
|
|
*rsdev = sdev;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
static int intel_svm_alloc_pasid(struct device *dev, struct mm_struct *mm,
|
|
|
|
unsigned int flags)
|
2015-09-09 18:40:47 +08:00
|
|
|
{
|
2021-06-10 10:00:59 +08:00
|
|
|
ioasid_t max_pasid = dev_is_pci(dev) ?
|
|
|
|
pci_max_pasids(to_pci_dev(dev)) : intel_pasid_max_id;
|
2015-09-09 18:40:47 +08:00
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
return iommu_sva_alloc_pasid(mm, PASID_MIN, max_pasid - 1);
|
|
|
|
}
|
2015-09-09 18:40:47 +08:00
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
static void intel_svm_free_pasid(struct mm_struct *mm)
|
|
|
|
{
|
|
|
|
iommu_sva_free_pasid(mm);
|
|
|
|
}
|
2020-01-02 08:18:05 +08:00
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
static struct iommu_sva *intel_svm_bind_mm(struct intel_iommu *iommu,
|
|
|
|
struct device *dev,
|
|
|
|
struct mm_struct *mm,
|
|
|
|
unsigned int flags)
|
|
|
|
{
|
2022-03-01 10:01:52 +08:00
|
|
|
struct device_domain_info *info = dev_iommu_priv_get(dev);
|
2021-06-10 10:00:59 +08:00
|
|
|
unsigned long iflags, sflags;
|
|
|
|
struct intel_svm_dev *sdev;
|
|
|
|
struct intel_svm *svm;
|
|
|
|
int ret = 0;
|
2015-09-09 18:40:47 +08:00
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
svm = pasid_private_find(mm->pasid);
|
|
|
|
if (!svm) {
|
|
|
|
svm = kzalloc(sizeof(*svm), GFP_KERNEL);
|
|
|
|
if (!svm)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
2015-10-15 22:52:15 +08:00
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
svm->pasid = mm->pasid;
|
|
|
|
svm->mm = mm;
|
|
|
|
svm->flags = flags;
|
|
|
|
INIT_LIST_HEAD_RCU(&svm->devs);
|
2015-09-09 18:40:47 +08:00
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
if (!(flags & SVM_FLAG_SUPERVISOR_MODE)) {
|
|
|
|
svm->notifier.ops = &intel_mmuops;
|
|
|
|
ret = mmu_notifier_register(&svm->notifier, mm);
|
|
|
|
if (ret) {
|
|
|
|
kfree(svm);
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
2021-03-23 09:05:58 +08:00
|
|
|
}
|
2015-09-09 18:40:47 +08:00
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
ret = pasid_private_add(svm->pasid, svm);
|
|
|
|
if (ret) {
|
|
|
|
if (svm->notifier.ops)
|
|
|
|
mmu_notifier_unregister(&svm->notifier, mm);
|
|
|
|
kfree(svm);
|
|
|
|
return ERR_PTR(ret);
|
2015-09-09 18:40:47 +08:00
|
|
|
}
|
2021-06-10 10:00:59 +08:00
|
|
|
}
|
2021-03-23 09:05:58 +08:00
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
/* Find the matching device in svm list */
|
2021-06-10 10:01:00 +08:00
|
|
|
sdev = svm_lookup_device_by_dev(svm, dev);
|
|
|
|
if (sdev) {
|
2021-06-10 10:00:59 +08:00
|
|
|
sdev->users++;
|
|
|
|
goto success;
|
2015-09-09 18:40:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
|
|
|
|
if (!sdev) {
|
|
|
|
ret = -ENOMEM;
|
2021-06-10 10:00:59 +08:00
|
|
|
goto free_svm;
|
2015-09-09 18:40:47 +08:00
|
|
|
}
|
2021-06-10 10:00:59 +08:00
|
|
|
|
2015-09-09 18:40:47 +08:00
|
|
|
sdev->dev = dev;
|
2021-01-07 00:03:55 +08:00
|
|
|
sdev->iommu = iommu;
|
2019-03-25 09:30:29 +08:00
|
|
|
sdev->did = FLPT_DEFAULT_DID;
|
|
|
|
sdev->sid = PCI_DEVID(info->bus, info->devfn);
|
2021-06-10 10:00:59 +08:00
|
|
|
sdev->users = 1;
|
|
|
|
sdev->pasid = svm->pasid;
|
|
|
|
sdev->sva.dev = dev;
|
|
|
|
init_rcu_head(&sdev->rcu);
|
2019-03-25 09:30:29 +08:00
|
|
|
if (info->ats_enabled) {
|
|
|
|
sdev->dev_iotlb = 1;
|
|
|
|
sdev->qdep = info->ats_qdep;
|
|
|
|
if (sdev->qdep >= QI_DEV_EIOTLB_MAX_INVS)
|
|
|
|
sdev->qdep = 0;
|
|
|
|
}
|
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
/* Setup the pasid table: */
|
|
|
|
sflags = (flags & SVM_FLAG_SUPERVISOR_MODE) ?
|
|
|
|
PASID_FLAG_SUPERVISOR_MODE : 0;
|
|
|
|
sflags |= cpu_feature_enabled(X86_FEATURE_LA57) ? PASID_FLAG_FL5LP : 0;
|
|
|
|
spin_lock_irqsave(&iommu->lock, iflags);
|
|
|
|
ret = intel_pasid_setup_first_level(iommu, dev, mm->pgd, mm->pasid,
|
|
|
|
FLPT_DEFAULT_DID, sflags);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, iflags);
|
2021-06-10 10:00:58 +08:00
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
if (ret)
|
|
|
|
goto free_sdev;
|
2018-03-16 12:31:36 +08:00
|
|
|
|
2015-09-09 18:40:47 +08:00
|
|
|
list_add_rcu(&sdev->list, &svm->devs);
|
2020-05-16 14:20:54 +08:00
|
|
|
success:
|
2021-06-10 10:00:59 +08:00
|
|
|
return &sdev->sva;
|
|
|
|
|
|
|
|
free_sdev:
|
|
|
|
kfree(sdev);
|
|
|
|
free_svm:
|
|
|
|
if (list_empty(&svm->devs)) {
|
|
|
|
if (svm->notifier.ops)
|
|
|
|
mmu_notifier_unregister(&svm->notifier, mm);
|
|
|
|
pasid_private_remove(mm->pasid);
|
|
|
|
kfree(svm);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ERR_PTR(ret);
|
2015-09-09 18:40:47 +08:00
|
|
|
}
|
|
|
|
|
2020-05-16 14:20:54 +08:00
|
|
|
/* Caller must hold pasid_mutex */
|
2020-09-16 00:30:05 +08:00
|
|
|
static int intel_svm_unbind_mm(struct device *dev, u32 pasid)
|
2015-09-09 18:40:47 +08:00
|
|
|
{
|
|
|
|
struct intel_svm_dev *sdev;
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
struct intel_svm *svm;
|
2021-06-10 10:00:59 +08:00
|
|
|
struct mm_struct *mm;
|
2015-09-09 18:40:47 +08:00
|
|
|
int ret = -EINVAL;
|
|
|
|
|
2020-07-24 09:49:21 +08:00
|
|
|
iommu = device_to_iommu(dev, NULL, NULL);
|
2018-07-14 15:47:01 +08:00
|
|
|
if (!iommu)
|
2015-09-09 18:40:47 +08:00
|
|
|
goto out;
|
|
|
|
|
2020-07-24 09:49:22 +08:00
|
|
|
ret = pasid_to_svm_sdev(dev, pasid, &svm, &sdev);
|
|
|
|
if (ret)
|
2020-01-02 08:18:08 +08:00
|
|
|
goto out;
|
2021-06-10 10:00:59 +08:00
|
|
|
mm = svm->mm;
|
2020-01-02 08:18:08 +08:00
|
|
|
|
2020-07-24 09:49:22 +08:00
|
|
|
if (sdev) {
|
2020-01-02 08:18:10 +08:00
|
|
|
sdev->users--;
|
|
|
|
if (!sdev->users) {
|
|
|
|
list_del_rcu(&sdev->list);
|
|
|
|
/* Flush the PASID cache and IOTLB for this device.
|
|
|
|
* Note that we do depend on the hardware *not* using
|
|
|
|
* the PASID any more. Just as we depend on other
|
|
|
|
* devices never using PASIDs that they have no right
|
|
|
|
* to use. We have a *shared* PASID table, because it's
|
|
|
|
* large and has to be physically contiguous. So it's
|
|
|
|
* hard to be as defensive as we might like. */
|
2020-05-16 14:20:57 +08:00
|
|
|
intel_pasid_tear_down_entry(iommu, dev,
|
|
|
|
svm->pasid, false);
|
2020-05-16 14:20:58 +08:00
|
|
|
intel_svm_drain_prq(dev, svm->pasid);
|
2020-01-02 08:18:10 +08:00
|
|
|
kfree_rcu(sdev, rcu);
|
|
|
|
|
|
|
|
if (list_empty(&svm->devs)) {
|
2021-10-14 13:38:37 +08:00
|
|
|
if (svm->notifier.ops)
|
2021-06-10 10:00:59 +08:00
|
|
|
mmu_notifier_unregister(&svm->notifier, mm);
|
2021-06-10 10:00:58 +08:00
|
|
|
pasid_private_remove(svm->pasid);
|
2020-01-02 08:18:10 +08:00
|
|
|
/* We mandate that no page faults may be outstanding
|
|
|
|
* for the PASID when intel_svm_unbind_mm() is called.
|
|
|
|
* If that is not obeyed, subtle errors will happen.
|
|
|
|
* Let's make them less subtle... */
|
|
|
|
memset(svm, 0x6b, sizeof(*svm));
|
|
|
|
kfree(svm);
|
2015-09-09 18:40:47 +08:00
|
|
|
}
|
|
|
|
}
|
2021-08-17 20:43:20 +08:00
|
|
|
/* Drop a PASID reference and free it if no reference. */
|
|
|
|
intel_svm_free_pasid(mm);
|
2015-09-09 18:40:47 +08:00
|
|
|
}
|
2020-07-24 09:49:22 +08:00
|
|
|
out:
|
2015-09-09 18:40:47 +08:00
|
|
|
return ret;
|
|
|
|
}
|
2017-05-11 02:39:03 +08:00
|
|
|
|
2015-10-08 06:35:18 +08:00
|
|
|
/* Page request queue descriptor */
|
|
|
|
struct page_req_dsc {
|
2019-01-11 13:04:57 +08:00
|
|
|
union {
|
|
|
|
struct {
|
|
|
|
u64 type:8;
|
|
|
|
u64 pasid_present:1;
|
|
|
|
u64 priv_data_present:1;
|
|
|
|
u64 rsvd:6;
|
|
|
|
u64 rid:16;
|
|
|
|
u64 pasid:20;
|
|
|
|
u64 exe_req:1;
|
|
|
|
u64 pm_req:1;
|
|
|
|
u64 rsvd2:10;
|
|
|
|
};
|
|
|
|
u64 qw_0;
|
|
|
|
};
|
|
|
|
union {
|
|
|
|
struct {
|
|
|
|
u64 rd_req:1;
|
|
|
|
u64 wr_req:1;
|
|
|
|
u64 lpig:1;
|
|
|
|
u64 prg_index:9;
|
|
|
|
u64 addr:52;
|
|
|
|
};
|
|
|
|
u64 qw_1;
|
|
|
|
};
|
|
|
|
u64 priv_data[2];
|
2015-10-08 06:35:18 +08:00
|
|
|
};
|
|
|
|
|
2017-08-09 04:29:27 +08:00
|
|
|
static bool is_canonical_address(u64 addr)
|
|
|
|
{
|
|
|
|
int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
|
|
|
|
long saddr = (long) addr;
|
|
|
|
|
|
|
|
return (((saddr << shift) >> shift) == saddr);
|
|
|
|
}
|
|
|
|
|
2020-05-16 14:20:58 +08:00
|
|
|
/**
|
|
|
|
* intel_svm_drain_prq - Drain page requests and responses for a pasid
|
|
|
|
* @dev: target device
|
|
|
|
* @pasid: pasid for draining
|
|
|
|
*
|
|
|
|
* Drain all pending page requests and responses related to @pasid in both
|
|
|
|
* software and hardware. This is supposed to be called after the device
|
|
|
|
* driver has stopped DMA, the pasid entry has been cleared, and both IOTLB
|
|
|
|
* and DevTLB have been invalidated.
|
|
|
|
*
|
|
|
|
* It waits until all pending page requests for @pasid in the page fault
|
|
|
|
* queue are completed by the prq handling thread. Then follow the steps
|
|
|
|
* described in VT-d spec CH7.10 to drain all page requests and page
|
|
|
|
* responses pending in the hardware.
|
|
|
|
*/
|
2020-09-16 00:30:05 +08:00
|
|
|
static void intel_svm_drain_prq(struct device *dev, u32 pasid)
|
2020-05-16 14:20:58 +08:00
|
|
|
{
|
|
|
|
struct device_domain_info *info;
|
|
|
|
struct dmar_domain *domain;
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
struct qi_desc desc[3];
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
int head, tail;
|
|
|
|
u16 sid, did;
|
|
|
|
int qdep;
|
|
|
|
|
2022-03-01 10:01:52 +08:00
|
|
|
info = dev_iommu_priv_get(dev);
|
2020-05-16 14:20:58 +08:00
|
|
|
if (WARN_ON(!info || !dev_is_pci(dev)))
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!info->pri_enabled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
iommu = info->iommu;
|
|
|
|
domain = info->domain;
|
|
|
|
pdev = to_pci_dev(dev);
|
|
|
|
sid = PCI_DEVID(info->bus, info->devfn);
|
|
|
|
did = domain->iommu_did[iommu->seq_id];
|
|
|
|
qdep = pci_ats_queue_depth(pdev);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check and wait until all pending page requests in the queue are
|
|
|
|
* handled by the prq handling thread.
|
|
|
|
*/
|
|
|
|
prq_retry:
|
|
|
|
reinit_completion(&iommu->prq_complete);
|
|
|
|
tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
|
|
|
|
head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
|
|
|
|
while (head != tail) {
|
|
|
|
struct page_req_dsc *req;
|
|
|
|
|
|
|
|
req = &iommu->prq[head / sizeof(*req)];
|
|
|
|
if (!req->pasid_present || req->pasid != pasid) {
|
|
|
|
head = (head + sizeof(*req)) & PRQ_RING_MASK;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
wait_for_completion(&iommu->prq_complete);
|
|
|
|
goto prq_retry;
|
|
|
|
}
|
|
|
|
|
2021-08-28 15:06:22 +08:00
|
|
|
/*
|
|
|
|
* A work in IO page fault workqueue may try to lock pasid_mutex now.
|
|
|
|
* Holding pasid_mutex while waiting in iopf_queue_flush_dev() for
|
|
|
|
* all works in the workqueue to finish may cause deadlock.
|
|
|
|
*
|
|
|
|
* It's unnecessary to hold pasid_mutex in iopf_queue_flush_dev().
|
|
|
|
* Unlock it to allow the works to be handled while waiting for
|
|
|
|
* them to finish.
|
|
|
|
*/
|
|
|
|
lockdep_assert_held(&pasid_mutex);
|
|
|
|
mutex_unlock(&pasid_mutex);
|
2021-06-10 10:01:03 +08:00
|
|
|
iopf_queue_flush_dev(dev);
|
2021-08-28 15:06:22 +08:00
|
|
|
mutex_lock(&pasid_mutex);
|
2021-06-10 10:01:03 +08:00
|
|
|
|
2020-05-16 14:20:58 +08:00
|
|
|
/*
|
|
|
|
* Perform steps described in VT-d spec CH7.10 to drain page
|
|
|
|
* requests and responses in hardware.
|
|
|
|
*/
|
|
|
|
memset(desc, 0, sizeof(desc));
|
|
|
|
desc[0].qw0 = QI_IWD_STATUS_DATA(QI_DONE) |
|
|
|
|
QI_IWD_FENCE |
|
|
|
|
QI_IWD_TYPE;
|
|
|
|
desc[1].qw0 = QI_EIOTLB_PASID(pasid) |
|
|
|
|
QI_EIOTLB_DID(did) |
|
|
|
|
QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
|
|
|
|
QI_EIOTLB_TYPE;
|
|
|
|
desc[2].qw0 = QI_DEV_EIOTLB_PASID(pasid) |
|
|
|
|
QI_DEV_EIOTLB_SID(sid) |
|
|
|
|
QI_DEV_EIOTLB_QDEP(qdep) |
|
|
|
|
QI_DEIOTLB_TYPE |
|
|
|
|
QI_DEV_IOTLB_PFSID(info->pfsid);
|
|
|
|
qi_retry:
|
|
|
|
reinit_completion(&iommu->prq_complete);
|
|
|
|
qi_submit_sync(iommu, desc, 3, QI_OPT_WAIT_DRAIN);
|
|
|
|
if (readl(iommu->reg + DMAR_PRS_REG) & DMA_PRS_PRO) {
|
|
|
|
wait_for_completion(&iommu->prq_complete);
|
|
|
|
goto qi_retry;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-07-24 09:49:23 +08:00
|
|
|
static int prq_to_iommu_prot(struct page_req_dsc *req)
|
|
|
|
{
|
|
|
|
int prot = 0;
|
|
|
|
|
|
|
|
if (req->rd_req)
|
|
|
|
prot |= IOMMU_FAULT_PERM_READ;
|
|
|
|
if (req->wr_req)
|
|
|
|
prot |= IOMMU_FAULT_PERM_WRITE;
|
|
|
|
if (req->exe_req)
|
|
|
|
prot |= IOMMU_FAULT_PERM_EXEC;
|
|
|
|
if (req->pm_req)
|
|
|
|
prot |= IOMMU_FAULT_PERM_PRIV;
|
|
|
|
|
|
|
|
return prot;
|
|
|
|
}
|
|
|
|
|
2021-06-10 10:01:08 +08:00
|
|
|
static int intel_svm_prq_report(struct intel_iommu *iommu, struct device *dev,
|
|
|
|
struct page_req_dsc *desc)
|
2020-07-24 09:49:23 +08:00
|
|
|
{
|
|
|
|
struct iommu_fault_event event;
|
|
|
|
|
|
|
|
if (!dev || !dev_is_pci(dev))
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
/* Fill in event data for device specific processing */
|
|
|
|
memset(&event, 0, sizeof(struct iommu_fault_event));
|
|
|
|
event.fault.type = IOMMU_FAULT_PAGE_REQ;
|
2021-03-20 10:54:11 +08:00
|
|
|
event.fault.prm.addr = (u64)desc->addr << VTD_PAGE_SHIFT;
|
2020-07-24 09:49:23 +08:00
|
|
|
event.fault.prm.pasid = desc->pasid;
|
|
|
|
event.fault.prm.grpid = desc->prg_index;
|
|
|
|
event.fault.prm.perm = prq_to_iommu_prot(desc);
|
|
|
|
|
|
|
|
if (desc->lpig)
|
|
|
|
event.fault.prm.flags |= IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE;
|
|
|
|
if (desc->pasid_present) {
|
|
|
|
event.fault.prm.flags |= IOMMU_FAULT_PAGE_REQUEST_PASID_VALID;
|
|
|
|
event.fault.prm.flags |= IOMMU_FAULT_PAGE_RESPONSE_NEEDS_PASID;
|
|
|
|
}
|
|
|
|
if (desc->priv_data_present) {
|
|
|
|
/*
|
|
|
|
* Set last page in group bit if private data is present,
|
|
|
|
* page response is required as it does for LPIG.
|
|
|
|
* iommu_report_device_fault() doesn't understand this vendor
|
|
|
|
* specific requirement thus we set last_page as a workaround.
|
|
|
|
*/
|
|
|
|
event.fault.prm.flags |= IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE;
|
|
|
|
event.fault.prm.flags |= IOMMU_FAULT_PAGE_REQUEST_PRIV_DATA;
|
2021-06-10 10:01:09 +08:00
|
|
|
event.fault.prm.private_data[0] = desc->priv_data[0];
|
|
|
|
event.fault.prm.private_data[1] = desc->priv_data[1];
|
2021-06-10 10:01:08 +08:00
|
|
|
} else if (dmar_latency_enabled(iommu, DMAR_LATENCY_PRQ)) {
|
|
|
|
/*
|
|
|
|
* If the private data fields are not used by hardware, use it
|
|
|
|
* to monitor the prq handle latency.
|
|
|
|
*/
|
|
|
|
event.fault.prm.private_data[0] = ktime_to_ns(ktime_get());
|
2020-07-24 09:49:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return iommu_report_device_fault(dev, &event);
|
|
|
|
}
|
|
|
|
|
2021-06-10 10:01:01 +08:00
|
|
|
static void handle_bad_prq_event(struct intel_iommu *iommu,
|
|
|
|
struct page_req_dsc *req, int result)
|
|
|
|
{
|
|
|
|
struct qi_desc desc;
|
|
|
|
|
|
|
|
pr_err("%s: Invalid page request: %08llx %08llx\n",
|
|
|
|
iommu->name, ((unsigned long long *)req)[0],
|
|
|
|
((unsigned long long *)req)[1]);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Per VT-d spec. v3.0 ch7.7, system software must
|
|
|
|
* respond with page group response if private data
|
|
|
|
* is present (PDP) or last page in group (LPIG) bit
|
|
|
|
* is set. This is an additional VT-d feature beyond
|
|
|
|
* PCI ATS spec.
|
|
|
|
*/
|
|
|
|
if (!req->lpig && !req->priv_data_present)
|
|
|
|
return;
|
|
|
|
|
|
|
|
desc.qw0 = QI_PGRP_PASID(req->pasid) |
|
|
|
|
QI_PGRP_DID(req->rid) |
|
|
|
|
QI_PGRP_PASID_P(req->pasid_present) |
|
|
|
|
QI_PGRP_PDP(req->priv_data_present) |
|
|
|
|
QI_PGRP_RESP_CODE(result) |
|
|
|
|
QI_PGRP_RESP_TYPE;
|
|
|
|
desc.qw1 = QI_PGRP_IDX(req->prg_index) |
|
|
|
|
QI_PGRP_LPIG(req->lpig);
|
|
|
|
|
2021-06-10 10:01:09 +08:00
|
|
|
if (req->priv_data_present) {
|
|
|
|
desc.qw2 = req->priv_data[0];
|
|
|
|
desc.qw3 = req->priv_data[1];
|
|
|
|
} else {
|
|
|
|
desc.qw2 = 0;
|
|
|
|
desc.qw3 = 0;
|
|
|
|
}
|
|
|
|
|
2021-06-10 10:01:01 +08:00
|
|
|
qi_submit_sync(iommu, &desc, 1, 0);
|
|
|
|
}
|
|
|
|
|
2015-10-08 06:35:18 +08:00
|
|
|
static irqreturn_t prq_event_thread(int irq, void *d)
|
|
|
|
{
|
2020-07-24 09:49:23 +08:00
|
|
|
struct intel_svm_dev *sdev = NULL;
|
2015-10-08 06:35:18 +08:00
|
|
|
struct intel_iommu *iommu = d;
|
|
|
|
struct intel_svm *svm = NULL;
|
2021-06-10 10:01:01 +08:00
|
|
|
struct page_req_dsc *req;
|
|
|
|
int head, tail, handled;
|
|
|
|
u64 address;
|
2015-10-08 06:35:18 +08:00
|
|
|
|
2021-06-10 10:01:01 +08:00
|
|
|
/*
|
|
|
|
* Clear PPR bit before reading head/tail registers, to ensure that
|
|
|
|
* we get a new interrupt if needed.
|
|
|
|
*/
|
2016-02-15 20:42:38 +08:00
|
|
|
writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
|
|
|
|
|
2015-10-08 06:35:18 +08:00
|
|
|
tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
|
|
|
|
head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
|
2021-06-10 10:01:01 +08:00
|
|
|
handled = (head != tail);
|
2015-10-08 06:35:18 +08:00
|
|
|
while (head != tail) {
|
|
|
|
req = &iommu->prq[head / sizeof(*req)];
|
2015-10-17 00:22:31 +08:00
|
|
|
address = (u64)req->addr << VTD_PAGE_SHIFT;
|
2021-06-10 10:01:01 +08:00
|
|
|
|
|
|
|
if (unlikely(!req->pasid_present)) {
|
|
|
|
pr_err("IOMMU: %s: Page request without PASID\n",
|
|
|
|
iommu->name);
|
|
|
|
bad_req:
|
|
|
|
svm = NULL;
|
|
|
|
sdev = NULL;
|
|
|
|
handle_bad_prq_event(iommu, req, QI_RESP_INVALID);
|
|
|
|
goto prq_advance;
|
2015-10-08 06:35:18 +08:00
|
|
|
}
|
2021-06-10 10:01:01 +08:00
|
|
|
|
|
|
|
if (unlikely(!is_canonical_address(address))) {
|
|
|
|
pr_err("IOMMU: %s: Address is not canonical\n",
|
|
|
|
iommu->name);
|
|
|
|
goto bad_req;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unlikely(req->pm_req && (req->rd_req | req->wr_req))) {
|
|
|
|
pr_err("IOMMU: %s: Page request in Privilege Mode\n",
|
|
|
|
iommu->name);
|
|
|
|
goto bad_req;
|
2021-03-02 18:13:59 +08:00
|
|
|
}
|
2021-06-10 10:01:01 +08:00
|
|
|
|
|
|
|
if (unlikely(req->exe_req && req->rd_req)) {
|
|
|
|
pr_err("IOMMU: %s: Execution request not supported\n",
|
|
|
|
iommu->name);
|
|
|
|
goto bad_req;
|
2021-03-02 18:13:59 +08:00
|
|
|
}
|
2021-06-10 10:01:01 +08:00
|
|
|
|
2015-10-08 06:35:18 +08:00
|
|
|
if (!svm || svm->pasid != req->pasid) {
|
2021-06-10 10:01:01 +08:00
|
|
|
/*
|
|
|
|
* It can't go away, because the driver is not permitted
|
2015-10-08 06:35:18 +08:00
|
|
|
* to unbind the mm while any page faults are outstanding.
|
2021-06-10 10:01:01 +08:00
|
|
|
*/
|
|
|
|
svm = pasid_private_find(req->pasid);
|
|
|
|
if (IS_ERR_OR_NULL(svm) || (svm->flags & SVM_FLAG_SUPERVISOR_MODE))
|
|
|
|
goto bad_req;
|
2015-10-08 06:35:18 +08:00
|
|
|
}
|
|
|
|
|
2021-06-10 10:01:01 +08:00
|
|
|
if (!sdev || sdev->sid != req->rid) {
|
2021-06-10 10:01:00 +08:00
|
|
|
sdev = svm_lookup_device_by_sid(svm, req->rid);
|
2021-06-10 10:01:01 +08:00
|
|
|
if (!sdev)
|
|
|
|
goto bad_req;
|
|
|
|
}
|
2017-08-09 04:29:27 +08:00
|
|
|
|
2021-06-10 10:01:04 +08:00
|
|
|
sdev->prq_seq_number++;
|
|
|
|
|
2020-07-24 09:49:23 +08:00
|
|
|
/*
|
|
|
|
* If prq is to be handled outside iommu driver via receiver of
|
|
|
|
* the fault notifiers, we skip the page response here.
|
|
|
|
*/
|
2021-06-10 10:01:08 +08:00
|
|
|
if (intel_svm_prq_report(iommu, sdev->dev, req))
|
2021-06-10 10:01:03 +08:00
|
|
|
handle_bad_prq_event(iommu, req, QI_RESP_INVALID);
|
2021-06-10 10:01:04 +08:00
|
|
|
|
|
|
|
trace_prq_report(iommu, sdev->dev, req->qw_0, req->qw_1,
|
|
|
|
req->priv_data[0], req->priv_data[1],
|
|
|
|
sdev->prq_seq_number);
|
2020-07-24 09:49:23 +08:00
|
|
|
prq_advance:
|
2015-10-08 06:35:18 +08:00
|
|
|
head = (head + sizeof(*req)) & PRQ_RING_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
|
|
|
|
|
2020-05-16 14:20:58 +08:00
|
|
|
/*
|
|
|
|
* Clear the page request overflow bit and wake up all threads that
|
|
|
|
* are waiting for the completion of this handling.
|
|
|
|
*/
|
2021-01-26 16:07:29 +08:00
|
|
|
if (readl(iommu->reg + DMAR_PRS_REG) & DMA_PRS_PRO) {
|
|
|
|
pr_info_ratelimited("IOMMU: %s: PRQ overflow detected\n",
|
|
|
|
iommu->name);
|
|
|
|
head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
|
|
|
|
tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
|
|
|
|
if (head == tail) {
|
2021-06-10 10:01:03 +08:00
|
|
|
iopf_queue_discard_partial(iommu->iopf_queue);
|
2021-01-26 16:07:29 +08:00
|
|
|
writel(DMA_PRS_PRO, iommu->reg + DMAR_PRS_REG);
|
|
|
|
pr_info_ratelimited("IOMMU: %s: PRQ overflow cleared",
|
|
|
|
iommu->name);
|
|
|
|
}
|
|
|
|
}
|
2020-05-16 14:20:58 +08:00
|
|
|
|
|
|
|
if (!completion_done(&iommu->prq_complete))
|
|
|
|
complete(&iommu->prq_complete);
|
|
|
|
|
2015-10-08 06:35:18 +08:00
|
|
|
return IRQ_RETVAL(handled);
|
|
|
|
}
|
2020-05-16 14:20:54 +08:00
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
struct iommu_sva *intel_svm_bind(struct device *dev, struct mm_struct *mm, void *drvdata)
|
2020-05-16 14:20:54 +08:00
|
|
|
{
|
2021-06-10 10:00:59 +08:00
|
|
|
struct intel_iommu *iommu = device_to_iommu(dev, NULL, NULL);
|
2020-09-16 00:30:06 +08:00
|
|
|
unsigned int flags = 0;
|
2021-06-10 10:00:59 +08:00
|
|
|
struct iommu_sva *sva;
|
2020-05-16 14:20:54 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (drvdata)
|
2020-09-16 00:30:06 +08:00
|
|
|
flags = *(unsigned int *)drvdata;
|
2021-06-10 10:00:59 +08:00
|
|
|
|
|
|
|
if (flags & SVM_FLAG_SUPERVISOR_MODE) {
|
|
|
|
if (!ecap_srs(iommu->ecap)) {
|
|
|
|
dev_err(dev, "%s: Supervisor PASID not supported\n",
|
|
|
|
iommu->name);
|
|
|
|
return ERR_PTR(-EOPNOTSUPP);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mm) {
|
|
|
|
dev_err(dev, "%s: Supervisor PASID with user provided mm\n",
|
|
|
|
iommu->name);
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
mm = &init_mm;
|
|
|
|
}
|
|
|
|
|
2020-05-16 14:20:54 +08:00
|
|
|
mutex_lock(&pasid_mutex);
|
2021-06-10 10:00:59 +08:00
|
|
|
ret = intel_svm_alloc_pasid(dev, mm, flags);
|
|
|
|
if (ret) {
|
|
|
|
mutex_unlock(&pasid_mutex);
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
2020-05-16 14:20:54 +08:00
|
|
|
|
2021-06-10 10:00:59 +08:00
|
|
|
sva = intel_svm_bind_mm(iommu, dev, mm, flags);
|
|
|
|
if (IS_ERR_OR_NULL(sva))
|
|
|
|
intel_svm_free_pasid(mm);
|
2020-05-16 14:20:54 +08:00
|
|
|
mutex_unlock(&pasid_mutex);
|
|
|
|
|
|
|
|
return sva;
|
|
|
|
}
|
|
|
|
|
|
|
|
void intel_svm_unbind(struct iommu_sva *sva)
|
|
|
|
{
|
2021-06-10 10:00:59 +08:00
|
|
|
struct intel_svm_dev *sdev = to_intel_svm_dev(sva);
|
2020-05-16 14:20:54 +08:00
|
|
|
|
|
|
|
mutex_lock(&pasid_mutex);
|
|
|
|
intel_svm_unbind_mm(sdev->dev, sdev->pasid);
|
|
|
|
mutex_unlock(&pasid_mutex);
|
|
|
|
}
|
|
|
|
|
2020-09-16 00:30:05 +08:00
|
|
|
u32 intel_svm_get_pasid(struct iommu_sva *sva)
|
2020-05-16 14:20:54 +08:00
|
|
|
{
|
|
|
|
struct intel_svm_dev *sdev;
|
2020-09-16 00:30:05 +08:00
|
|
|
u32 pasid;
|
2020-05-16 14:20:54 +08:00
|
|
|
|
|
|
|
mutex_lock(&pasid_mutex);
|
|
|
|
sdev = to_intel_svm_dev(sva);
|
|
|
|
pasid = sdev->pasid;
|
|
|
|
mutex_unlock(&pasid_mutex);
|
|
|
|
|
|
|
|
return pasid;
|
|
|
|
}
|
2020-07-24 09:49:24 +08:00
|
|
|
|
|
|
|
int intel_svm_page_response(struct device *dev,
|
|
|
|
struct iommu_fault_event *evt,
|
|
|
|
struct iommu_page_response *msg)
|
|
|
|
{
|
|
|
|
struct iommu_fault_page_request *prm;
|
|
|
|
struct intel_svm_dev *sdev = NULL;
|
|
|
|
struct intel_svm *svm = NULL;
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
bool private_present;
|
|
|
|
bool pasid_present;
|
|
|
|
bool last_page;
|
|
|
|
u8 bus, devfn;
|
|
|
|
int ret = 0;
|
|
|
|
u16 sid;
|
|
|
|
|
|
|
|
if (!dev || !dev_is_pci(dev))
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
iommu = device_to_iommu(dev, &bus, &devfn);
|
|
|
|
if (!iommu)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
if (!msg || !evt)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mutex_lock(&pasid_mutex);
|
|
|
|
|
|
|
|
prm = &evt->fault.prm;
|
|
|
|
sid = PCI_DEVID(bus, devfn);
|
|
|
|
pasid_present = prm->flags & IOMMU_FAULT_PAGE_REQUEST_PASID_VALID;
|
|
|
|
private_present = prm->flags & IOMMU_FAULT_PAGE_REQUEST_PRIV_DATA;
|
|
|
|
last_page = prm->flags & IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE;
|
|
|
|
|
|
|
|
if (!pasid_present) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (prm->pasid == 0 || prm->pasid >= PASID_MAX) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = pasid_to_svm_sdev(dev, prm->pasid, &svm, &sdev);
|
|
|
|
if (ret || !sdev) {
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Per VT-d spec. v3.0 ch7.7, system software must respond
|
|
|
|
* with page group response if private data is present (PDP)
|
|
|
|
* or last page in group (LPIG) bit is set. This is an
|
|
|
|
* additional VT-d requirement beyond PCI ATS spec.
|
|
|
|
*/
|
|
|
|
if (last_page || private_present) {
|
|
|
|
struct qi_desc desc;
|
|
|
|
|
|
|
|
desc.qw0 = QI_PGRP_PASID(prm->pasid) | QI_PGRP_DID(sid) |
|
|
|
|
QI_PGRP_PASID_P(pasid_present) |
|
|
|
|
QI_PGRP_PDP(private_present) |
|
|
|
|
QI_PGRP_RESP_CODE(msg->code) |
|
|
|
|
QI_PGRP_RESP_TYPE;
|
|
|
|
desc.qw1 = QI_PGRP_IDX(prm->grpid) | QI_PGRP_LPIG(last_page);
|
|
|
|
desc.qw2 = 0;
|
|
|
|
desc.qw3 = 0;
|
2021-06-10 10:01:09 +08:00
|
|
|
|
|
|
|
if (private_present) {
|
|
|
|
desc.qw2 = prm->private_data[0];
|
|
|
|
desc.qw3 = prm->private_data[1];
|
|
|
|
} else if (prm->private_data[0]) {
|
2021-06-10 10:01:08 +08:00
|
|
|
dmar_latency_update(iommu, DMAR_LATENCY_PRQ,
|
|
|
|
ktime_to_ns(ktime_get()) - prm->private_data[0]);
|
2021-06-10 10:01:09 +08:00
|
|
|
}
|
2020-07-24 09:49:24 +08:00
|
|
|
|
|
|
|
qi_submit_sync(iommu, &desc, 1, 0);
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
mutex_unlock(&pasid_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|