2011-10-04 18:19:01 +08:00
|
|
|
config DRM_EXYNOS
|
|
|
|
|
tristate "DRM Support for Samsung SoC EXYNOS Series"
|
2013-08-28 13:17:53 +08:00
|
|
|
depends on OF && DRM && (PLAT_SAMSUNG || ARCH_MULTIPLATFORM)
|
2011-10-04 18:19:01 +08:00
|
|
|
select DRM_KMS_HELPER
|
2013-10-08 23:44:47 +08:00
|
|
|
select DRM_KMS_FB_HELPER
|
2011-10-04 18:19:01 +08:00
|
|
|
select FB_CFB_FILLRECT
|
|
|
|
|
select FB_CFB_COPYAREA
|
|
|
|
|
select FB_CFB_IMAGEBLIT
|
2013-08-30 17:10:51 +08:00
|
|
|
select VIDEOMODE_HELPERS
|
2011-10-04 18:19:01 +08:00
|
|
|
help
|
|
|
|
|
Choose this option if you have a Samsung SoC EXYNOS chipset.
|
|
|
|
|
If M is selected the module will be called exynosdrm.
|
|
|
|
|
|
2012-10-20 22:53:42 +08:00
|
|
|
config DRM_EXYNOS_IOMMU
|
2015-01-20 22:31:14 +08:00
|
|
|
bool
|
2012-10-20 22:53:42 +08:00
|
|
|
depends on DRM_EXYNOS && EXYNOS_IOMMU && ARM_DMA_USE_IOMMU
|
2015-01-20 22:31:14 +08:00
|
|
|
default y
|
2012-10-20 22:53:42 +08:00
|
|
|
|
2011-10-04 18:19:01 +08:00
|
|
|
config DRM_EXYNOS_FIMD
|
2012-03-16 17:47:08 +08:00
|
|
|
bool "Exynos DRM FIMD"
|
2014-05-23 18:58:36 +08:00
|
|
|
depends on DRM_EXYNOS && !FB_S3C
|
2013-03-09 08:10:20 +08:00
|
|
|
select FB_MODE_HELPERS
|
2014-07-17 17:01:21 +08:00
|
|
|
select MFD_SYSCON
|
2011-10-04 18:19:01 +08:00
|
|
|
help
|
|
|
|
|
Choose this option if you want to use Exynos FIMD for DRM.
|
drm/exynos: added hdmi display support
This patch is hdmi display support for exynos drm driver.
There is already v4l2 based exynos hdmi driver in drivers/media/video/s5p-tv
and some low level code is already in s5p-tv and even headers for register
define are almost same. but in this patch, we decide not to consider separated
common code with s5p-tv.
Exynos HDMI is composed of 5 blocks, mixer, vp, hdmi, hdmiphy and ddc.
1. mixer. The piece of hardware responsible for mixing and blending multiple
data inputs before passing it to an output device. The mixer is capable of
handling up to three image layers. One is the output of VP. Other two are
images in RGB format. The blending factor, and layers' priority are controlled
by mixer's registers. The output is passed to HDMI.
2. vp (video processor). It is used for processing of NV12/NV21 data. An image
stored in RAM is accessed by DMA. The output in YCbCr444 format is send to
mixer.
3. hdmi. The piece of HW responsible for generation of HDMI packets. It takes
pixel data from mixer and transforms it into data frames. The output is send
to HDMIPHY interface.
4. hdmiphy. Physical interface for HDMI. Its duties are sending HDMI packets to
HDMI connector. Basically, it contains a PLL that produces source clock for
mixer, vp and hdmi.
5. ddc (display data channel). It is dedicated i2c channel to exchange display
information as edid with display monitor.
With plane support, exynos hdmi driver fully supports two mixer layes and vp
layer. Also vp layer supports multi buffer plane pixel formats having non
contigus memory spaces.
In exynos drm driver, common drm_hdmi driver to interface with drm framework
has opertion pointers for mixer and hdmi. this drm_hdmi driver is registered as
sub driver of exynos_drm. hdmi has hdmiphy and ddc i2c clients and controls
them. mixer controls all overlay layers in both mixer and vp.
Vblank interrupts for hdmi are handled by mixer internally because drm
framework cannot support multiple irq id. And pipe number is used to check
which display device irq happens.
History
v2: this version
- drm plane feature support to handle overlay layers.
- multi buffer plane pixel format support for vp layer.
- vp layer support
RFCv1: original
- at https://lkml.org/lkml/2011/11/4/164
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2011-12-21 16:39:39 +08:00
|
|
|
|
2014-03-17 20:03:56 +08:00
|
|
|
config DRM_EXYNOS_DPI
|
|
|
|
|
bool "EXYNOS DRM parallel output support"
|
2014-05-23 18:59:28 +08:00
|
|
|
depends on DRM_EXYNOS_FIMD
|
2014-03-17 20:03:56 +08:00
|
|
|
select DRM_PANEL
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
This enables support for Exynos parallel output.
|
|
|
|
|
|
2014-04-04 00:19:56 +08:00
|
|
|
config DRM_EXYNOS_DSI
|
|
|
|
|
bool "EXYNOS DRM MIPI-DSI driver support"
|
2014-05-23 18:59:28 +08:00
|
|
|
depends on DRM_EXYNOS_FIMD
|
2014-04-04 00:19:56 +08:00
|
|
|
select DRM_MIPI_DSI
|
|
|
|
|
select DRM_PANEL
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
This enables support for Exynos MIPI-DSI device.
|
|
|
|
|
|
2014-01-31 05:19:22 +08:00
|
|
|
config DRM_EXYNOS_DP
|
|
|
|
|
bool "EXYNOS DRM DP driver support"
|
2014-05-23 18:59:28 +08:00
|
|
|
depends on DRM_EXYNOS_FIMD && ARCH_EXYNOS && (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS)
|
2014-01-31 05:19:22 +08:00
|
|
|
default DRM_EXYNOS
|
2014-08-01 01:42:14 +08:00
|
|
|
select DRM_PANEL
|
2014-01-31 05:19:22 +08:00
|
|
|
help
|
|
|
|
|
This enables support for DP device.
|
|
|
|
|
|
drm/exynos: added hdmi display support
This patch is hdmi display support for exynos drm driver.
There is already v4l2 based exynos hdmi driver in drivers/media/video/s5p-tv
and some low level code is already in s5p-tv and even headers for register
define are almost same. but in this patch, we decide not to consider separated
common code with s5p-tv.
Exynos HDMI is composed of 5 blocks, mixer, vp, hdmi, hdmiphy and ddc.
1. mixer. The piece of hardware responsible for mixing and blending multiple
data inputs before passing it to an output device. The mixer is capable of
handling up to three image layers. One is the output of VP. Other two are
images in RGB format. The blending factor, and layers' priority are controlled
by mixer's registers. The output is passed to HDMI.
2. vp (video processor). It is used for processing of NV12/NV21 data. An image
stored in RAM is accessed by DMA. The output in YCbCr444 format is send to
mixer.
3. hdmi. The piece of HW responsible for generation of HDMI packets. It takes
pixel data from mixer and transforms it into data frames. The output is send
to HDMIPHY interface.
4. hdmiphy. Physical interface for HDMI. Its duties are sending HDMI packets to
HDMI connector. Basically, it contains a PLL that produces source clock for
mixer, vp and hdmi.
5. ddc (display data channel). It is dedicated i2c channel to exchange display
information as edid with display monitor.
With plane support, exynos hdmi driver fully supports two mixer layes and vp
layer. Also vp layer supports multi buffer plane pixel formats having non
contigus memory spaces.
In exynos drm driver, common drm_hdmi driver to interface with drm framework
has opertion pointers for mixer and hdmi. this drm_hdmi driver is registered as
sub driver of exynos_drm. hdmi has hdmiphy and ddc i2c clients and controls
them. mixer controls all overlay layers in both mixer and vp.
Vblank interrupts for hdmi are handled by mixer internally because drm
framework cannot support multiple irq id. And pipe number is used to check
which display device irq happens.
History
v2: this version
- drm plane feature support to handle overlay layers.
- multi buffer plane pixel format support for vp layer.
- vp layer support
RFCv1: original
- at https://lkml.org/lkml/2011/11/4/164
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2011-12-21 16:39:39 +08:00
|
|
|
config DRM_EXYNOS_HDMI
|
2012-03-16 17:47:08 +08:00
|
|
|
bool "Exynos DRM HDMI"
|
2012-01-04 14:34:32 +08:00
|
|
|
depends on DRM_EXYNOS && !VIDEO_SAMSUNG_S5P_TV
|
drm/exynos: added hdmi display support
This patch is hdmi display support for exynos drm driver.
There is already v4l2 based exynos hdmi driver in drivers/media/video/s5p-tv
and some low level code is already in s5p-tv and even headers for register
define are almost same. but in this patch, we decide not to consider separated
common code with s5p-tv.
Exynos HDMI is composed of 5 blocks, mixer, vp, hdmi, hdmiphy and ddc.
1. mixer. The piece of hardware responsible for mixing and blending multiple
data inputs before passing it to an output device. The mixer is capable of
handling up to three image layers. One is the output of VP. Other two are
images in RGB format. The blending factor, and layers' priority are controlled
by mixer's registers. The output is passed to HDMI.
2. vp (video processor). It is used for processing of NV12/NV21 data. An image
stored in RAM is accessed by DMA. The output in YCbCr444 format is send to
mixer.
3. hdmi. The piece of HW responsible for generation of HDMI packets. It takes
pixel data from mixer and transforms it into data frames. The output is send
to HDMIPHY interface.
4. hdmiphy. Physical interface for HDMI. Its duties are sending HDMI packets to
HDMI connector. Basically, it contains a PLL that produces source clock for
mixer, vp and hdmi.
5. ddc (display data channel). It is dedicated i2c channel to exchange display
information as edid with display monitor.
With plane support, exynos hdmi driver fully supports two mixer layes and vp
layer. Also vp layer supports multi buffer plane pixel formats having non
contigus memory spaces.
In exynos drm driver, common drm_hdmi driver to interface with drm framework
has opertion pointers for mixer and hdmi. this drm_hdmi driver is registered as
sub driver of exynos_drm. hdmi has hdmiphy and ddc i2c clients and controls
them. mixer controls all overlay layers in both mixer and vp.
Vblank interrupts for hdmi are handled by mixer internally because drm
framework cannot support multiple irq id. And pipe number is used to check
which display device irq happens.
History
v2: this version
- drm plane feature support to handle overlay layers.
- multi buffer plane pixel format support for vp layer.
- vp layer support
RFCv1: original
- at https://lkml.org/lkml/2011/11/4/164
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2011-12-21 16:39:39 +08:00
|
|
|
help
|
|
|
|
|
Choose this option if you want to use Exynos HDMI for DRM.
|
2012-03-21 09:55:26 +08:00
|
|
|
|
|
|
|
|
config DRM_EXYNOS_VIDI
|
|
|
|
|
bool "Exynos DRM Virtual Display"
|
|
|
|
|
depends on DRM_EXYNOS
|
|
|
|
|
help
|
|
|
|
|
Choose this option if you want to use Exynos VIDI for DRM.
|
2012-05-17 19:06:32 +08:00
|
|
|
|
|
|
|
|
config DRM_EXYNOS_G2D
|
|
|
|
|
bool "Exynos DRM G2D"
|
2012-08-14 14:37:20 +08:00
|
|
|
depends on DRM_EXYNOS && !VIDEO_SAMSUNG_S5P_G2D
|
2012-05-17 19:06:32 +08:00
|
|
|
help
|
|
|
|
|
Choose this option if you want to use Exynos G2D for DRM.
|
drm/exynos: add ipp subsystem
This patch adds Image Post Processing(IPP) support for exynos drm driver.
IPP supports image scaler/rotator and input/output DMA operations
using IPP subsystem framework to control FIMC, Rotator and GSC hardware
and supports some user interfaces for user side.
And each IPP-based drivers support Memory to Memory operations
with various converting. And in case of FIMC hardware, it also supports
Writeback and Display output operations through local path.
Features:
- Memory to Memory operation support.
- Various pixel formats support.
- Image scaling support.
- Color Space Conversion support.
- Image crop operation support.
- Rotate operation support to 90, 180 or 270 degree.
- Flip operation support to vertical, horizontal or both.
- Writeback operation support to display blended image of FIMD fifo on screen
A summary to IPP Subsystem operations:
First of all, user should get property capabilities from IPP subsystem
and set these properties to hardware registers for desired operations.
The properties could be pixel format, position, rotation degree and
flip operation.
And next, user should set source and destination buffer data using
DRM_EXYNOS_IPP_QUEUE_BUF ioctl command with gem handles to source and
destinition buffers.
And next, user can control user-desired hardware with desired operations
such as play, stop, pause and resume controls.
And finally, user can aware of dma operation completion and also get
destination buffer that it contains user-desried result through dequeue
command.
IOCTL commands:
- DRM_EXYNOS_IPP_GET_PROPERTY
. get ipp driver capabilitis and id.
- DRM_EXYNOS_IPP_SET_PROPERTY
. set format, position, rotation, flip to source and destination buffers
- DRM_EXYNOS_IPP_QUEUE_BUF
. enqueue/dequeue buffer and make event list.
- DRM_EXYNOS_IPP_CMD_CTRL
. play/stop/pause/resume control.
Event:
- DRM_EXYNOS_IPP_EVENT
. a event to notify dma operation completion to user side.
Basic control flow:
Open -> Get properties -> User choose desired IPP sub driver(FIMC, Rotator
or GSCALER) -> Set Property -> Create gem handle -> Enqueue to source and
destination buffers -> Command control(Play) -> Event is notified to User
-> User gets destinition buffer complated -> (Enqueue to source and
destination buffers -> Event is notified to User) * N -> Queue/Dequeue to
source and destination buffers -> Command control(Stop) -> Free gem handle
-> Close
Changelog v1 ~ v5:
- added comments, code fixups and cleanups.
Signed-off-by: Eunchul Kim <chulspro.kim@samsung.com>
Signed-off-by: Jinyoung Jeon <jy0.jeon@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2012-12-14 17:10:31 +08:00
|
|
|
|
|
|
|
|
config DRM_EXYNOS_IPP
|
|
|
|
|
bool "Exynos DRM IPP"
|
2014-01-16 14:27:57 +08:00
|
|
|
depends on DRM_EXYNOS
|
drm/exynos: add ipp subsystem
This patch adds Image Post Processing(IPP) support for exynos drm driver.
IPP supports image scaler/rotator and input/output DMA operations
using IPP subsystem framework to control FIMC, Rotator and GSC hardware
and supports some user interfaces for user side.
And each IPP-based drivers support Memory to Memory operations
with various converting. And in case of FIMC hardware, it also supports
Writeback and Display output operations through local path.
Features:
- Memory to Memory operation support.
- Various pixel formats support.
- Image scaling support.
- Color Space Conversion support.
- Image crop operation support.
- Rotate operation support to 90, 180 or 270 degree.
- Flip operation support to vertical, horizontal or both.
- Writeback operation support to display blended image of FIMD fifo on screen
A summary to IPP Subsystem operations:
First of all, user should get property capabilities from IPP subsystem
and set these properties to hardware registers for desired operations.
The properties could be pixel format, position, rotation degree and
flip operation.
And next, user should set source and destination buffer data using
DRM_EXYNOS_IPP_QUEUE_BUF ioctl command with gem handles to source and
destinition buffers.
And next, user can control user-desired hardware with desired operations
such as play, stop, pause and resume controls.
And finally, user can aware of dma operation completion and also get
destination buffer that it contains user-desried result through dequeue
command.
IOCTL commands:
- DRM_EXYNOS_IPP_GET_PROPERTY
. get ipp driver capabilitis and id.
- DRM_EXYNOS_IPP_SET_PROPERTY
. set format, position, rotation, flip to source and destination buffers
- DRM_EXYNOS_IPP_QUEUE_BUF
. enqueue/dequeue buffer and make event list.
- DRM_EXYNOS_IPP_CMD_CTRL
. play/stop/pause/resume control.
Event:
- DRM_EXYNOS_IPP_EVENT
. a event to notify dma operation completion to user side.
Basic control flow:
Open -> Get properties -> User choose desired IPP sub driver(FIMC, Rotator
or GSCALER) -> Set Property -> Create gem handle -> Enqueue to source and
destination buffers -> Command control(Play) -> Event is notified to User
-> User gets destinition buffer complated -> (Enqueue to source and
destination buffers -> Event is notified to User) * N -> Queue/Dequeue to
source and destination buffers -> Command control(Stop) -> Free gem handle
-> Close
Changelog v1 ~ v5:
- added comments, code fixups and cleanups.
Signed-off-by: Eunchul Kim <chulspro.kim@samsung.com>
Signed-off-by: Jinyoung Jeon <jy0.jeon@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2012-12-14 17:10:31 +08:00
|
|
|
help
|
|
|
|
|
Choose this option if you want to use IPP feature for DRM.
|
2012-12-14 16:58:55 +08:00
|
|
|
|
|
|
|
|
config DRM_EXYNOS_FIMC
|
|
|
|
|
bool "Exynos DRM FIMC"
|
2013-09-05 18:55:32 +08:00
|
|
|
depends on DRM_EXYNOS_IPP && MFD_SYSCON
|
2012-12-14 16:58:55 +08:00
|
|
|
help
|
|
|
|
|
Choose this option if you want to use Exynos FIMC for DRM.
|
2012-12-14 16:58:56 +08:00
|
|
|
|
|
|
|
|
config DRM_EXYNOS_ROTATOR
|
|
|
|
|
bool "Exynos DRM Rotator"
|
|
|
|
|
depends on DRM_EXYNOS_IPP
|
|
|
|
|
help
|
|
|
|
|
Choose this option if you want to use Exynos Rotator for DRM.
|
|
|
|
|
|
2012-12-14 16:58:57 +08:00
|
|
|
config DRM_EXYNOS_GSC
|
|
|
|
|
bool "Exynos DRM GSC"
|
2014-01-16 14:27:57 +08:00
|
|
|
depends on DRM_EXYNOS_IPP && ARCH_EXYNOS5 && !ARCH_MULTIPLATFORM
|
2012-12-14 16:58:57 +08:00
|
|
|
help
|
|
|
|
|
Choose this option if you want to use Exynos GSC for DRM.
|
