2018-09-27 01:47:15 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright(c) 2018 Intel Corporation. All rights reserved.
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* Intel specific definitions for NVDIMM Firmware Interface Table - NFIT
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*/
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#ifndef _NFIT_INTEL_H_
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#define _NFIT_INTEL_H_
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#define ND_INTEL_SMART 1
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#define ND_INTEL_SMART_SHUTDOWN_COUNT_VALID (1 << 5)
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#define ND_INTEL_SMART_SHUTDOWN_VALID (1 << 10)
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struct nd_intel_smart {
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u32 status;
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union {
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struct {
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u32 flags;
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u8 reserved0[4];
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u8 health;
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u8 spares;
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u8 life_used;
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u8 alarm_flags;
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u16 media_temperature;
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u16 ctrl_temperature;
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u32 shutdown_count;
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u8 ait_status;
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u16 pmic_temperature;
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u8 reserved1[8];
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u8 shutdown_state;
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u32 vendor_size;
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u8 vendor_data[92];
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} __packed;
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u8 data[128];
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};
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} __packed;
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2018-12-06 15:39:29 +08:00
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extern const struct nvdimm_security_ops *intel_security_ops;
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acpi/nfit: Add support for Intel DSM 1.8 commands
Add command definition for security commands defined in Intel DSM
specification v1.8 [1]. This includes "get security state", "set
passphrase", "unlock unit", "freeze lock", "secure erase", "overwrite",
"overwrite query", "master passphrase enable/disable", and "master
erase", . Since this adds several Intel definitions, move the relevant
bits to their own header.
These commands mutate physical data, but that manipulation is not cache
coherent. The requirement to flush and invalidate caches makes these
commands unsuitable to be called from userspace, so extra logic is added
to detect and block these commands from being submitted via the ioctl
command submission path.
Lastly, the commands may contain sensitive key material that should not
be dumped in a standard debug session. Update the nvdimm-command
payload-dump facility to move security command payloads behind a
default-off compile time switch.
[1]: http://pmem.io/documents/NVDIMM_DSM_Interface-V1.8.pdf
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2018-12-05 02:31:11 +08:00
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#define ND_INTEL_STATUS_SIZE 4
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#define ND_INTEL_PASSPHRASE_SIZE 32
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#define ND_INTEL_STATUS_NOT_SUPPORTED 1
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#define ND_INTEL_STATUS_RETRY 5
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#define ND_INTEL_STATUS_NOT_READY 9
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#define ND_INTEL_STATUS_INVALID_STATE 10
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#define ND_INTEL_STATUS_INVALID_PASS 11
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#define ND_INTEL_STATUS_OVERWRITE_UNSUPPORTED 0x10007
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#define ND_INTEL_STATUS_OQUERY_INPROGRESS 0x10007
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#define ND_INTEL_STATUS_OQUERY_SEQUENCE_ERR 0x20007
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#define ND_INTEL_SEC_STATE_ENABLED 0x02
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#define ND_INTEL_SEC_STATE_LOCKED 0x04
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#define ND_INTEL_SEC_STATE_FROZEN 0x08
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#define ND_INTEL_SEC_STATE_PLIMIT 0x10
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#define ND_INTEL_SEC_STATE_UNSUPPORTED 0x20
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#define ND_INTEL_SEC_STATE_OVERWRITE 0x40
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#define ND_INTEL_SEC_ESTATE_ENABLED 0x01
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#define ND_INTEL_SEC_ESTATE_PLIMIT 0x02
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struct nd_intel_get_security_state {
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u32 status;
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u8 extended_state;
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u8 reserved[3];
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u8 state;
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u8 reserved1[3];
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} __packed;
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struct nd_intel_set_passphrase {
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u8 old_pass[ND_INTEL_PASSPHRASE_SIZE];
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u8 new_pass[ND_INTEL_PASSPHRASE_SIZE];
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u32 status;
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} __packed;
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struct nd_intel_unlock_unit {
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u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
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u32 status;
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} __packed;
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struct nd_intel_disable_passphrase {
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u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
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u32 status;
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} __packed;
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struct nd_intel_freeze_lock {
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u32 status;
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} __packed;
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struct nd_intel_secure_erase {
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u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
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u32 status;
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} __packed;
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struct nd_intel_overwrite {
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u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
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u32 status;
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} __packed;
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struct nd_intel_query_overwrite {
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u32 status;
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} __packed;
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struct nd_intel_set_master_passphrase {
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u8 old_pass[ND_INTEL_PASSPHRASE_SIZE];
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u8 new_pass[ND_INTEL_PASSPHRASE_SIZE];
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u32 status;
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} __packed;
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struct nd_intel_master_secure_erase {
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u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
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u32 status;
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} __packed;
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2020-07-21 06:07:40 +08:00
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#define ND_INTEL_FWA_IDLE 0
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#define ND_INTEL_FWA_ARMED 1
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#define ND_INTEL_FWA_BUSY 2
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#define ND_INTEL_DIMM_FWA_NONE 0
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#define ND_INTEL_DIMM_FWA_NOTSTAGED 1
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#define ND_INTEL_DIMM_FWA_SUCCESS 2
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#define ND_INTEL_DIMM_FWA_NEEDRESET 3
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#define ND_INTEL_DIMM_FWA_MEDIAFAILED 4
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#define ND_INTEL_DIMM_FWA_ABORT 5
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#define ND_INTEL_DIMM_FWA_NOTSUPP 6
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#define ND_INTEL_DIMM_FWA_ERROR 7
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struct nd_intel_fw_activate_dimminfo {
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u32 status;
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u16 result;
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u8 state;
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u8 reserved[7];
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} __packed;
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2020-07-21 06:08:02 +08:00
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#define ND_INTEL_DIMM_FWA_ARM 1
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#define ND_INTEL_DIMM_FWA_DISARM 0
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2020-07-21 06:07:40 +08:00
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struct nd_intel_fw_activate_arm {
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u8 activate_arm;
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u32 status;
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} __packed;
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/* Root device command payloads */
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#define ND_INTEL_BUS_FWA_CAP_FWQUIESCE (1 << 0)
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#define ND_INTEL_BUS_FWA_CAP_OSQUIESCE (1 << 1)
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#define ND_INTEL_BUS_FWA_CAP_RESET (1 << 2)
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struct nd_intel_bus_fw_activate_businfo {
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u32 status;
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u16 reserved;
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u8 state;
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u8 capability;
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u64 activate_tmo;
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u64 cpu_quiesce_tmo;
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u64 io_quiesce_tmo;
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u64 max_quiesce_tmo;
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} __packed;
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#define ND_INTEL_BUS_FWA_STATUS_NOARM (6 | 1 << 16)
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#define ND_INTEL_BUS_FWA_STATUS_BUSY (6 | 2 << 16)
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#define ND_INTEL_BUS_FWA_STATUS_NOFW (6 | 3 << 16)
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#define ND_INTEL_BUS_FWA_STATUS_TMO (6 | 4 << 16)
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#define ND_INTEL_BUS_FWA_STATUS_NOIDLE (6 | 5 << 16)
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#define ND_INTEL_BUS_FWA_STATUS_ABORT (6 | 6 << 16)
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2020-07-21 06:08:02 +08:00
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#define ND_INTEL_BUS_FWA_IODEV_FORCE_IDLE (0)
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#define ND_INTEL_BUS_FWA_IODEV_OS_IDLE (1)
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2020-07-21 06:07:40 +08:00
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struct nd_intel_bus_fw_activate {
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u8 iodev_state;
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u32 status;
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} __packed;
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2020-07-21 06:08:24 +08:00
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extern const struct nvdimm_fw_ops *intel_fw_ops;
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extern const struct nvdimm_bus_fw_ops *intel_bus_fw_ops;
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2018-09-27 01:47:15 +08:00
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#endif
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