2015-06-12 15:57:06 +08:00
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#define pr_fmt(fmt) "DMAR-IR: " fmt
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2008-08-20 11:49:59 +08:00
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#include <linux/interrupt.h>
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2008-07-11 02:16:40 +08:00
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#include <linux/dmar.h>
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2008-07-11 02:16:43 +08:00
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#include <linux/spinlock.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2008-07-11 02:16:43 +08:00
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#include <linux/jiffies.h>
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2009-08-05 03:07:08 +08:00
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#include <linux/hpet.h>
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2008-07-11 02:16:43 +08:00
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#include <linux/pci.h>
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2008-07-11 02:16:44 +08:00
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#include <linux/irq.h>
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2013-12-03 08:49:16 +08:00
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#include <linux/intel-iommu.h>
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#include <linux/acpi.h>
|
2015-04-13 14:11:32 +08:00
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#include <linux/irqdomain.h>
|
2015-06-12 21:00:21 +08:00
|
|
|
#include <linux/crash_dump.h>
|
2008-07-11 02:16:40 +08:00
|
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#include <asm/io_apic.h>
|
2008-12-13 05:14:18 +08:00
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#include <asm/smp.h>
|
2009-01-08 00:08:59 +08:00
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#include <asm/cpu.h>
|
2012-03-31 02:47:08 +08:00
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#include <asm/irq_remapping.h>
|
2009-05-23 00:41:15 +08:00
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#include <asm/pci-direct.h>
|
2012-03-31 02:47:05 +08:00
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#include <asm/msidef.h>
|
2008-07-11 02:16:40 +08:00
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|
2012-03-31 02:47:08 +08:00
|
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#include "irq_remapping.h"
|
2012-03-31 02:47:00 +08:00
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|
2015-06-09 13:20:32 +08:00
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enum irq_mode {
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IRQ_REMAPPING,
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IRQ_POSTING,
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};
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|
2012-03-31 02:46:59 +08:00
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struct ioapic_scope {
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struct intel_iommu *iommu;
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unsigned int id;
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unsigned int bus; /* PCI bus number */
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unsigned int devfn; /* PCI devfn number */
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|
};
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struct hpet_scope {
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struct intel_iommu *iommu;
|
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u8 id;
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|
unsigned int bus;
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unsigned int devfn;
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};
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|
2015-04-14 10:29:51 +08:00
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struct irq_2_iommu {
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|
struct intel_iommu *iommu;
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|
u16 irte_index;
|
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|
|
u16 sub_handle;
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|
|
u8 irte_mask;
|
2015-06-09 13:20:32 +08:00
|
|
|
enum irq_mode mode;
|
2015-04-14 10:29:51 +08:00
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|
};
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|
2015-04-13 14:11:32 +08:00
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|
struct intel_ir_data {
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struct irq_2_iommu irq_2_iommu;
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struct irte irte_entry;
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union {
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|
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struct msi_msg msi_entry;
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};
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};
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|
2012-03-31 02:46:59 +08:00
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|
#define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
|
2015-01-07 15:31:37 +08:00
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|
#define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
|
2012-03-31 02:46:59 +08:00
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|
2015-01-07 15:31:37 +08:00
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|
static int __read_mostly eim_mode;
|
2008-07-11 02:16:40 +08:00
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static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
|
2009-08-05 03:07:08 +08:00
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static struct hpet_scope ir_hpet[MAX_HPET_TBS];
|
2010-07-21 02:06:49 +08:00
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|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 14:07:33 +08:00
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|
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/*
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* Lock ordering:
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* ->dmar_global_lock
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* ->irq_2_ir_lock
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* ->qi->q_lock
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* ->iommu->register_lock
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* Note:
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* intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
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|
* in single-threaded environment with interrupt disabled, so no need to tabke
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* the dmar_global_lock.
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*/
|
2011-07-19 22:28:19 +08:00
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static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
|
2015-04-13 14:11:32 +08:00
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static struct irq_domain_ops intel_ir_domain_ops;
|
2010-10-10 18:34:27 +08:00
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|
2015-06-12 21:00:21 +08:00
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static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
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2014-01-06 14:18:16 +08:00
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static int __init parse_ioapics_under_ir(void);
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2015-06-12 21:00:21 +08:00
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static bool ir_pre_enabled(struct intel_iommu *iommu)
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{
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return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
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}
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static void clear_ir_pre_enabled(struct intel_iommu *iommu)
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{
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iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
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}
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static void init_ir_status(struct intel_iommu *iommu)
|
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|
|
{
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|
u32 gsts;
|
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gsts = readl(iommu->reg + DMAR_GSTS_REG);
|
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if (gsts & DMA_GSTS_IRES)
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iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
|
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}
|
|
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|
|
2015-04-13 14:11:31 +08:00
|
|
|
static int alloc_irte(struct intel_iommu *iommu, int irq,
|
|
|
|
struct irq_2_iommu *irq_iommu, u16 count)
|
2008-07-11 02:16:44 +08:00
|
|
|
{
|
|
|
|
struct ir_table *table = iommu->ir_table;
|
|
|
|
unsigned int mask = 0;
|
2009-03-17 08:04:53 +08:00
|
|
|
unsigned long flags;
|
2014-01-09 13:32:36 +08:00
|
|
|
int index;
|
2008-07-11 02:16:44 +08:00
|
|
|
|
2010-10-10 18:34:27 +08:00
|
|
|
if (!count || !irq_iommu)
|
2008-08-20 11:50:21 +08:00
|
|
|
return -1;
|
|
|
|
|
2008-07-11 02:16:44 +08:00
|
|
|
if (count > 1) {
|
|
|
|
count = __roundup_pow_of_two(count);
|
|
|
|
mask = ilog2(count);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mask > ecap_max_handle_mask(iommu->ecap)) {
|
2015-06-12 15:57:06 +08:00
|
|
|
pr_err("Requested mask %x exceeds the max invalidation handle"
|
2008-07-11 02:16:44 +08:00
|
|
|
" mask value %Lx\n", mask,
|
|
|
|
ecap_max_handle_mask(iommu->ecap));
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2011-07-19 22:28:19 +08:00
|
|
|
raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
|
2014-01-06 14:18:08 +08:00
|
|
|
index = bitmap_find_free_region(table->bitmap,
|
|
|
|
INTR_REMAP_TABLE_ENTRIES, mask);
|
|
|
|
if (index < 0) {
|
|
|
|
pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
|
|
|
|
} else {
|
|
|
|
irq_iommu->iommu = iommu;
|
|
|
|
irq_iommu->irte_index = index;
|
|
|
|
irq_iommu->sub_handle = 0;
|
|
|
|
irq_iommu->irte_mask = mask;
|
2015-06-09 13:20:32 +08:00
|
|
|
irq_iommu->mode = IRQ_REMAPPING;
|
2014-01-06 14:18:08 +08:00
|
|
|
}
|
2011-07-19 22:28:19 +08:00
|
|
|
raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
|
2008-07-11 02:16:44 +08:00
|
|
|
|
|
|
|
return index;
|
|
|
|
}
|
|
|
|
|
2009-01-04 16:28:52 +08:00
|
|
|
static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
|
2008-07-11 02:16:44 +08:00
|
|
|
{
|
|
|
|
struct qi_desc desc;
|
|
|
|
|
|
|
|
desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
|
|
|
|
| QI_IEC_SELECTIVE;
|
|
|
|
desc.high = 0;
|
|
|
|
|
2009-01-04 16:28:52 +08:00
|
|
|
return qi_submit_sync(&desc, iommu);
|
2008-07-11 02:16:44 +08:00
|
|
|
}
|
|
|
|
|
2015-04-13 14:11:31 +08:00
|
|
|
static int modify_irte(struct irq_2_iommu *irq_iommu,
|
|
|
|
struct irte *irte_modified)
|
2008-07-11 02:16:44 +08:00
|
|
|
{
|
|
|
|
struct intel_iommu *iommu;
|
2009-03-17 08:04:53 +08:00
|
|
|
unsigned long flags;
|
2010-10-10 18:34:27 +08:00
|
|
|
struct irte *irte;
|
|
|
|
int rc, index;
|
2008-07-11 02:16:44 +08:00
|
|
|
|
2010-10-10 18:34:27 +08:00
|
|
|
if (!irq_iommu)
|
2008-07-11 02:16:44 +08:00
|
|
|
return -1;
|
2010-10-10 18:34:27 +08:00
|
|
|
|
2011-07-19 22:28:19 +08:00
|
|
|
raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
|
2008-07-11 02:16:44 +08:00
|
|
|
|
2008-08-20 11:50:21 +08:00
|
|
|
iommu = irq_iommu->iommu;
|
2008-07-11 02:16:44 +08:00
|
|
|
|
2008-08-20 11:50:21 +08:00
|
|
|
index = irq_iommu->irte_index + irq_iommu->sub_handle;
|
2008-07-11 02:16:44 +08:00
|
|
|
irte = &iommu->ir_table->base[index];
|
|
|
|
|
2015-10-15 10:19:11 +08:00
|
|
|
#if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
|
|
|
|
if ((irte->pst == 1) || (irte_modified->pst == 1)) {
|
|
|
|
bool ret;
|
|
|
|
|
|
|
|
ret = cmpxchg_double(&irte->low, &irte->high,
|
|
|
|
irte->low, irte->high,
|
|
|
|
irte_modified->low, irte_modified->high);
|
|
|
|
/*
|
|
|
|
* We use cmpxchg16 to atomically update the 128-bit IRTE,
|
|
|
|
* and it cannot be updated by the hardware or other processors
|
|
|
|
* behind us, so the return value of cmpxchg16 should be the
|
|
|
|
* same as the old value.
|
|
|
|
*/
|
|
|
|
WARN_ON(!ret);
|
|
|
|
} else
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
set_64bit(&irte->low, irte_modified->low);
|
|
|
|
set_64bit(&irte->high, irte_modified->high);
|
|
|
|
}
|
2008-07-11 02:16:44 +08:00
|
|
|
__iommu_flush_cache(iommu, irte, sizeof(*irte));
|
|
|
|
|
2009-01-04 16:28:52 +08:00
|
|
|
rc = qi_flush_iec(iommu, index, 0);
|
2015-06-09 13:20:32 +08:00
|
|
|
|
|
|
|
/* Update iommu mode according to the IRTE mode */
|
|
|
|
irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
|
2011-07-19 22:28:19 +08:00
|
|
|
raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
|
2009-01-04 16:28:52 +08:00
|
|
|
|
|
|
|
return rc;
|
2008-07-11 02:16:44 +08:00
|
|
|
}
|
|
|
|
|
2012-03-31 02:47:06 +08:00
|
|
|
static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
|
2009-08-05 03:07:08 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < MAX_HPET_TBS; i++)
|
2014-11-09 22:48:00 +08:00
|
|
|
if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
|
2009-08-05 03:07:08 +08:00
|
|
|
return ir_hpet[i].iommu;
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2012-03-31 02:47:06 +08:00
|
|
|
static struct intel_iommu *map_ioapic_to_ir(int apic)
|
x64, x2apic/intr-remap: IO-APIC support for interrupt-remapping
IO-APIC support in the presence of interrupt-remapping infrastructure.
IO-APIC RTE will be programmed with interrupt-remapping table entry(IRTE)
index and the IRTE will contain information about the vector, cpu destination,
trigger mode etc, which traditionally was present in the IO-APIC RTE.
Introduce a new irq_chip for cleaner irq migration (in the process
context as opposed to the current irq migration in the context of an interrupt.
interrupt-remapping infrastructure will help us achieve this cleanly).
For edge triggered, irq migration is a simple atomic update(of vector
and cpu destination) of IRTE and flush the hardware cache.
For level triggered, we need to modify the io-apic RTE aswell with the update
vector information, along with modifying IRTE with vector and cpu destination.
So irq migration for level triggered is little bit more complex compared to
edge triggered migration. But the good news is, we use the same algorithm
for level triggered migration as we have today, only difference being,
we now initiate the irq migration from process context instead of the
interrupt context.
In future, when we do a directed EOI (combined with cpu EOI broadcast
suppression) to the IO-APIC, level triggered irq migration will also be
as simple as edge triggered migration and we can do the irq migration
with a simple atomic update to IO-APIC RTE.
TBD: some tests/changes needed in the presence of fixup_irqs() for
level triggered irq migration.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: akpm@linux-foundation.org
Cc: arjan@linux.intel.com
Cc: andi@firstfloor.org
Cc: ebiederm@xmission.com
Cc: jbarnes@virtuousgeek.org
Cc: steiner@sgi.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11 02:16:56 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < MAX_IO_APICS; i++)
|
2014-11-09 22:48:00 +08:00
|
|
|
if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
|
x64, x2apic/intr-remap: IO-APIC support for interrupt-remapping
IO-APIC support in the presence of interrupt-remapping infrastructure.
IO-APIC RTE will be programmed with interrupt-remapping table entry(IRTE)
index and the IRTE will contain information about the vector, cpu destination,
trigger mode etc, which traditionally was present in the IO-APIC RTE.
Introduce a new irq_chip for cleaner irq migration (in the process
context as opposed to the current irq migration in the context of an interrupt.
interrupt-remapping infrastructure will help us achieve this cleanly).
For edge triggered, irq migration is a simple atomic update(of vector
and cpu destination) of IRTE and flush the hardware cache.
For level triggered, we need to modify the io-apic RTE aswell with the update
vector information, along with modifying IRTE with vector and cpu destination.
So irq migration for level triggered is little bit more complex compared to
edge triggered migration. But the good news is, we use the same algorithm
for level triggered migration as we have today, only difference being,
we now initiate the irq migration from process context instead of the
interrupt context.
In future, when we do a directed EOI (combined with cpu EOI broadcast
suppression) to the IO-APIC, level triggered irq migration will also be
as simple as edge triggered migration and we can do the irq migration
with a simple atomic update to IO-APIC RTE.
TBD: some tests/changes needed in the presence of fixup_irqs() for
level triggered irq migration.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: akpm@linux-foundation.org
Cc: arjan@linux.intel.com
Cc: andi@firstfloor.org
Cc: ebiederm@xmission.com
Cc: jbarnes@virtuousgeek.org
Cc: steiner@sgi.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11 02:16:56 +08:00
|
|
|
return ir_ioapic[i].iommu;
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2012-03-31 02:47:06 +08:00
|
|
|
static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
|
2008-07-11 02:16:57 +08:00
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
|
|
|
|
drhd = dmar_find_matched_drhd_unit(dev);
|
|
|
|
if (!drhd)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return drhd->iommu;
|
|
|
|
}
|
|
|
|
|
2009-05-23 00:41:14 +08:00
|
|
|
static int clear_entries(struct irq_2_iommu *irq_iommu)
|
|
|
|
{
|
|
|
|
struct irte *start, *entry, *end;
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
int index;
|
|
|
|
|
|
|
|
if (irq_iommu->sub_handle)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
iommu = irq_iommu->iommu;
|
2015-04-13 14:11:31 +08:00
|
|
|
index = irq_iommu->irte_index;
|
2009-05-23 00:41:14 +08:00
|
|
|
|
|
|
|
start = iommu->ir_table->base + index;
|
|
|
|
end = start + (1 << irq_iommu->irte_mask);
|
|
|
|
|
|
|
|
for (entry = start; entry < end; entry++) {
|
2010-08-07 02:02:31 +08:00
|
|
|
set_64bit(&entry->low, 0);
|
|
|
|
set_64bit(&entry->high, 0);
|
2009-05-23 00:41:14 +08:00
|
|
|
}
|
2014-01-06 14:18:08 +08:00
|
|
|
bitmap_release_region(iommu->ir_table->bitmap, index,
|
|
|
|
irq_iommu->irte_mask);
|
2009-05-23 00:41:14 +08:00
|
|
|
|
|
|
|
return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
|
|
|
|
}
|
|
|
|
|
2009-05-23 00:41:15 +08:00
|
|
|
/*
|
|
|
|
* source validation type
|
|
|
|
*/
|
|
|
|
#define SVT_NO_VERIFY 0x0 /* no verification is required */
|
2011-03-31 09:57:33 +08:00
|
|
|
#define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
|
2009-05-23 00:41:15 +08:00
|
|
|
#define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* source-id qualifier
|
|
|
|
*/
|
|
|
|
#define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
|
|
|
|
#define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
|
|
|
|
* the third least significant bit
|
|
|
|
*/
|
|
|
|
#define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
|
|
|
|
* the second and third least significant bits
|
|
|
|
*/
|
|
|
|
#define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
|
|
|
|
* the least three significant bits
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* set SVT, SQ and SID fields of irte to verify
|
|
|
|
* source ids of interrupt requests
|
|
|
|
*/
|
|
|
|
static void set_irte_sid(struct irte *irte, unsigned int svt,
|
|
|
|
unsigned int sq, unsigned int sid)
|
|
|
|
{
|
2010-07-21 02:06:49 +08:00
|
|
|
if (disable_sourceid_checking)
|
|
|
|
svt = SVT_NO_VERIFY;
|
2009-05-23 00:41:15 +08:00
|
|
|
irte->svt = svt;
|
|
|
|
irte->sq = sq;
|
|
|
|
irte->sid = sid;
|
|
|
|
}
|
|
|
|
|
2012-03-31 02:47:06 +08:00
|
|
|
static int set_ioapic_sid(struct irte *irte, int apic)
|
2009-05-23 00:41:15 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
u16 sid = 0;
|
|
|
|
|
|
|
|
if (!irte)
|
|
|
|
return -1;
|
|
|
|
|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 14:07:33 +08:00
|
|
|
down_read(&dmar_global_lock);
|
2009-05-23 00:41:15 +08:00
|
|
|
for (i = 0; i < MAX_IO_APICS; i++) {
|
2014-11-09 22:48:00 +08:00
|
|
|
if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
|
2009-05-23 00:41:15 +08:00
|
|
|
sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 14:07:33 +08:00
|
|
|
up_read(&dmar_global_lock);
|
2009-05-23 00:41:15 +08:00
|
|
|
|
|
|
|
if (sid == 0) {
|
2015-06-12 15:57:06 +08:00
|
|
|
pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
|
2009-05-23 00:41:15 +08:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2014-01-06 14:18:17 +08:00
|
|
|
set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
|
2009-05-23 00:41:15 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-03-31 02:47:06 +08:00
|
|
|
static int set_hpet_sid(struct irte *irte, u8 id)
|
2009-08-05 03:07:08 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
u16 sid = 0;
|
|
|
|
|
|
|
|
if (!irte)
|
|
|
|
return -1;
|
|
|
|
|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 14:07:33 +08:00
|
|
|
down_read(&dmar_global_lock);
|
2009-08-05 03:07:08 +08:00
|
|
|
for (i = 0; i < MAX_HPET_TBS; i++) {
|
2014-11-09 22:48:00 +08:00
|
|
|
if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
|
2009-08-05 03:07:08 +08:00
|
|
|
sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 14:07:33 +08:00
|
|
|
up_read(&dmar_global_lock);
|
2009-08-05 03:07:08 +08:00
|
|
|
|
|
|
|
if (sid == 0) {
|
2015-06-12 15:57:06 +08:00
|
|
|
pr_warn("Failed to set source-id of HPET block (%d)\n", id);
|
2009-08-05 03:07:08 +08:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Should really use SQ_ALL_16. Some platforms are broken.
|
|
|
|
* While we figure out the right quirks for these broken platforms, use
|
|
|
|
* SQ_13_IGNORE_3 for now.
|
|
|
|
*/
|
|
|
|
set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-07-03 23:51:43 +08:00
|
|
|
struct set_msi_sid_data {
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
u16 alias;
|
|
|
|
};
|
|
|
|
|
|
|
|
static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
|
|
|
|
{
|
|
|
|
struct set_msi_sid_data *data = opaque;
|
|
|
|
|
|
|
|
data->pdev = pdev;
|
|
|
|
data->alias = alias;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-03-31 02:47:06 +08:00
|
|
|
static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
|
2009-05-23 00:41:15 +08:00
|
|
|
{
|
2014-07-03 23:51:43 +08:00
|
|
|
struct set_msi_sid_data data;
|
2009-05-23 00:41:15 +08:00
|
|
|
|
|
|
|
if (!irte || !dev)
|
|
|
|
return -1;
|
|
|
|
|
2014-07-03 23:51:43 +08:00
|
|
|
pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
|
2009-05-23 00:41:15 +08:00
|
|
|
|
2014-07-03 23:51:43 +08:00
|
|
|
/*
|
|
|
|
* DMA alias provides us with a PCI device and alias. The only case
|
|
|
|
* where the it will return an alias on a different bus than the
|
|
|
|
* device is the case of a PCIe-to-PCI bridge, where the alias is for
|
|
|
|
* the subordinate bus. In this case we can only verify the bus.
|
|
|
|
*
|
|
|
|
* If the alias device is on a different bus than our source device
|
|
|
|
* then we have a topology based alias, use it.
|
|
|
|
*
|
|
|
|
* Otherwise, the alias is for a device DMA quirk and we cannot
|
|
|
|
* assume that MSI uses the same requester ID. Therefore use the
|
|
|
|
* original device.
|
|
|
|
*/
|
|
|
|
if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
|
|
|
|
set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
|
|
|
|
PCI_DEVID(PCI_BUS_NUM(data.alias),
|
|
|
|
dev->bus->number));
|
|
|
|
else if (data.pdev->bus->number != dev->bus->number)
|
|
|
|
set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
|
|
|
|
else
|
|
|
|
set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
|
|
|
|
PCI_DEVID(dev->bus->number, dev->devfn));
|
2009-05-23 00:41:15 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-06-12 21:00:21 +08:00
|
|
|
static int iommu_load_old_irte(struct intel_iommu *iommu)
|
|
|
|
{
|
2015-10-10 06:16:46 +08:00
|
|
|
struct irte *old_ir_table;
|
2015-06-12 21:00:21 +08:00
|
|
|
phys_addr_t irt_phys;
|
2015-06-12 21:06:26 +08:00
|
|
|
unsigned int i;
|
2015-06-12 21:00:21 +08:00
|
|
|
size_t size;
|
|
|
|
u64 irta;
|
|
|
|
|
|
|
|
/* Check whether the old ir-table has the same size as ours */
|
|
|
|
irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
|
|
|
|
if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
|
|
|
|
!= INTR_REMAP_TABLE_REG_SIZE)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
irt_phys = irta & VTD_PAGE_MASK;
|
|
|
|
size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
|
|
|
|
|
|
|
|
/* Map the old IR table */
|
2015-10-10 06:16:46 +08:00
|
|
|
old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
|
2015-06-12 21:00:21 +08:00
|
|
|
if (!old_ir_table)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
/* Copy data over */
|
2015-10-10 06:16:46 +08:00
|
|
|
memcpy(iommu->ir_table->base, old_ir_table, size);
|
2015-06-12 21:00:21 +08:00
|
|
|
|
|
|
|
__iommu_flush_cache(iommu, iommu->ir_table->base, size);
|
|
|
|
|
2015-06-12 21:06:26 +08:00
|
|
|
/*
|
|
|
|
* Now check the table for used entries and mark those as
|
|
|
|
* allocated in the bitmap
|
|
|
|
*/
|
|
|
|
for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
|
|
|
|
if (iommu->ir_table->base[i].present)
|
|
|
|
bitmap_set(iommu->ir_table->bitmap, i, 1);
|
|
|
|
}
|
|
|
|
|
2015-10-10 06:16:46 +08:00
|
|
|
memunmap(old_ir_table);
|
2015-07-31 00:54:01 +08:00
|
|
|
|
2015-06-12 21:00:21 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2012-03-31 02:47:07 +08:00
|
|
|
static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
|
2008-07-11 02:16:43 +08:00
|
|
|
{
|
2015-06-12 20:35:54 +08:00
|
|
|
unsigned long flags;
|
2008-07-11 02:16:43 +08:00
|
|
|
u64 addr;
|
2009-05-11 03:30:58 +08:00
|
|
|
u32 sts;
|
2008-07-11 02:16:43 +08:00
|
|
|
|
|
|
|
addr = virt_to_phys((void *)iommu->ir_table->base);
|
|
|
|
|
2011-07-19 22:19:51 +08:00
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flags);
|
2008-07-11 02:16:43 +08:00
|
|
|
|
|
|
|
dmar_writeq(iommu->reg + DMAR_IRTA_REG,
|
|
|
|
(addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
|
|
|
|
|
|
|
|
/* Set interrupt-remapping table pointer */
|
2014-08-11 19:13:25 +08:00
|
|
|
writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
|
2008-07-11 02:16:43 +08:00
|
|
|
|
|
|
|
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
|
|
|
|
readl, (sts & DMA_GSTS_IRTPS), sts);
|
2011-07-19 22:19:51 +08:00
|
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
|
2008-07-11 02:16:43 +08:00
|
|
|
|
|
|
|
/*
|
2015-06-12 20:35:54 +08:00
|
|
|
* Global invalidation of interrupt entry cache to make sure the
|
|
|
|
* hardware uses the new irq remapping table.
|
2008-07-11 02:16:43 +08:00
|
|
|
*/
|
|
|
|
qi_global_iec(iommu);
|
2015-06-12 20:35:54 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
u32 sts;
|
2008-07-11 02:16:43 +08:00
|
|
|
|
2011-07-19 22:19:51 +08:00
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flags);
|
2008-07-11 02:16:43 +08:00
|
|
|
|
|
|
|
/* Enable interrupt-remapping */
|
|
|
|
iommu->gcmd |= DMA_GCMD_IRE;
|
2013-02-02 06:57:43 +08:00
|
|
|
iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
|
2009-05-11 03:30:58 +08:00
|
|
|
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
|
2008-07-11 02:16:43 +08:00
|
|
|
|
|
|
|
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
|
|
|
|
readl, (sts & DMA_GSTS_IRES), sts);
|
|
|
|
|
2013-02-02 06:57:43 +08:00
|
|
|
/*
|
|
|
|
* With CFI clear in the Global Command register, we should be
|
|
|
|
* protected from dangerous (i.e. compatibility) interrupts
|
|
|
|
* regardless of x2apic status. Check just to be sure.
|
|
|
|
*/
|
|
|
|
if (sts & DMA_GSTS_CFIS)
|
|
|
|
WARN(1, KERN_WARNING
|
|
|
|
"Compatibility-format IRQs enabled despite intr remapping;\n"
|
|
|
|
"you are vulnerable to IRQ injection.\n");
|
|
|
|
|
2011-07-19 22:19:51 +08:00
|
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
|
2008-07-11 02:16:43 +08:00
|
|
|
}
|
|
|
|
|
2014-11-09 22:48:00 +08:00
|
|
|
static int intel_setup_irq_remapping(struct intel_iommu *iommu)
|
2008-07-11 02:16:43 +08:00
|
|
|
{
|
|
|
|
struct ir_table *ir_table;
|
|
|
|
struct page *pages;
|
2014-01-06 14:18:08 +08:00
|
|
|
unsigned long *bitmap;
|
2008-07-11 02:16:43 +08:00
|
|
|
|
2014-11-09 22:48:00 +08:00
|
|
|
if (iommu->ir_table)
|
|
|
|
return 0;
|
2008-07-11 02:16:43 +08:00
|
|
|
|
2015-01-07 15:31:30 +08:00
|
|
|
ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
|
2014-11-09 22:48:00 +08:00
|
|
|
if (!ir_table)
|
2008-07-11 02:16:43 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2015-01-07 15:31:30 +08:00
|
|
|
pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
|
2009-10-03 02:01:23 +08:00
|
|
|
INTR_REMAP_PAGE_ORDER);
|
2008-07-11 02:16:43 +08:00
|
|
|
if (!pages) {
|
2014-01-06 14:18:08 +08:00
|
|
|
pr_err("IR%d: failed to allocate pages of order %d\n",
|
|
|
|
iommu->seq_id, INTR_REMAP_PAGE_ORDER);
|
2014-11-09 22:48:00 +08:00
|
|
|
goto out_free_table;
|
2008-07-11 02:16:43 +08:00
|
|
|
}
|
|
|
|
|
2014-01-06 14:18:08 +08:00
|
|
|
bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
|
|
|
|
sizeof(long), GFP_ATOMIC);
|
|
|
|
if (bitmap == NULL) {
|
|
|
|
pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
|
2014-11-09 22:48:00 +08:00
|
|
|
goto out_free_pages;
|
2014-01-06 14:18:08 +08:00
|
|
|
}
|
|
|
|
|
2015-04-13 14:11:32 +08:00
|
|
|
iommu->ir_domain = irq_domain_add_hierarchy(arch_get_ir_parent_domain(),
|
|
|
|
0, INTR_REMAP_TABLE_ENTRIES,
|
|
|
|
NULL, &intel_ir_domain_ops,
|
|
|
|
iommu);
|
|
|
|
if (!iommu->ir_domain) {
|
|
|
|
pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
|
|
|
|
goto out_free_bitmap;
|
|
|
|
}
|
|
|
|
iommu->ir_msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
|
|
|
|
|
2008-07-11 02:16:43 +08:00
|
|
|
ir_table->base = page_address(pages);
|
2014-01-06 14:18:08 +08:00
|
|
|
ir_table->bitmap = bitmap;
|
2014-11-09 22:48:00 +08:00
|
|
|
iommu->ir_table = ir_table;
|
2015-06-12 20:23:56 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If the queued invalidation is already initialized,
|
|
|
|
* shouldn't disable it.
|
|
|
|
*/
|
|
|
|
if (!iommu->qi) {
|
|
|
|
/*
|
|
|
|
* Clear previous faults.
|
|
|
|
*/
|
|
|
|
dmar_fault(-1, iommu);
|
|
|
|
dmar_disable_qi(iommu);
|
|
|
|
|
|
|
|
if (dmar_enable_qi(iommu)) {
|
|
|
|
pr_err("Failed to enable queued invalidation\n");
|
|
|
|
goto out_free_bitmap;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-06-12 21:00:21 +08:00
|
|
|
init_ir_status(iommu);
|
|
|
|
|
|
|
|
if (ir_pre_enabled(iommu)) {
|
2017-04-28 01:16:15 +08:00
|
|
|
if (!is_kdump_kernel()) {
|
|
|
|
pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
|
|
|
|
iommu->name);
|
|
|
|
clear_ir_pre_enabled(iommu);
|
|
|
|
iommu_disable_irq_remapping(iommu);
|
|
|
|
} else if (iommu_load_old_irte(iommu))
|
2015-06-12 21:00:21 +08:00
|
|
|
pr_err("Failed to copy IR table for %s from previous kernel\n",
|
|
|
|
iommu->name);
|
|
|
|
else
|
|
|
|
pr_info("Copied IR table for %s from previous kernel\n",
|
|
|
|
iommu->name);
|
|
|
|
}
|
|
|
|
|
2015-06-12 20:35:54 +08:00
|
|
|
iommu_set_irq_remapping(iommu, eim_mode);
|
|
|
|
|
2008-07-11 02:16:43 +08:00
|
|
|
return 0;
|
2014-11-09 22:48:00 +08:00
|
|
|
|
2015-04-13 14:11:32 +08:00
|
|
|
out_free_bitmap:
|
|
|
|
kfree(bitmap);
|
2014-11-09 22:48:00 +08:00
|
|
|
out_free_pages:
|
|
|
|
__free_pages(pages, INTR_REMAP_PAGE_ORDER);
|
|
|
|
out_free_table:
|
|
|
|
kfree(ir_table);
|
2015-06-12 20:23:56 +08:00
|
|
|
|
|
|
|
iommu->ir_table = NULL;
|
|
|
|
|
2014-11-09 22:48:00 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
if (iommu && iommu->ir_table) {
|
2015-04-13 14:11:32 +08:00
|
|
|
if (iommu->ir_msi_domain) {
|
|
|
|
irq_domain_remove(iommu->ir_msi_domain);
|
|
|
|
iommu->ir_msi_domain = NULL;
|
|
|
|
}
|
|
|
|
if (iommu->ir_domain) {
|
|
|
|
irq_domain_remove(iommu->ir_domain);
|
|
|
|
iommu->ir_domain = NULL;
|
|
|
|
}
|
2014-11-09 22:48:00 +08:00
|
|
|
free_pages((unsigned long)iommu->ir_table->base,
|
|
|
|
INTR_REMAP_PAGE_ORDER);
|
|
|
|
kfree(iommu->ir_table->bitmap);
|
|
|
|
kfree(iommu->ir_table);
|
|
|
|
iommu->ir_table = NULL;
|
|
|
|
}
|
2008-07-11 02:16:43 +08:00
|
|
|
}
|
|
|
|
|
2009-03-17 08:04:56 +08:00
|
|
|
/*
|
|
|
|
* Disable Interrupt Remapping.
|
|
|
|
*/
|
2012-03-31 02:47:07 +08:00
|
|
|
static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
|
2009-03-17 08:04:56 +08:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
u32 sts;
|
|
|
|
|
|
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
|
|
return;
|
|
|
|
|
2009-03-28 05:22:44 +08:00
|
|
|
/*
|
|
|
|
* global invalidation of interrupt entry cache before disabling
|
|
|
|
* interrupt-remapping.
|
|
|
|
*/
|
|
|
|
qi_global_iec(iommu);
|
|
|
|
|
2011-07-19 22:19:51 +08:00
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flags);
|
2009-03-17 08:04:56 +08:00
|
|
|
|
2016-01-14 05:15:03 +08:00
|
|
|
sts = readl(iommu->reg + DMAR_GSTS_REG);
|
2009-03-17 08:04:56 +08:00
|
|
|
if (!(sts & DMA_GSTS_IRES))
|
|
|
|
goto end;
|
|
|
|
|
|
|
|
iommu->gcmd &= ~DMA_GCMD_IRE;
|
|
|
|
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
|
|
|
|
|
|
|
|
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
|
|
|
|
readl, !(sts & DMA_GSTS_IRES), sts);
|
|
|
|
|
|
|
|
end:
|
2011-07-19 22:19:51 +08:00
|
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
|
2009-03-17 08:04:56 +08:00
|
|
|
}
|
|
|
|
|
2011-08-24 08:05:18 +08:00
|
|
|
static int __init dmar_x2apic_optout(void)
|
|
|
|
{
|
|
|
|
struct acpi_table_dmar *dmar;
|
|
|
|
dmar = (struct acpi_table_dmar *)dmar_tbl;
|
|
|
|
if (!dmar || no_x2apic_optout)
|
|
|
|
return 0;
|
|
|
|
return dmar->flags & DMAR_X2APIC_OPT_OUT;
|
|
|
|
}
|
|
|
|
|
2015-01-07 15:31:29 +08:00
|
|
|
static void __init intel_cleanup_irq_remapping(void)
|
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
|
|
|
|
for_each_iommu(iommu, drhd) {
|
|
|
|
if (ecap_ir_support(iommu->ecap)) {
|
|
|
|
iommu_disable_irq_remapping(iommu);
|
|
|
|
intel_teardown_irq_remapping(iommu);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (x2apic_supported())
|
2015-06-12 15:57:06 +08:00
|
|
|
pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
|
2015-01-07 15:31:29 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int __init intel_prepare_irq_remapping(void)
|
2008-07-11 02:16:43 +08:00
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
2014-01-06 14:18:18 +08:00
|
|
|
struct intel_iommu *iommu;
|
2015-06-12 20:15:49 +08:00
|
|
|
int eim = 0;
|
2008-07-11 02:16:43 +08:00
|
|
|
|
2015-01-07 15:31:35 +08:00
|
|
|
if (irq_remap_broken) {
|
2015-06-12 15:57:06 +08:00
|
|
|
pr_warn("This system BIOS has enabled interrupt remapping\n"
|
2015-01-07 15:31:35 +08:00
|
|
|
"on a chipset that contains an erratum making that\n"
|
|
|
|
"feature unstable. To maintain system stability\n"
|
|
|
|
"interrupt remapping is being disabled. Please\n"
|
|
|
|
"contact your BIOS vendor for an update\n");
|
|
|
|
add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2015-01-07 15:31:29 +08:00
|
|
|
if (dmar_table_init() < 0)
|
2015-01-07 15:31:35 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
if (!dmar_ir_support())
|
|
|
|
return -ENODEV;
|
2013-02-02 06:57:43 +08:00
|
|
|
|
2015-11-02 18:57:31 +08:00
|
|
|
if (parse_ioapics_under_ir()) {
|
2015-06-12 15:57:06 +08:00
|
|
|
pr_info("Not enabling interrupt remapping\n");
|
2013-02-02 06:57:43 +08:00
|
|
|
goto error;
|
2009-09-07 22:58:07 +08:00
|
|
|
}
|
|
|
|
|
2015-01-07 15:31:36 +08:00
|
|
|
/* First make sure all IOMMUs support IRQ remapping */
|
2015-01-07 15:31:35 +08:00
|
|
|
for_each_iommu(iommu, drhd)
|
2015-01-07 15:31:36 +08:00
|
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
|
|
goto error;
|
|
|
|
|
2015-06-12 20:15:49 +08:00
|
|
|
/* Detect remapping mode: lapic or x2apic */
|
|
|
|
if (x2apic_supported()) {
|
|
|
|
eim = !dmar_x2apic_optout();
|
|
|
|
if (!eim) {
|
|
|
|
pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
|
|
|
|
pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_iommu(iommu, drhd) {
|
|
|
|
if (eim && !ecap_eim_support(iommu->ecap)) {
|
|
|
|
pr_info("%s does not support EIM\n", iommu->name);
|
|
|
|
eim = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
eim_mode = eim;
|
|
|
|
if (eim)
|
|
|
|
pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
|
|
|
|
|
2015-06-12 20:23:56 +08:00
|
|
|
/* Do the initializations early */
|
|
|
|
for_each_iommu(iommu, drhd) {
|
|
|
|
if (intel_setup_irq_remapping(iommu)) {
|
|
|
|
pr_err("Failed to setup irq remapping for %s\n",
|
|
|
|
iommu->name);
|
2015-01-07 15:31:29 +08:00
|
|
|
goto error;
|
2015-06-12 20:23:56 +08:00
|
|
|
}
|
|
|
|
}
|
2015-01-07 15:31:36 +08:00
|
|
|
|
2015-01-07 15:31:29 +08:00
|
|
|
return 0;
|
2015-01-07 15:31:35 +08:00
|
|
|
|
2015-01-07 15:31:29 +08:00
|
|
|
error:
|
|
|
|
intel_cleanup_irq_remapping();
|
2015-01-07 15:31:35 +08:00
|
|
|
return -ENODEV;
|
2015-01-07 15:31:29 +08:00
|
|
|
}
|
|
|
|
|
2015-06-09 13:20:35 +08:00
|
|
|
/*
|
|
|
|
* Set Posted-Interrupts capability.
|
|
|
|
*/
|
|
|
|
static inline void set_irq_posting_cap(void)
|
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
|
|
|
|
if (!disable_irq_post) {
|
2015-10-15 10:19:11 +08:00
|
|
|
/*
|
|
|
|
* If IRTE is in posted format, the 'pda' field goes across the
|
|
|
|
* 64-bit boundary, we need use cmpxchg16b to atomically update
|
|
|
|
* it. We only expose posted-interrupt when X86_FEATURE_CX16
|
|
|
|
* is supported. Actually, hardware platforms supporting PI
|
|
|
|
* should have X86_FEATURE_CX16 support, this has been confirmed
|
|
|
|
* with Intel hardware guys.
|
|
|
|
*/
|
2015-12-07 17:39:41 +08:00
|
|
|
if (boot_cpu_has(X86_FEATURE_CX16))
|
2015-10-15 10:19:11 +08:00
|
|
|
intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
|
2015-06-09 13:20:35 +08:00
|
|
|
|
|
|
|
for_each_iommu(iommu, drhd)
|
|
|
|
if (!cap_pi_support(iommu->cap)) {
|
|
|
|
intel_irq_remap_ops.capability &=
|
|
|
|
~(1 << IRQ_POSTING_CAP);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-01-07 15:31:29 +08:00
|
|
|
static int __init intel_enable_irq_remapping(void)
|
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu;
|
2015-02-06 17:59:53 +08:00
|
|
|
bool setup = false;
|
2008-07-11 02:16:43 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup Interrupt-remapping for all the DRHD's now.
|
|
|
|
*/
|
2014-01-06 14:18:18 +08:00
|
|
|
for_each_iommu(iommu, drhd) {
|
2015-06-12 21:15:34 +08:00
|
|
|
if (!ir_pre_enabled(iommu))
|
|
|
|
iommu_enable_irq_remapping(iommu);
|
2015-02-06 17:59:53 +08:00
|
|
|
setup = true;
|
2008-07-11 02:16:43 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!setup)
|
|
|
|
goto error;
|
|
|
|
|
2012-03-31 02:47:07 +08:00
|
|
|
irq_remapping_enabled = 1;
|
2012-09-26 18:44:36 +08:00
|
|
|
|
2015-06-09 13:20:35 +08:00
|
|
|
set_irq_posting_cap();
|
|
|
|
|
2015-06-12 20:15:49 +08:00
|
|
|
pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
|
2008-07-11 02:16:43 +08:00
|
|
|
|
2015-06-12 20:15:49 +08:00
|
|
|
return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
|
2008-07-11 02:16:43 +08:00
|
|
|
|
|
|
|
error:
|
2015-01-07 15:31:29 +08:00
|
|
|
intel_cleanup_irq_remapping();
|
2008-07-11 02:16:43 +08:00
|
|
|
return -1;
|
|
|
|
}
|
2008-07-11 02:16:40 +08:00
|
|
|
|
2014-11-09 22:48:00 +08:00
|
|
|
static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
|
|
|
|
struct intel_iommu *iommu,
|
|
|
|
struct acpi_dmar_hardware_unit *drhd)
|
2009-08-05 03:07:08 +08:00
|
|
|
{
|
|
|
|
struct acpi_dmar_pci_path *path;
|
|
|
|
u8 bus;
|
2014-11-09 22:48:00 +08:00
|
|
|
int count, free = -1;
|
2009-08-05 03:07:08 +08:00
|
|
|
|
|
|
|
bus = scope->bus;
|
|
|
|
path = (struct acpi_dmar_pci_path *)(scope + 1);
|
|
|
|
count = (scope->length - sizeof(struct acpi_dmar_device_scope))
|
|
|
|
/ sizeof(struct acpi_dmar_pci_path);
|
|
|
|
|
|
|
|
while (--count > 0) {
|
|
|
|
/*
|
|
|
|
* Access PCI directly due to the PCI
|
|
|
|
* subsystem isn't initialized yet.
|
|
|
|
*/
|
2013-10-31 09:30:22 +08:00
|
|
|
bus = read_pci_config_byte(bus, path->device, path->function,
|
2009-08-05 03:07:08 +08:00
|
|
|
PCI_SECONDARY_BUS);
|
|
|
|
path++;
|
|
|
|
}
|
2014-11-09 22:48:00 +08:00
|
|
|
|
|
|
|
for (count = 0; count < MAX_HPET_TBS; count++) {
|
|
|
|
if (ir_hpet[count].iommu == iommu &&
|
|
|
|
ir_hpet[count].id == scope->enumeration_id)
|
|
|
|
return 0;
|
|
|
|
else if (ir_hpet[count].iommu == NULL && free == -1)
|
|
|
|
free = count;
|
|
|
|
}
|
|
|
|
if (free == -1) {
|
|
|
|
pr_warn("Exceeded Max HPET blocks\n");
|
|
|
|
return -ENOSPC;
|
|
|
|
}
|
|
|
|
|
|
|
|
ir_hpet[free].iommu = iommu;
|
|
|
|
ir_hpet[free].id = scope->enumeration_id;
|
|
|
|
ir_hpet[free].bus = bus;
|
|
|
|
ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
|
|
|
|
pr_info("HPET id %d under DRHD base 0x%Lx\n",
|
|
|
|
scope->enumeration_id, drhd->address);
|
|
|
|
|
|
|
|
return 0;
|
2009-08-05 03:07:08 +08:00
|
|
|
}
|
|
|
|
|
2014-11-09 22:48:00 +08:00
|
|
|
static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
|
|
|
|
struct intel_iommu *iommu,
|
|
|
|
struct acpi_dmar_hardware_unit *drhd)
|
2009-05-23 00:41:15 +08:00
|
|
|
{
|
|
|
|
struct acpi_dmar_pci_path *path;
|
|
|
|
u8 bus;
|
2014-11-09 22:48:00 +08:00
|
|
|
int count, free = -1;
|
2009-05-23 00:41:15 +08:00
|
|
|
|
|
|
|
bus = scope->bus;
|
|
|
|
path = (struct acpi_dmar_pci_path *)(scope + 1);
|
|
|
|
count = (scope->length - sizeof(struct acpi_dmar_device_scope))
|
|
|
|
/ sizeof(struct acpi_dmar_pci_path);
|
|
|
|
|
|
|
|
while (--count > 0) {
|
|
|
|
/*
|
|
|
|
* Access PCI directly due to the PCI
|
|
|
|
* subsystem isn't initialized yet.
|
|
|
|
*/
|
2013-10-31 09:30:22 +08:00
|
|
|
bus = read_pci_config_byte(bus, path->device, path->function,
|
2009-05-23 00:41:15 +08:00
|
|
|
PCI_SECONDARY_BUS);
|
|
|
|
path++;
|
|
|
|
}
|
|
|
|
|
2014-11-09 22:48:00 +08:00
|
|
|
for (count = 0; count < MAX_IO_APICS; count++) {
|
|
|
|
if (ir_ioapic[count].iommu == iommu &&
|
|
|
|
ir_ioapic[count].id == scope->enumeration_id)
|
|
|
|
return 0;
|
|
|
|
else if (ir_ioapic[count].iommu == NULL && free == -1)
|
|
|
|
free = count;
|
|
|
|
}
|
|
|
|
if (free == -1) {
|
|
|
|
pr_warn("Exceeded Max IO APICS\n");
|
|
|
|
return -ENOSPC;
|
|
|
|
}
|
|
|
|
|
|
|
|
ir_ioapic[free].bus = bus;
|
|
|
|
ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
|
|
|
|
ir_ioapic[free].iommu = iommu;
|
|
|
|
ir_ioapic[free].id = scope->enumeration_id;
|
|
|
|
pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
|
|
|
|
scope->enumeration_id, drhd->address, iommu->seq_id);
|
|
|
|
|
|
|
|
return 0;
|
2009-05-23 00:41:15 +08:00
|
|
|
}
|
|
|
|
|
2009-08-05 03:07:08 +08:00
|
|
|
static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
|
|
|
|
struct intel_iommu *iommu)
|
2008-07-11 02:16:40 +08:00
|
|
|
{
|
2014-11-09 22:48:00 +08:00
|
|
|
int ret = 0;
|
2008-07-11 02:16:40 +08:00
|
|
|
struct acpi_dmar_hardware_unit *drhd;
|
|
|
|
struct acpi_dmar_device_scope *scope;
|
|
|
|
void *start, *end;
|
|
|
|
|
|
|
|
drhd = (struct acpi_dmar_hardware_unit *)header;
|
|
|
|
start = (void *)(drhd + 1);
|
|
|
|
end = ((void *)drhd) + header->length;
|
|
|
|
|
2014-11-09 22:48:00 +08:00
|
|
|
while (start < end && ret == 0) {
|
2008-07-11 02:16:40 +08:00
|
|
|
scope = start;
|
2014-11-09 22:48:00 +08:00
|
|
|
if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
|
|
|
|
ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
|
|
|
|
else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
|
|
|
|
ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
|
|
|
|
start += scope->length;
|
|
|
|
}
|
2008-07-11 02:16:40 +08:00
|
|
|
|
2014-11-09 22:48:00 +08:00
|
|
|
return ret;
|
|
|
|
}
|
2009-08-05 03:07:08 +08:00
|
|
|
|
2014-11-09 22:48:00 +08:00
|
|
|
static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
int i;
|
2009-08-05 03:07:08 +08:00
|
|
|
|
2014-11-09 22:48:00 +08:00
|
|
|
for (i = 0; i < MAX_HPET_TBS; i++)
|
|
|
|
if (ir_hpet[i].iommu == iommu)
|
|
|
|
ir_hpet[i].iommu = NULL;
|
2008-07-11 02:16:40 +08:00
|
|
|
|
2014-11-09 22:48:00 +08:00
|
|
|
for (i = 0; i < MAX_IO_APICS; i++)
|
|
|
|
if (ir_ioapic[i].iommu == iommu)
|
|
|
|
ir_ioapic[i].iommu = NULL;
|
2008-07-11 02:16:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Finds the assocaition between IOAPIC's and its Interrupt-remapping
|
|
|
|
* hardware unit.
|
|
|
|
*/
|
2014-01-06 14:18:16 +08:00
|
|
|
static int __init parse_ioapics_under_ir(void)
|
2008-07-11 02:16:40 +08:00
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
2014-01-06 14:18:18 +08:00
|
|
|
struct intel_iommu *iommu;
|
2015-02-06 17:59:53 +08:00
|
|
|
bool ir_supported = false;
|
2012-08-08 21:27:03 +08:00
|
|
|
int ioapic_idx;
|
2008-07-11 02:16:40 +08:00
|
|
|
|
2015-10-23 17:57:13 +08:00
|
|
|
for_each_iommu(iommu, drhd) {
|
|
|
|
int ret;
|
2008-07-11 02:16:40 +08:00
|
|
|
|
2015-10-23 17:57:13 +08:00
|
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ir_supported = true;
|
|
|
|
}
|
2008-07-11 02:16:40 +08:00
|
|
|
|
2012-08-08 21:27:03 +08:00
|
|
|
if (!ir_supported)
|
2015-10-22 14:00:51 +08:00
|
|
|
return -ENODEV;
|
2012-08-08 21:27:03 +08:00
|
|
|
|
|
|
|
for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
|
|
|
|
int ioapic_id = mpc_ioapic_id(ioapic_idx);
|
|
|
|
if (!map_ioapic_to_ir(ioapic_id)) {
|
|
|
|
pr_err(FW_BUG "ioapic %d has no mapping iommu, "
|
|
|
|
"interrupt remapping will be disabled\n",
|
|
|
|
ioapic_id);
|
|
|
|
return -1;
|
|
|
|
}
|
2008-07-11 02:16:40 +08:00
|
|
|
}
|
|
|
|
|
2015-10-22 14:00:51 +08:00
|
|
|
return 0;
|
2008-07-11 02:16:40 +08:00
|
|
|
}
|
2009-03-28 05:22:44 +08:00
|
|
|
|
2013-12-18 14:34:27 +08:00
|
|
|
static int __init ir_dev_scope_init(void)
|
2011-08-24 08:05:19 +08:00
|
|
|
{
|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 14:07:33 +08:00
|
|
|
int ret;
|
|
|
|
|
2012-03-31 02:47:07 +08:00
|
|
|
if (!irq_remapping_enabled)
|
2011-08-24 08:05:19 +08:00
|
|
|
return 0;
|
|
|
|
|
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 14:07:33 +08:00
|
|
|
down_write(&dmar_global_lock);
|
|
|
|
ret = dmar_dev_scope_init();
|
|
|
|
up_write(&dmar_global_lock);
|
|
|
|
|
|
|
|
return ret;
|
2011-08-24 08:05:19 +08:00
|
|
|
}
|
|
|
|
rootfs_initcall(ir_dev_scope_init);
|
|
|
|
|
2012-03-31 02:47:07 +08:00
|
|
|
static void disable_irq_remapping(void)
|
2009-03-28 05:22:44 +08:00
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
struct intel_iommu *iommu = NULL;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable Interrupt-remapping for all the DRHD's now.
|
|
|
|
*/
|
|
|
|
for_each_iommu(iommu, drhd) {
|
|
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
|
|
continue;
|
|
|
|
|
2012-03-31 02:47:07 +08:00
|
|
|
iommu_disable_irq_remapping(iommu);
|
2009-03-28 05:22:44 +08:00
|
|
|
}
|
2015-06-09 13:20:35 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear Posted-Interrupts capability.
|
|
|
|
*/
|
|
|
|
if (!disable_irq_post)
|
|
|
|
intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
|
2009-03-28 05:22:44 +08:00
|
|
|
}
|
|
|
|
|
2012-03-31 02:47:07 +08:00
|
|
|
static int reenable_irq_remapping(int eim)
|
2009-03-28 05:22:44 +08:00
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
2015-02-06 17:59:53 +08:00
|
|
|
bool setup = false;
|
2009-03-28 05:22:44 +08:00
|
|
|
struct intel_iommu *iommu = NULL;
|
|
|
|
|
|
|
|
for_each_iommu(iommu, drhd)
|
|
|
|
if (iommu->qi)
|
|
|
|
dmar_reenable_qi(iommu);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup Interrupt-remapping for all the DRHD's now.
|
|
|
|
*/
|
|
|
|
for_each_iommu(iommu, drhd) {
|
|
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Set up interrupt remapping for iommu.*/
|
2012-03-31 02:47:07 +08:00
|
|
|
iommu_set_irq_remapping(iommu, eim);
|
2015-06-12 20:35:54 +08:00
|
|
|
iommu_enable_irq_remapping(iommu);
|
2015-02-06 17:59:53 +08:00
|
|
|
setup = true;
|
2009-03-28 05:22:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!setup)
|
|
|
|
goto error;
|
|
|
|
|
2015-06-09 13:20:35 +08:00
|
|
|
set_irq_posting_cap();
|
|
|
|
|
2009-03-28 05:22:44 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
error:
|
|
|
|
/*
|
|
|
|
* handle error condition gracefully here!
|
|
|
|
*/
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2015-04-14 10:29:47 +08:00
|
|
|
static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
|
2012-03-31 02:47:02 +08:00
|
|
|
{
|
|
|
|
memset(irte, 0, sizeof(*irte));
|
|
|
|
|
|
|
|
irte->present = 1;
|
|
|
|
irte->dst_mode = apic->irq_dest_mode;
|
|
|
|
/*
|
|
|
|
* Trigger mode in the IRTE will always be edge, and for IO-APIC, the
|
|
|
|
* actual level or edge trigger will be setup in the IO-APIC
|
|
|
|
* RTE. This will help simplify level triggered irq migration.
|
|
|
|
* For more details, see the comments (in io_apic.c) explainig IO-APIC
|
|
|
|
* irq migration in the presence of interrupt-remapping.
|
|
|
|
*/
|
|
|
|
irte->trigger_mode = 0;
|
|
|
|
irte->dlvry_mode = apic->irq_delivery_mode;
|
|
|
|
irte->vector = vector;
|
|
|
|
irte->dest_id = IRTE_DEST(dest);
|
|
|
|
irte->redir_hint = 1;
|
|
|
|
}
|
|
|
|
|
2015-04-13 14:11:32 +08:00
|
|
|
static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
|
|
|
|
{
|
|
|
|
struct intel_iommu *iommu = NULL;
|
|
|
|
|
|
|
|
if (!info)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
switch (info->type) {
|
|
|
|
case X86_IRQ_ALLOC_TYPE_IOAPIC:
|
|
|
|
iommu = map_ioapic_to_ir(info->ioapic_id);
|
|
|
|
break;
|
|
|
|
case X86_IRQ_ALLOC_TYPE_HPET:
|
|
|
|
iommu = map_hpet_to_ir(info->hpet_id);
|
|
|
|
break;
|
|
|
|
case X86_IRQ_ALLOC_TYPE_MSI:
|
|
|
|
case X86_IRQ_ALLOC_TYPE_MSIX:
|
|
|
|
iommu = map_dev_to_ir(info->msi_dev);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG_ON(1);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return iommu ? iommu->ir_domain : NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
|
|
|
|
{
|
|
|
|
struct intel_iommu *iommu;
|
|
|
|
|
|
|
|
if (!info)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
switch (info->type) {
|
|
|
|
case X86_IRQ_ALLOC_TYPE_MSI:
|
|
|
|
case X86_IRQ_ALLOC_TYPE_MSIX:
|
|
|
|
iommu = map_dev_to_ir(info->msi_dev);
|
|
|
|
if (iommu)
|
|
|
|
return iommu->ir_msi_domain;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2012-03-31 02:47:00 +08:00
|
|
|
struct irq_remap_ops intel_irq_remap_ops = {
|
2015-01-07 15:31:29 +08:00
|
|
|
.prepare = intel_prepare_irq_remapping,
|
2012-03-31 02:47:07 +08:00
|
|
|
.enable = intel_enable_irq_remapping,
|
|
|
|
.disable = disable_irq_remapping,
|
|
|
|
.reenable = reenable_irq_remapping,
|
2012-03-31 02:47:01 +08:00
|
|
|
.enable_faulting = enable_drhd_fault_handling,
|
2015-04-13 14:11:32 +08:00
|
|
|
.get_ir_irq_domain = intel_get_ir_irq_domain,
|
|
|
|
.get_irq_domain = intel_get_irq_domain,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Migrate the IO-APIC irq in the presence of intr-remapping.
|
|
|
|
*
|
|
|
|
* For both level and edge triggered, irq migration is a simple atomic
|
|
|
|
* update(of vector and cpu destination) of IRTE and flush the hardware cache.
|
|
|
|
*
|
|
|
|
* For level triggered, we eliminate the io-apic RTE modification (with the
|
|
|
|
* updated vector information), by using a virtual vector (io-apic pin number).
|
|
|
|
* Real vector that is used for interrupting cpu will be coming from
|
|
|
|
* the interrupt-remapping table entry.
|
|
|
|
*
|
|
|
|
* As the migration is a simple atomic update of IRTE, the same mechanism
|
|
|
|
* is used to migrate MSI irq's in the presence of interrupt-remapping.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
|
|
|
|
bool force)
|
|
|
|
{
|
|
|
|
struct intel_ir_data *ir_data = data->chip_data;
|
|
|
|
struct irte *irte = &ir_data->irte_entry;
|
|
|
|
struct irq_cfg *cfg = irqd_cfg(data);
|
|
|
|
struct irq_data *parent = data->parent_data;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = parent->chip->irq_set_affinity(parent, mask, force);
|
|
|
|
if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Atomically updates the IRTE with the new destination, vector
|
|
|
|
* and flushes the interrupt entry cache.
|
|
|
|
*/
|
|
|
|
irte->vector = cfg->vector;
|
|
|
|
irte->dest_id = IRTE_DEST(cfg->dest_apicid);
|
2015-06-09 13:20:33 +08:00
|
|
|
|
|
|
|
/* Update the hardware only if the interrupt is in remapped mode. */
|
|
|
|
if (ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
|
|
|
|
modify_irte(&ir_data->irq_2_iommu, irte);
|
2015-04-13 14:11:32 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* After this point, all the interrupts will start arriving
|
|
|
|
* at the new destination. So, time to cleanup the previous
|
|
|
|
* vector allocation.
|
|
|
|
*/
|
2015-04-14 10:30:02 +08:00
|
|
|
send_cleanup_vector(cfg);
|
2015-04-13 14:11:32 +08:00
|
|
|
|
|
|
|
return IRQ_SET_MASK_OK_DONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
|
|
|
|
struct msi_msg *msg)
|
|
|
|
{
|
|
|
|
struct intel_ir_data *ir_data = irq_data->chip_data;
|
|
|
|
|
|
|
|
*msg = ir_data->msi_entry;
|
|
|
|
}
|
|
|
|
|
2015-06-09 13:20:31 +08:00
|
|
|
static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
|
|
|
|
{
|
|
|
|
struct intel_ir_data *ir_data = data->chip_data;
|
|
|
|
struct vcpu_data *vcpu_pi_info = info;
|
|
|
|
|
|
|
|
/* stop posting interrupts, back to remapping mode */
|
|
|
|
if (!vcpu_pi_info) {
|
|
|
|
modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
|
|
|
|
} else {
|
|
|
|
struct irte irte_pi;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We are not caching the posted interrupt entry. We
|
|
|
|
* copy the data from the remapped entry and modify
|
|
|
|
* the fields which are relevant for posted mode. The
|
|
|
|
* cached remapped entry is used for switching back to
|
|
|
|
* remapped mode.
|
|
|
|
*/
|
|
|
|
memset(&irte_pi, 0, sizeof(irte_pi));
|
|
|
|
dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
|
|
|
|
|
|
|
|
/* Update the posted mode fields */
|
|
|
|
irte_pi.p_pst = 1;
|
|
|
|
irte_pi.p_urgent = 0;
|
|
|
|
irte_pi.p_vector = vcpu_pi_info->vector;
|
|
|
|
irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
|
|
|
|
(32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
|
|
|
|
irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
|
|
|
|
~(-1UL << PDA_HIGH_BIT);
|
|
|
|
|
|
|
|
modify_irte(&ir_data->irq_2_iommu, &irte_pi);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-04-13 14:11:32 +08:00
|
|
|
static struct irq_chip intel_ir_chip = {
|
|
|
|
.irq_ack = ir_ack_apic_edge,
|
|
|
|
.irq_set_affinity = intel_ir_set_affinity,
|
|
|
|
.irq_compose_msi_msg = intel_ir_compose_msi_msg,
|
2015-06-09 13:20:31 +08:00
|
|
|
.irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
|
2015-04-13 14:11:32 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
|
|
|
|
struct irq_cfg *irq_cfg,
|
|
|
|
struct irq_alloc_info *info,
|
|
|
|
int index, int sub_handle)
|
|
|
|
{
|
|
|
|
struct IR_IO_APIC_route_entry *entry;
|
|
|
|
struct irte *irte = &data->irte_entry;
|
|
|
|
struct msi_msg *msg = &data->msi_entry;
|
|
|
|
|
|
|
|
prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
|
|
|
|
switch (info->type) {
|
|
|
|
case X86_IRQ_ALLOC_TYPE_IOAPIC:
|
|
|
|
/* Set source-id of interrupt request */
|
|
|
|
set_ioapic_sid(irte, info->ioapic_id);
|
|
|
|
apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
|
|
|
|
info->ioapic_id, irte->present, irte->fpd,
|
|
|
|
irte->dst_mode, irte->redir_hint,
|
|
|
|
irte->trigger_mode, irte->dlvry_mode,
|
|
|
|
irte->avail, irte->vector, irte->dest_id,
|
|
|
|
irte->sid, irte->sq, irte->svt);
|
|
|
|
|
|
|
|
entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
|
|
|
|
info->ioapic_entry = NULL;
|
|
|
|
memset(entry, 0, sizeof(*entry));
|
|
|
|
entry->index2 = (index >> 15) & 0x1;
|
|
|
|
entry->zero = 0;
|
|
|
|
entry->format = 1;
|
|
|
|
entry->index = (index & 0x7fff);
|
|
|
|
/*
|
|
|
|
* IO-APIC RTE will be configured with virtual vector.
|
|
|
|
* irq handler will do the explicit EOI to the io-apic.
|
|
|
|
*/
|
|
|
|
entry->vector = info->ioapic_pin;
|
|
|
|
entry->mask = 0; /* enable IRQ */
|
|
|
|
entry->trigger = info->ioapic_trigger;
|
|
|
|
entry->polarity = info->ioapic_polarity;
|
|
|
|
if (info->ioapic_trigger)
|
|
|
|
entry->mask = 1; /* Mask level triggered irqs. */
|
|
|
|
break;
|
|
|
|
|
|
|
|
case X86_IRQ_ALLOC_TYPE_HPET:
|
|
|
|
case X86_IRQ_ALLOC_TYPE_MSI:
|
|
|
|
case X86_IRQ_ALLOC_TYPE_MSIX:
|
|
|
|
if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
|
|
|
|
set_hpet_sid(irte, info->hpet_id);
|
|
|
|
else
|
|
|
|
set_msi_sid(irte, info->msi_dev);
|
|
|
|
|
|
|
|
msg->address_hi = MSI_ADDR_BASE_HI;
|
|
|
|
msg->data = sub_handle;
|
|
|
|
msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
|
|
|
|
MSI_ADDR_IR_SHV |
|
|
|
|
MSI_ADDR_IR_INDEX1(index) |
|
|
|
|
MSI_ADDR_IR_INDEX2(index);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
BUG_ON(1);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_free_irq_resources(struct irq_domain *domain,
|
|
|
|
unsigned int virq, unsigned int nr_irqs)
|
|
|
|
{
|
|
|
|
struct irq_data *irq_data;
|
|
|
|
struct intel_ir_data *data;
|
|
|
|
struct irq_2_iommu *irq_iommu;
|
|
|
|
unsigned long flags;
|
|
|
|
int i;
|
|
|
|
for (i = 0; i < nr_irqs; i++) {
|
|
|
|
irq_data = irq_domain_get_irq_data(domain, virq + i);
|
|
|
|
if (irq_data && irq_data->chip_data) {
|
|
|
|
data = irq_data->chip_data;
|
|
|
|
irq_iommu = &data->irq_2_iommu;
|
|
|
|
raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
|
|
|
|
clear_entries(irq_iommu);
|
|
|
|
raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
|
|
|
|
irq_domain_reset_irq_data(irq_data);
|
|
|
|
kfree(data);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_irq_remapping_alloc(struct irq_domain *domain,
|
|
|
|
unsigned int virq, unsigned int nr_irqs,
|
|
|
|
void *arg)
|
|
|
|
{
|
|
|
|
struct intel_iommu *iommu = domain->host_data;
|
|
|
|
struct irq_alloc_info *info = arg;
|
2015-05-04 10:47:40 +08:00
|
|
|
struct intel_ir_data *data, *ird;
|
2015-04-13 14:11:32 +08:00
|
|
|
struct irq_data *irq_data;
|
|
|
|
struct irq_cfg *irq_cfg;
|
|
|
|
int i, ret, index;
|
|
|
|
|
|
|
|
if (!info || !iommu)
|
|
|
|
return -EINVAL;
|
|
|
|
if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
|
|
|
|
info->type != X86_IRQ_ALLOC_TYPE_MSIX)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* With IRQ remapping enabled, don't need contiguous CPU vectors
|
|
|
|
* to support multiple MSI interrupts.
|
|
|
|
*/
|
|
|
|
if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
|
|
|
|
info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
|
|
|
|
|
|
|
|
ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = -ENOMEM;
|
|
|
|
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
|
|
|
if (!data)
|
|
|
|
goto out_free_parent;
|
|
|
|
|
|
|
|
down_read(&dmar_global_lock);
|
|
|
|
index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs);
|
|
|
|
up_read(&dmar_global_lock);
|
|
|
|
if (index < 0) {
|
|
|
|
pr_warn("Failed to allocate IRTE\n");
|
|
|
|
kfree(data);
|
|
|
|
goto out_free_parent;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < nr_irqs; i++) {
|
|
|
|
irq_data = irq_domain_get_irq_data(domain, virq + i);
|
|
|
|
irq_cfg = irqd_cfg(irq_data);
|
|
|
|
if (!irq_data || !irq_cfg) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out_free_data;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i > 0) {
|
2015-05-04 10:47:40 +08:00
|
|
|
ird = kzalloc(sizeof(*ird), GFP_KERNEL);
|
|
|
|
if (!ird)
|
2015-04-13 14:11:32 +08:00
|
|
|
goto out_free_data;
|
2015-05-04 10:47:40 +08:00
|
|
|
/* Initialize the common data */
|
|
|
|
ird->irq_2_iommu = data->irq_2_iommu;
|
|
|
|
ird->irq_2_iommu.sub_handle = i;
|
|
|
|
} else {
|
|
|
|
ird = data;
|
2015-04-13 14:11:32 +08:00
|
|
|
}
|
2015-05-04 10:47:40 +08:00
|
|
|
|
2015-04-13 14:11:32 +08:00
|
|
|
irq_data->hwirq = (index << 16) + i;
|
2015-05-04 10:47:40 +08:00
|
|
|
irq_data->chip_data = ird;
|
2015-04-13 14:11:32 +08:00
|
|
|
irq_data->chip = &intel_ir_chip;
|
2015-05-04 10:47:40 +08:00
|
|
|
intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
|
2015-04-13 14:11:32 +08:00
|
|
|
irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_free_data:
|
|
|
|
intel_free_irq_resources(domain, virq, i);
|
|
|
|
out_free_parent:
|
|
|
|
irq_domain_free_irqs_common(domain, virq, nr_irqs);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_irq_remapping_free(struct irq_domain *domain,
|
|
|
|
unsigned int virq, unsigned int nr_irqs)
|
|
|
|
{
|
|
|
|
intel_free_irq_resources(domain, virq, nr_irqs);
|
|
|
|
irq_domain_free_irqs_common(domain, virq, nr_irqs);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_irq_remapping_activate(struct irq_domain *domain,
|
|
|
|
struct irq_data *irq_data)
|
|
|
|
{
|
|
|
|
struct intel_ir_data *data = irq_data->chip_data;
|
|
|
|
|
|
|
|
modify_irte(&data->irq_2_iommu, &data->irte_entry);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_irq_remapping_deactivate(struct irq_domain *domain,
|
|
|
|
struct irq_data *irq_data)
|
|
|
|
{
|
|
|
|
struct intel_ir_data *data = irq_data->chip_data;
|
|
|
|
struct irte entry;
|
|
|
|
|
|
|
|
memset(&entry, 0, sizeof(entry));
|
|
|
|
modify_irte(&data->irq_2_iommu, &entry);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct irq_domain_ops intel_ir_domain_ops = {
|
|
|
|
.alloc = intel_irq_remapping_alloc,
|
|
|
|
.free = intel_irq_remapping_free,
|
|
|
|
.activate = intel_irq_remapping_activate,
|
|
|
|
.deactivate = intel_irq_remapping_deactivate,
|
2012-03-31 02:47:00 +08:00
|
|
|
};
|
2014-11-09 22:47:58 +08:00
|
|
|
|
2014-11-09 22:48:00 +08:00
|
|
|
/*
|
|
|
|
* Support of Interrupt Remapping Unit Hotplug
|
|
|
|
*/
|
|
|
|
static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int eim = x2apic_enabled();
|
|
|
|
|
|
|
|
if (eim && !ecap_eim_support(iommu->ecap)) {
|
|
|
|
pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
|
|
|
|
iommu->reg_phys, iommu->ecap);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
|
|
|
|
pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
|
|
|
|
iommu->reg_phys);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TODO: check all IOAPICs are covered by IOMMU */
|
|
|
|
|
|
|
|
/* Setup Interrupt-remapping now. */
|
|
|
|
ret = intel_setup_irq_remapping(iommu);
|
|
|
|
if (ret) {
|
2015-06-12 20:23:56 +08:00
|
|
|
pr_err("Failed to setup irq remapping for %s\n",
|
|
|
|
iommu->name);
|
2014-11-09 22:48:00 +08:00
|
|
|
intel_teardown_irq_remapping(iommu);
|
|
|
|
ir_remove_ioapic_hpet_scope(iommu);
|
2015-06-12 20:23:56 +08:00
|
|
|
} else {
|
2015-06-12 20:35:54 +08:00
|
|
|
iommu_enable_irq_remapping(iommu);
|
2014-11-09 22:48:00 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-11-09 22:47:58 +08:00
|
|
|
int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
|
|
|
|
{
|
2014-11-09 22:48:00 +08:00
|
|
|
int ret = 0;
|
|
|
|
struct intel_iommu *iommu = dmaru->iommu;
|
|
|
|
|
|
|
|
if (!irq_remapping_enabled)
|
|
|
|
return 0;
|
|
|
|
if (iommu == NULL)
|
|
|
|
return -EINVAL;
|
|
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
|
|
return 0;
|
2015-06-09 13:20:37 +08:00
|
|
|
if (irq_remapping_cap(IRQ_POSTING_CAP) &&
|
|
|
|
!cap_pi_support(iommu->cap))
|
|
|
|
return -EBUSY;
|
2014-11-09 22:48:00 +08:00
|
|
|
|
|
|
|
if (insert) {
|
|
|
|
if (!iommu->ir_table)
|
|
|
|
ret = dmar_ir_add(dmaru, iommu);
|
|
|
|
} else {
|
|
|
|
if (iommu->ir_table) {
|
|
|
|
if (!bitmap_empty(iommu->ir_table->bitmap,
|
|
|
|
INTR_REMAP_TABLE_ENTRIES)) {
|
|
|
|
ret = -EBUSY;
|
|
|
|
} else {
|
|
|
|
iommu_disable_irq_remapping(iommu);
|
|
|
|
intel_teardown_irq_remapping(iommu);
|
|
|
|
ir_remove_ioapic_hpet_scope(iommu);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
2014-11-09 22:47:58 +08:00
|
|
|
}
|