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linux/drivers/clk/rockchip/clk.c

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clk: rockchip: add basic infrastructure for clock branches This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:58:39 +08:00
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* based on
*
* samsung/clk.c
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Copyright (c) 2013 Linaro Ltd.
* Author: Thomas Abraham <thomas.ab@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
clk: rockchip: add clock type for pll clocks and pll used on rk3066 All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:59:10 +08:00
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
clk: rockchip: add restart handler Add infrastructure to write the correct value to the restart register and register the restart notifier for both rk3188 (including rk3066) and rk3288. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2014-08-20 08:45:38 +08:00
#include <linux/reboot.h>
clk: rockchip: add basic infrastructure for clock branches This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:58:39 +08:00
#include "clk.h"
/**
* Register a clock branch.
* Most clock branches have a form like
*
* src1 --|--\
* |M |--[GATE]-[DIV]-
* src2 --|--/
*
* sometimes without one of those components.
*/
clk: rockchip: make rockchip_clk_register_branch static It is only used locally in clk/rockchip/clk.c and thus can be static. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-27 06:54:56 +08:00
static struct clk *rockchip_clk_register_branch(const char *name,
clk: make several parent names const Since commit 2893c379461a ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-28 16:45:51 +08:00
const char *const *parent_names, u8 num_parents, void __iomem *base,
clk: rockchip: add basic infrastructure for clock branches This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:58:39 +08:00
int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
u8 div_shift, u8 div_width, u8 div_flags,
struct clk_div_table *div_table, int gate_offset,
u8 gate_shift, u8 gate_flags, unsigned long flags,
spinlock_t *lock)
{
struct clk *clk;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
*gate_ops = NULL;
if (num_parents > 1) {
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
mux->reg = base + muxdiv_offset;
mux->shift = mux_shift;
mux->mask = BIT(mux_width) - 1;
mux->flags = mux_flags;
mux->lock = lock;
mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
: &clk_mux_ops;
}
if (gate_offset >= 0) {
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
gate->flags = gate_flags;
gate->reg = base + gate_offset;
gate->bit_idx = gate_shift;
gate->lock = lock;
gate_ops = &clk_gate_ops;
}
if (div_width > 0) {
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
return ERR_PTR(-ENOMEM);
div->flags = div_flags;
div->reg = base + muxdiv_offset;
div->shift = div_shift;
div->width = div_width;
div->lock = lock;
div->table = div_table;
clk-divider: Fix READ_ONLY when divider > 1 Commit 79c6ab509558 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the recalc_rate() and round_rate() clock callbacks to be omitted. However using this flag has the unfortunate side effect of causing the clock recalculation code when a clock rate change is attempted to always treat it as a pass-through clock, i.e. with a fixed divide of 1, which may not be the case. Child clock rates are then recalculated using the wrong parent rate. Therefore instead of dropping the recalc_rate() and round_rate() callbacks, alter clk_divider_bestdiv() to always report the current divider as the best divider so that it is never altered. For me the read only clock was the system clock, which divided the PLL rate by 2, from which both the UART and the SPI clocks were divided. Initial setting of the UART rate set it correctly, but when the SPI clock was set, the other child clocks were miscalculated. The UART clock was recalculated using the PLL rate as the parent rate, resulting in a UART new_rate of double what it should be, and a UART which spewed forth garbage when the rate changes were propagated. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Max Schwarz <max.schwarz@online.de> Cc: <stable@vger.kernel.org> # v3.16+ Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-14 23:32:09 +08:00
div_ops = &clk_divider_ops;
clk: rockchip: add basic infrastructure for clock branches This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:58:39 +08:00
}
clk = clk_register_composite(NULL, name, parent_names, num_parents,
mux ? &mux->hw : NULL, mux_ops,
div ? &div->hw : NULL, div_ops,
gate ? &gate->hw : NULL, gate_ops,
flags);
return clk;
}
clk: rockchip: handle mux dependency of fractional dividers The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 05:27:59 +08:00
struct rockchip_clk_frac {
struct notifier_block clk_nb;
struct clk_fractional_divider div;
struct clk_gate gate;
struct clk_mux mux;
const struct clk_ops *mux_ops;
int mux_frac_idx;
bool rate_change_remuxed;
int rate_change_idx;
};
#define to_rockchip_clk_frac_nb(nb) \
container_of(nb, struct rockchip_clk_frac, clk_nb)
static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
struct clk_notifier_data *ndata = data;
struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
struct clk_mux *frac_mux = &frac->mux;
int ret = 0;
pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
__func__, event, ndata->old_rate, ndata->new_rate);
if (event == PRE_RATE_CHANGE) {
frac->rate_change_idx = frac->mux_ops->get_parent(&frac_mux->hw);
if (frac->rate_change_idx != frac->mux_frac_idx) {
frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx);
frac->rate_change_remuxed = 1;
}
} else if (event == POST_RATE_CHANGE) {
/*
* The POST_RATE_CHANGE notifier runs directly after the
* divider clock is set in clk_change_rate, so we'll have
* remuxed back to the original parent before clk_change_rate
* reaches the mux itself.
*/
if (frac->rate_change_remuxed) {
frac->mux_ops->set_parent(&frac_mux->hw, frac->rate_change_idx);
frac->rate_change_remuxed = 0;
}
}
return notifier_from_errno(ret);
}
clk: rockchip: implement the fraction divider branch type Rockchip SoCs may provide fraction dividers for some clocks, mostly for i2s and uarts. In contrast to the other registers, these do not use the hiword-mask paradigm, but instead split the register into the upper 16 bit for the nominator and the lower 16 bit for the denominator. The common clock framework got a generic fractional divider clock type recently that can accomodate this setting easily. All currently known fraction dividers have a separate gate too, therefore implement the divider as composite using the ops-struct from fractional_divider clock and add the gate if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-27 06:54:21 +08:00
static struct clk *rockchip_clk_register_frac_branch(const char *name,
clk: make several parent names const Since commit 2893c379461a ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-28 16:45:51 +08:00
const char *const *parent_names, u8 num_parents,
void __iomem *base, int muxdiv_offset, u8 div_flags,
clk: rockchip: implement the fraction divider branch type Rockchip SoCs may provide fraction dividers for some clocks, mostly for i2s and uarts. In contrast to the other registers, these do not use the hiword-mask paradigm, but instead split the register into the upper 16 bit for the nominator and the lower 16 bit for the denominator. The common clock framework got a generic fractional divider clock type recently that can accomodate this setting easily. All currently known fraction dividers have a separate gate too, therefore implement the divider as composite using the ops-struct from fractional_divider clock and add the gate if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-27 06:54:21 +08:00
int gate_offset, u8 gate_shift, u8 gate_flags,
clk: rockchip: handle mux dependency of fractional dividers The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 05:27:59 +08:00
unsigned long flags, struct rockchip_clk_branch *child,
spinlock_t *lock)
clk: rockchip: implement the fraction divider branch type Rockchip SoCs may provide fraction dividers for some clocks, mostly for i2s and uarts. In contrast to the other registers, these do not use the hiword-mask paradigm, but instead split the register into the upper 16 bit for the nominator and the lower 16 bit for the denominator. The common clock framework got a generic fractional divider clock type recently that can accomodate this setting easily. All currently known fraction dividers have a separate gate too, therefore implement the divider as composite using the ops-struct from fractional_divider clock and add the gate if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-27 06:54:21 +08:00
{
clk: rockchip: handle mux dependency of fractional dividers The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 05:27:59 +08:00
struct rockchip_clk_frac *frac;
clk: rockchip: implement the fraction divider branch type Rockchip SoCs may provide fraction dividers for some clocks, mostly for i2s and uarts. In contrast to the other registers, these do not use the hiword-mask paradigm, but instead split the register into the upper 16 bit for the nominator and the lower 16 bit for the denominator. The common clock framework got a generic fractional divider clock type recently that can accomodate this setting easily. All currently known fraction dividers have a separate gate too, therefore implement the divider as composite using the ops-struct from fractional_divider clock and add the gate if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-27 06:54:21 +08:00
struct clk *clk;
struct clk_gate *gate = NULL;
struct clk_fractional_divider *div = NULL;
const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
clk: rockchip: handle mux dependency of fractional dividers The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 05:27:59 +08:00
if (muxdiv_offset < 0)
return ERR_PTR(-EINVAL);
if (child && child->branch_type != branch_mux) {
pr_err("%s: fractional child clock for %s can only be a mux\n",
__func__, name);
return ERR_PTR(-EINVAL);
}
clk: rockchip: implement the fraction divider branch type Rockchip SoCs may provide fraction dividers for some clocks, mostly for i2s and uarts. In contrast to the other registers, these do not use the hiword-mask paradigm, but instead split the register into the upper 16 bit for the nominator and the lower 16 bit for the denominator. The common clock framework got a generic fractional divider clock type recently that can accomodate this setting easily. All currently known fraction dividers have a separate gate too, therefore implement the divider as composite using the ops-struct from fractional_divider clock and add the gate if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-27 06:54:21 +08:00
clk: rockchip: handle mux dependency of fractional dividers The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 05:27:59 +08:00
frac = kzalloc(sizeof(*frac), GFP_KERNEL);
if (!frac)
return ERR_PTR(-ENOMEM);
if (gate_offset >= 0) {
gate = &frac->gate;
clk: rockchip: implement the fraction divider branch type Rockchip SoCs may provide fraction dividers for some clocks, mostly for i2s and uarts. In contrast to the other registers, these do not use the hiword-mask paradigm, but instead split the register into the upper 16 bit for the nominator and the lower 16 bit for the denominator. The common clock framework got a generic fractional divider clock type recently that can accomodate this setting easily. All currently known fraction dividers have a separate gate too, therefore implement the divider as composite using the ops-struct from fractional_divider clock and add the gate if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-27 06:54:21 +08:00
gate->flags = gate_flags;
gate->reg = base + gate_offset;
gate->bit_idx = gate_shift;
gate->lock = lock;
gate_ops = &clk_gate_ops;
}
clk: rockchip: handle mux dependency of fractional dividers The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 05:27:59 +08:00
div = &frac->div;
clk: rockchip: implement the fraction divider branch type Rockchip SoCs may provide fraction dividers for some clocks, mostly for i2s and uarts. In contrast to the other registers, these do not use the hiword-mask paradigm, but instead split the register into the upper 16 bit for the nominator and the lower 16 bit for the denominator. The common clock framework got a generic fractional divider clock type recently that can accomodate this setting easily. All currently known fraction dividers have a separate gate too, therefore implement the divider as composite using the ops-struct from fractional_divider clock and add the gate if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-27 06:54:21 +08:00
div->flags = div_flags;
div->reg = base + muxdiv_offset;
div->mshift = 16;
clk: rockchip: save width in struct clk_fractional_divider The ->mwidth and ->nwidth fields will be used by clk-fractional-divider when it will be switched to rational base approximation algorithm. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-22 23:54:10 +08:00
div->mwidth = 16;
div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
clk: rockchip: implement the fraction divider branch type Rockchip SoCs may provide fraction dividers for some clocks, mostly for i2s and uarts. In contrast to the other registers, these do not use the hiword-mask paradigm, but instead split the register into the upper 16 bit for the nominator and the lower 16 bit for the denominator. The common clock framework got a generic fractional divider clock type recently that can accomodate this setting easily. All currently known fraction dividers have a separate gate too, therefore implement the divider as composite using the ops-struct from fractional_divider clock and add the gate if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-27 06:54:21 +08:00
div->nshift = 0;
clk: rockchip: save width in struct clk_fractional_divider The ->mwidth and ->nwidth fields will be used by clk-fractional-divider when it will be switched to rational base approximation algorithm. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-22 23:54:10 +08:00
div->nwidth = 16;
div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
clk: rockchip: implement the fraction divider branch type Rockchip SoCs may provide fraction dividers for some clocks, mostly for i2s and uarts. In contrast to the other registers, these do not use the hiword-mask paradigm, but instead split the register into the upper 16 bit for the nominator and the lower 16 bit for the denominator. The common clock framework got a generic fractional divider clock type recently that can accomodate this setting easily. All currently known fraction dividers have a separate gate too, therefore implement the divider as composite using the ops-struct from fractional_divider clock and add the gate if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-27 06:54:21 +08:00
div->lock = lock;
div_ops = &clk_fractional_divider_ops;
clk = clk_register_composite(NULL, name, parent_names, num_parents,
NULL, NULL,
&div->hw, div_ops,
gate ? &gate->hw : NULL, gate_ops,
clk: rockchip: handle mux dependency of fractional dividers The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 05:27:59 +08:00
flags | CLK_SET_RATE_UNGATE);
if (IS_ERR(clk)) {
kfree(frac);
return clk;
}
if (child) {
struct clk_mux *frac_mux = &frac->mux;
struct clk_init_data init;
struct clk *mux_clk;
int i, ret;
frac->mux_frac_idx = -1;
for (i = 0; i < child->num_parents; i++) {
if (!strcmp(name, child->parent_names[i])) {
pr_debug("%s: found fractional parent in mux at pos %d\n",
__func__, i);
frac->mux_frac_idx = i;
break;
}
}
frac->mux_ops = &clk_mux_ops;
frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
frac_mux->reg = base + child->muxdiv_offset;
frac_mux->shift = child->mux_shift;
frac_mux->mask = BIT(child->mux_width) - 1;
frac_mux->flags = child->mux_flags;
frac_mux->lock = lock;
frac_mux->hw.init = &init;
init.name = child->name;
init.flags = child->flags | CLK_SET_RATE_PARENT;
init.ops = frac->mux_ops;
init.parent_names = child->parent_names;
init.num_parents = child->num_parents;
mux_clk = clk_register(NULL, &frac_mux->hw);
if (IS_ERR(mux_clk))
return clk;
rockchip_clk_add_lookup(mux_clk, child->id);
/* notifier on the fraction divider to catch rate changes */
if (frac->mux_frac_idx >= 0) {
ret = clk_notifier_register(clk, &frac->clk_nb);
if (ret)
pr_err("%s: failed to register clock notifier for %s\n",
__func__, name);
} else {
pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
__func__, name, child->name);
}
}
clk: rockchip: implement the fraction divider branch type Rockchip SoCs may provide fraction dividers for some clocks, mostly for i2s and uarts. In contrast to the other registers, these do not use the hiword-mask paradigm, but instead split the register into the upper 16 bit for the nominator and the lower 16 bit for the denominator. The common clock framework got a generic fractional divider clock type recently that can accomodate this setting easily. All currently known fraction dividers have a separate gate too, therefore implement the divider as composite using the ops-struct from fractional_divider clock and add the gate if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-27 06:54:21 +08:00
return clk;
}
clk: rockchip: add basic infrastructure for clock branches This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:58:39 +08:00
static DEFINE_SPINLOCK(clk_lock);
static struct clk **clk_table;
static void __iomem *reg_base;
static struct clk_onecell_data clk_data;
clk: rockchip: add clock type for pll clocks and pll used on rk3066 All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:59:10 +08:00
static struct device_node *cru_node;
static struct regmap *grf;
clk: rockchip: add basic infrastructure for clock branches This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:58:39 +08:00
void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
unsigned long nr_clks)
{
reg_base = base;
clk: rockchip: add clock type for pll clocks and pll used on rk3066 All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:59:10 +08:00
cru_node = np;
grf = ERR_PTR(-EPROBE_DEFER);
clk: rockchip: add basic infrastructure for clock branches This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:58:39 +08:00
clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
if (!clk_table)
pr_err("%s: could not allocate clock lookup table\n", __func__);
clk_data.clks = clk_table;
clk_data.clk_num = nr_clks;
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
clk: rockchip: add clock type for pll clocks and pll used on rk3066 All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:59:10 +08:00
struct regmap *rockchip_clk_get_grf(void)
{
if (IS_ERR(grf))
grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
return grf;
}
clk: rockchip: add basic infrastructure for clock branches This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:58:39 +08:00
void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
{
if (clk_table && id)
clk_table[id] = clk;
}
clk: rockchip: add clock type for pll clocks and pll used on rk3066 All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:59:10 +08:00
void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
unsigned int nr_pll, int grf_lock_offset)
{
struct clk *clk;
int idx;
for (idx = 0; idx < nr_pll; idx++, list++) {
clk = rockchip_clk_register_pll(list->type, list->name,
list->parent_names, list->num_parents,
reg_base, list->con_offset, grf_lock_offset,
list->lock_shift, list->mode_offset,
clk: rockchip: add ability to specify pll-specific flags This adds a flag parameter to plls that allows us to create special flags to tweak the behaviour of the plls if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-11-21 03:38:50 +08:00
list->mode_shift, list->rate_table,
list->pll_flags, &clk_lock);
clk: rockchip: add clock type for pll clocks and pll used on rk3066 All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:59:10 +08:00
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
rockchip_clk_add_lookup(clk, list->id);
}
}
clk: rockchip: add basic infrastructure for clock branches This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:58:39 +08:00
void __init rockchip_clk_register_branches(
struct rockchip_clk_branch *list,
unsigned int nr_clk)
{
struct clk *clk = NULL;
unsigned int idx;
unsigned long flags;
for (idx = 0; idx < nr_clk; idx++, list++) {
flags = list->flags;
/* catch simple muxes */
switch (list->branch_type) {
case branch_mux:
clk = clk_register_mux(NULL, list->name,
list->parent_names, list->num_parents,
flags, reg_base + list->muxdiv_offset,
list->mux_shift, list->mux_width,
list->mux_flags, &clk_lock);
break;
case branch_divider:
if (list->div_table)
clk = clk_register_divider_table(NULL,
list->name, list->parent_names[0],
flags, reg_base + list->muxdiv_offset,
list->div_shift, list->div_width,
list->div_flags, list->div_table,
&clk_lock);
else
clk = clk_register_divider(NULL, list->name,
list->parent_names[0], flags,
reg_base + list->muxdiv_offset,
list->div_shift, list->div_width,
list->div_flags, &clk_lock);
break;
case branch_fraction_divider:
clk: rockchip: implement the fraction divider branch type Rockchip SoCs may provide fraction dividers for some clocks, mostly for i2s and uarts. In contrast to the other registers, these do not use the hiword-mask paradigm, but instead split the register into the upper 16 bit for the nominator and the lower 16 bit for the denominator. The common clock framework got a generic fractional divider clock type recently that can accomodate this setting easily. All currently known fraction dividers have a separate gate too, therefore implement the divider as composite using the ops-struct from fractional_divider clock and add the gate if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-27 06:54:21 +08:00
clk = rockchip_clk_register_frac_branch(list->name,
list->parent_names, list->num_parents,
reg_base, list->muxdiv_offset, list->div_flags,
list->gate_offset, list->gate_shift,
clk: rockchip: handle mux dependency of fractional dividers The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 05:27:59 +08:00
list->gate_flags, flags, list->child,
&clk_lock);
clk: rockchip: add basic infrastructure for clock branches This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:58:39 +08:00
break;
case branch_gate:
flags |= CLK_SET_RATE_PARENT;
clk = clk_register_gate(NULL, list->name,
list->parent_names[0], flags,
reg_base + list->gate_offset,
list->gate_shift, list->gate_flags, &clk_lock);
break;
case branch_composite:
clk = rockchip_clk_register_branch(list->name,
list->parent_names, list->num_parents,
reg_base, list->muxdiv_offset, list->mux_shift,
list->mux_width, list->mux_flags,
list->div_shift, list->div_width,
list->div_flags, list->div_table,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, &clk_lock);
break;
clk: rockchip: Add support for the mmc clock phases using the framework This patch adds the 2 physical clocks for the mmc (drive and sample). They're mostly there for the phase properties, but they also show the true clock (by dividing by RK3288_MMC_CLKGEN_DIV). The drive and sample phases are generated by dividing an upstream parent clock by 2, this allows us to adjust the phase by 90 deg. There's also an option to have up to 255 delay elements (40-80 picoseconds long). This driver uses those elements (under the assumption that they're 60 ps long) to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as 90 deg if the delay elements are as big as 80 ps, so a finer division (smaller than 22.5) was not picked because the phase might not be monotonic anymore. Suggested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-27 09:30:27 +08:00
case branch_mmc:
clk = rockchip_clk_register_mmc(
list->name,
list->parent_names, list->num_parents,
reg_base + list->muxdiv_offset,
list->div_shift
);
break;
clk: rockchip: add support for phase inverters Most Rockchip socs have optional phase inverters connected to some clocks that move the clock-phase by 180 degrees. Signed-off-by: Heiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Dropped lazy part of commit text] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-05 17:00:14 +08:00
case branch_inverter:
clk = rockchip_clk_register_inverter(
list->name, list->parent_names,
list->num_parents,
reg_base + list->muxdiv_offset,
list->div_shift, list->div_flags, &clk_lock);
break;
clk: rockchip: add basic infrastructure for clock branches This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-03 07:58:39 +08:00
}
/* none of the cases above matched */
if (!clk) {
pr_err("%s: unknown clock type %d\n",
__func__, list->branch_type);
continue;
}
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s: %ld\n",
__func__, list->name, PTR_ERR(clk));
continue;
}
rockchip_clk_add_lookup(clk, list->id);
}
}
clk: rockchip: protect critical clocks from getting disabled The clock-tree contains clocks that should never get disabled automatically. One example are the base ACLKs, the base supplies for all peripherals. Therefore add a structure similar to the sunxi clock-tree to protect these special clocks from being disabled. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Doug Anderson <dianders@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-15 05:00:26 +08:00
clk: rockchip: add new clock-type for the cpuclk When changing the armclk on Rockchip SoCs it is supposed to be reparented to an alternate parent before changing the underlying pll and back after the change. Additionally there exist clocks that are very tightly bound to the armclk whose divider values are set according to the armclk rate. Add a special clock-type to handle all that. The rate table and divider values will be supplied from the soc-specific clock controllers. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> On a rk3288-board: Tested-by: Doug Anderson <dianders@chromium.org>
2014-09-05 04:10:43 +08:00
void __init rockchip_clk_register_armclk(unsigned int lookup_id,
clk: make several parent names const Since commit 2893c379461a ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-28 16:45:51 +08:00
const char *name, const char *const *parent_names,
clk: rockchip: add new clock-type for the cpuclk When changing the armclk on Rockchip SoCs it is supposed to be reparented to an alternate parent before changing the underlying pll and back after the change. Additionally there exist clocks that are very tightly bound to the armclk whose divider values are set according to the armclk rate. Add a special clock-type to handle all that. The rate table and divider values will be supplied from the soc-specific clock controllers. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> On a rk3288-board: Tested-by: Doug Anderson <dianders@chromium.org>
2014-09-05 04:10:43 +08:00
u8 num_parents,
const struct rockchip_cpuclk_reg_data *reg_data,
const struct rockchip_cpuclk_rate_table *rates,
int nrates)
{
struct clk *clk;
clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
reg_data, rates, nrates, reg_base,
&clk_lock);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s: %ld\n",
__func__, name, PTR_ERR(clk));
return;
}
rockchip_clk_add_lookup(clk, lookup_id);
}
clk: don't use __initconst for non-const arrays The statement static const char *name[]; defines a modifiable array of pointers to constant chars. That is *name[0] = 'f'; is forbidden, but name[0] = "f"; is not. So marking an array that is defined as above with __initconst is wrong. Either an additional const must be added such that the whole definition reads: static const char *const name[] __initconst; or where this is not possible __initdata must be used. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-18 17:59:45 +08:00
void __init rockchip_clk_protect_critical(const char *const clocks[],
int nclocks)
clk: rockchip: protect critical clocks from getting disabled The clock-tree contains clocks that should never get disabled automatically. One example are the base ACLKs, the base supplies for all peripherals. Therefore add a structure similar to the sunxi clock-tree to protect these special clocks from being disabled. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Doug Anderson <dianders@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-15 05:00:26 +08:00
{
int i;
/* Protect the clocks that needs to stay on */
for (i = 0; i < nclocks; i++) {
struct clk *clk = __clk_lookup(clocks[i]);
if (clk)
clk_prepare_enable(clk);
}
}
clk: rockchip: add restart handler Add infrastructure to write the correct value to the restart register and register the restart notifier for both rk3188 (including rk3066) and rk3288. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2014-08-20 08:45:38 +08:00
static unsigned int reg_restart;
clk: rockchip: only enter pll slow-mode directly before reboots on rk3288 As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2015-12-19 00:51:55 +08:00
static void (*cb_restart)(void);
clk: rockchip: add restart handler Add infrastructure to write the correct value to the restart register and register the restart notifier for both rk3188 (including rk3066) and rk3288. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2014-08-20 08:45:38 +08:00
static int rockchip_restart_notify(struct notifier_block *this,
unsigned long mode, void *cmd)
{
clk: rockchip: only enter pll slow-mode directly before reboots on rk3288 As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2015-12-19 00:51:55 +08:00
if (cb_restart)
cb_restart();
clk: rockchip: add restart handler Add infrastructure to write the correct value to the restart register and register the restart notifier for both rk3188 (including rk3066) and rk3288. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2014-08-20 08:45:38 +08:00
writel(0xfdb9, reg_base + reg_restart);
return NOTIFY_DONE;
}
static struct notifier_block rockchip_restart_handler = {
.notifier_call = rockchip_restart_notify,
.priority = 128,
};
clk: rockchip: only enter pll slow-mode directly before reboots on rk3288 As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2015-12-19 00:51:55 +08:00
void __init rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void))
clk: rockchip: add restart handler Add infrastructure to write the correct value to the restart register and register the restart notifier for both rk3188 (including rk3066) and rk3288. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2014-08-20 08:45:38 +08:00
{
int ret;
reg_restart = reg;
clk: rockchip: only enter pll slow-mode directly before reboots on rk3288 As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2015-12-19 00:51:55 +08:00
cb_restart = cb;
clk: rockchip: add restart handler Add infrastructure to write the correct value to the restart register and register the restart notifier for both rk3188 (including rk3066) and rk3288. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2014-08-20 08:45:38 +08:00
ret = register_restart_handler(&rockchip_restart_handler);
if (ret)
pr_err("%s: cannot register restart handler, %d\n",
__func__, ret);
}
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