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linux/drivers/phy/cadence/Kconfig

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treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-19 20:07:45 +08:00
# SPDX-License-Identifier: GPL-2.0-only
phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. Signed-off-by: Scott Telford <stelford@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-08-09 18:30:30 +08:00
#
phy: cadence: Add driver for Sierra PHY Add a Sierra PHY driver with PCIe and USB support. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-11-13 00:42:16 +08:00
# Phy drivers for Cadence PHYs
phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. Signed-off-by: Scott Telford <stelford@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-08-09 18:30:30 +08:00
#
phy: Add Cadence D-PHY support Cadence has designed a D-PHY that can be used by the, currently in tree, DSI bridge (DRM), CSI Transceiver and CSI Receiver (v4l2) drivers. Only the DSI driver has an ad-hoc driver for that phy at the moment, while the v4l2 drivers are completely missing any phy support. In order to make that phy support available to all these drivers, without having to duplicate that code three times, let's create a generic phy framework driver. Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-01-21 23:45:53 +08:00
phy: cadence-dp: Rename to phy-cadence-torrent Rename Cadence DP PHY driver from phy-cadence-dp to phy-cadence-torrent to make it more generic for future use. Modifiy Makefile and Kconfig accordingly. Also, change driver compatible from "cdns,dp-phy" to "cdns,torrent-phy".This will not affect ABI as the driver has never been functional, and therefore do not exist in any active use case. Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-02-06 14:10:51 +08:00
config PHY_CADENCE_TORRENT
tristate "Cadence Torrent PHY driver"
phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. Signed-off-by: Scott Telford <stelford@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-08-09 18:30:30 +08:00
depends on OF
depends on HAS_IOMEM
phy: cadence-torrent: Add support to drive refclk out cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. Model this derived reference clock as a "clock" so that platforms like AM642 EVM can enable it. This is used by PCIe to use the same refclk both in local SERDES and remote device. Add support here to drive refclk out. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210310120840.16447-7-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-10 20:08:40 +08:00
depends on COMMON_CLK
phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. Signed-off-by: Scott Telford <stelford@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-08-09 18:30:30 +08:00
select GENERIC_PHY
help
phy: cadence-dp: Rename to phy-cadence-torrent Rename Cadence DP PHY driver from phy-cadence-dp to phy-cadence-torrent to make it more generic for future use. Modifiy Makefile and Kconfig accordingly. Also, change driver compatible from "cdns,dp-phy" to "cdns,torrent-phy".This will not affect ABI as the driver has never been functional, and therefore do not exist in any active use case. Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-02-06 14:10:51 +08:00
Support for Cadence Torrent PHY.
phy: cadence: Add driver for Sierra PHY Add a Sierra PHY driver with PCIe and USB support. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-11-13 00:42:16 +08:00
phy: Add Cadence D-PHY support Cadence has designed a D-PHY that can be used by the, currently in tree, DSI bridge (DRM), CSI Transceiver and CSI Receiver (v4l2) drivers. Only the DSI driver has an ad-hoc driver for that phy at the moment, while the v4l2 drivers are completely missing any phy support. In order to make that phy support available to all these drivers, without having to duplicate that code three times, let's create a generic phy framework driver. Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-01-21 23:45:53 +08:00
config PHY_CADENCE_DPHY
tristate "Cadence D-PHY Support"
depends on HAS_IOMEM && OF
select GENERIC_PHY
select GENERIC_PHY_MIPI_DPHY
help
Choose this option if you have a Cadence D-PHY in your
system. If M is selected, the module will be called
cdns-dphy.
phy: cadence: Add driver for Sierra PHY Add a Sierra PHY driver with PCIe and USB support. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-11-13 00:42:16 +08:00
config PHY_CADENCE_SIERRA
tristate "Cadence Sierra PHY Driver"
depends on OF && HAS_IOMEM && RESET_CONTROLLER
phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's possible to select one of these two inputs from device tree. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-13-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-19 20:41:27 +08:00
depends on COMMON_CLK
phy: cadence: Add driver for Sierra PHY Add a Sierra PHY driver with PCIe and USB support. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-11-13 00:42:16 +08:00
select GENERIC_PHY
help
phy: Add Cadence D-PHY support Cadence has designed a D-PHY that can be used by the, currently in tree, DSI bridge (DRM), CSI Transceiver and CSI Receiver (v4l2) drivers. Only the DSI driver has an ad-hoc driver for that phy at the moment, while the v4l2 drivers are completely missing any phy support. In order to make that phy support available to all these drivers, without having to duplicate that code three times, let's create a generic phy framework driver. Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-01-21 23:45:53 +08:00
Enable this to support the Cadence Sierra PHY driver
phy: cadence: salvo: add salvo phy driver Cadence SALVO PHY is a 28nm product, and is only used for USB3 & USB2. According to the Cadence, this PHY is a legacy Module, and Sierra and Torrent are later evolutions from it, and their sequence overlap is minimal, meaning we cannot reuse either (Sierra & Torrent) of the PHY drivers. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-04-01 09:38:50 +08:00
config PHY_CADENCE_SALVO
tristate "Cadence Salvo PHY Driver"
depends on OF && HAS_IOMEM
select GENERIC_PHY
help
Enable this to support the Cadence SALVO PHY driver,
this PHY is a legacy PHY, and only are used for USB3
and USB2.
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