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linux/drivers/pci/host/pcie-xilinx.c

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PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate Add SPDX GPL-2.0+ to all PCI files that specified the GPL and allowed either GPL version 2 or any later version. Remove the boilerplate GPL version 2 or later language, relying on the assertion in b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") that the SPDX identifier may be used instead of the full boilerplate text. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-01-27 04:22:04 +08:00
// SPDX-License-Identifier: GPL-2.0+
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
/*
* PCIe host controller driver for Xilinx AXI PCIe Bridge
*
* Copyright (c) 2012 - 2014 Xilinx, Inc.
*
* Based on the Tegra PCIe driver
*
PCI: Fix typos and whitespace errors Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-09-02 05:35:50 +08:00
* Bits taken from Synopsys DesignWare Host controller driver and
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
* ARM PCI Host generic driver.
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
PCI: xilinx: Make explicitly non-modular This code is not being built as a module by anyone: drivers/pci/host/Kconfig:config PCIE_XILINX drivers/pci/host/Kconfig: bool "Xilinx AXI PCIe host bridge support" Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(), etc., so that when reading the driver there is no doubt it is builtin-only. The information is preserved in comments at the top of the file. Note that for non-modular code, builtin_platform_driver() uses the same init level priority as module_platform_driver(), so this doesn't change init ordering. [bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com> CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
2016-08-25 04:57:49 +08:00
#include <linux/init.h>
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
/* Register definitions */
#define XILINX_PCIE_REG_BIR 0x00000130
#define XILINX_PCIE_REG_IDR 0x00000138
#define XILINX_PCIE_REG_IMR 0x0000013c
#define XILINX_PCIE_REG_PSCR 0x00000144
#define XILINX_PCIE_REG_RPSC 0x00000148
#define XILINX_PCIE_REG_MSIBASE1 0x0000014c
#define XILINX_PCIE_REG_MSIBASE2 0x00000150
#define XILINX_PCIE_REG_RPEFR 0x00000154
#define XILINX_PCIE_REG_RPIFR1 0x00000158
#define XILINX_PCIE_REG_RPIFR2 0x0000015c
/* Interrupt registers definitions */
#define XILINX_PCIE_INTR_LINK_DOWN BIT(0)
#define XILINX_PCIE_INTR_ECRC_ERR BIT(1)
#define XILINX_PCIE_INTR_STR_ERR BIT(2)
#define XILINX_PCIE_INTR_HOT_RESET BIT(3)
#define XILINX_PCIE_INTR_CFG_TIMEOUT BIT(8)
#define XILINX_PCIE_INTR_CORRECTABLE BIT(9)
#define XILINX_PCIE_INTR_NONFATAL BIT(10)
#define XILINX_PCIE_INTR_FATAL BIT(11)
#define XILINX_PCIE_INTR_INTX BIT(16)
#define XILINX_PCIE_INTR_MSI BIT(17)
#define XILINX_PCIE_INTR_SLV_UNSUPP BIT(20)
#define XILINX_PCIE_INTR_SLV_UNEXP BIT(21)
#define XILINX_PCIE_INTR_SLV_COMPL BIT(22)
#define XILINX_PCIE_INTR_SLV_ERRP BIT(23)
#define XILINX_PCIE_INTR_SLV_CMPABT BIT(24)
#define XILINX_PCIE_INTR_SLV_ILLBUR BIT(25)
#define XILINX_PCIE_INTR_MST_DECERR BIT(26)
#define XILINX_PCIE_INTR_MST_SLVERR BIT(27)
#define XILINX_PCIE_INTR_MST_ERRP BIT(28)
#define XILINX_PCIE_IMR_ALL_MASK 0x1FF30FED
PCI: xilinx: Don't enable config completion interrupts The Xilinx AXI bridge for PCI Express device provides interrupts indicating the completion of config space accesses. We have previously enabled/unmasked them but do nothing with them besides acknowledge them. Leave the interrupts masked in order to avoid servicing a large number of pointless interrupts during boot. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16 05:25:25 +08:00
#define XILINX_PCIE_IMR_ENABLE_MASK 0x1FF30F0D
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
#define XILINX_PCIE_IDR_ALL_MASK 0xFFFFFFFF
/* Root Port Error FIFO Read Register definitions */
#define XILINX_PCIE_RPEFR_ERR_VALID BIT(18)
#define XILINX_PCIE_RPEFR_REQ_ID GENMASK(15, 0)
#define XILINX_PCIE_RPEFR_ALL_MASK 0xFFFFFFFF
/* Root Port Interrupt FIFO Read Register 1 definitions */
#define XILINX_PCIE_RPIFR1_INTR_VALID BIT(31)
#define XILINX_PCIE_RPIFR1_MSI_INTR BIT(30)
#define XILINX_PCIE_RPIFR1_INTR_MASK GENMASK(28, 27)
#define XILINX_PCIE_RPIFR1_ALL_MASK 0xFFFFFFFF
#define XILINX_PCIE_RPIFR1_INTR_SHIFT 27
/* Bridge Info Register definitions */
#define XILINX_PCIE_BIR_ECAM_SZ_MASK GENMASK(18, 16)
#define XILINX_PCIE_BIR_ECAM_SZ_SHIFT 16
/* Root Port Interrupt FIFO Read Register 2 definitions */
#define XILINX_PCIE_RPIFR2_MSG_DATA GENMASK(15, 0)
/* Root Port Status/control Register definitions */
#define XILINX_PCIE_REG_RPSC_BEN BIT(0)
/* Phy Status/Control Register definitions */
#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
/* ECAM definitions */
#define ECAM_BUS_NUM_SHIFT 20
#define ECAM_DEV_NUM_SHIFT 12
/* Number of MSI IRQs */
#define XILINX_NUM_MSI_IRQS 128
/**
* struct xilinx_pcie_port - PCIe port information
* @reg_base: IO Mapped Register Base
* @irq: Interrupt number
* @msi_pages: MSI pages
* @root_busno: Root Bus number
* @dev: Device pointer
PCI: xilinx: Keep both legacy and MSI interrupt domain references When built with MSI support, the legacy domain reference was being overwritten with MSI. Create two separate domains for MSI and legacy interrupts. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-01 18:14:41 +08:00
* @msi_domain: MSI IRQ domain pointer
* @leg_domain: Legacy IRQ domain pointer
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
* @resources: Bus Resources
*/
struct xilinx_pcie_port {
void __iomem *reg_base;
u32 irq;
unsigned long msi_pages;
u8 root_busno;
struct device *dev;
PCI: xilinx: Keep both legacy and MSI interrupt domain references When built with MSI support, the legacy domain reference was being overwritten with MSI. Create two separate domains for MSI and legacy interrupts. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-01 18:14:41 +08:00
struct irq_domain *msi_domain;
struct irq_domain *leg_domain;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
struct list_head resources;
};
static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
{
return readl(port->reg_base + reg);
}
static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg)
{
writel(val, port->reg_base + reg);
}
PCI: xilinx: Rename xilinx_pcie_link_is_up() to xilinx_pcie_link_up() Rename xilinx_pcie_link_is_up() to xilinx_pcie_link_up() to follow the convention of other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2017-11-10 06:19:47 +08:00
static inline bool xilinx_pcie_link_up(struct xilinx_pcie_port *port)
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
{
return (pcie_read(port, XILINX_PCIE_REG_PSCR) &
XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
}
/**
* xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
* @port: PCIe port information
*/
static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
{
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
struct device *dev = port->dev;
PCI: xilinx: Fix harmless format string warning The xilinx PCIe driver prints a register value whose type is propagated to the type returned by the GENMASK() macro. Unfortunately, that type has recently changed as the result of a bug fix, so now we get a warning about the type: drivers/pci/host/pcie-xilinx.c: In function 'xilinx_pcie_clear_err_interrupts': drivers/pci/host/pcie-xilinx.c:154:3: warning: format '%d' expects argument of type 'int', but argument 4 has type 'long unsigned int' [-Wformat=] Change the code so we always print the number as an 'unsigned long' type to avoid the warning. The original code was fine on 32-bit architectures but not on 64-bit. Now it works as expected on both. Fixes: 00b4d9a1412 ("bitops: Fix shift overflow in GENMASK macros") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-01-13 22:20:05 +08:00
unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_dbg(dev, "Requester ID %lu\n",
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
val & XILINX_PCIE_RPEFR_REQ_ID);
pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK,
XILINX_PCIE_REG_RPEFR);
}
}
/**
* xilinx_pcie_valid_device - Check if a valid device is present on bus
* @bus: PCI Bus structure
* @devfn: device/function
*
* Return: 'true' on success and 'false' if invalid device is found
*/
static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
{
PCI: xilinx: Remove dependency on ARM-specific struct hw_pci The Xilinx PCIe host controller driver uses pci_common_init_dev(), which is ARM-specific and requires the ARM struct hw_pci. The part of pci_common_init_dev() that is needed is limited and can be done here without using hw_pci. Create and scan the root bus directly without using the ARM pci_common_init_dev() interface. [bhelgaas: revise changelog to show similarity to 79953dd22c1d ("PCI: rcar: Remove dependency on ARM-specific struct hw_pci")] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-02-12 00:28:08 +08:00
struct xilinx_pcie_port *port = bus->sysdata;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
/* Check if link is up when trying to access downstream ports */
if (bus->number != port->root_busno)
PCI: xilinx: Rename xilinx_pcie_link_is_up() to xilinx_pcie_link_up() Rename xilinx_pcie_link_is_up() to xilinx_pcie_link_up() to follow the convention of other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2017-11-10 06:19:47 +08:00
if (!xilinx_pcie_link_up(port))
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
return false;
/* Only one device down on each root port */
if (bus->number == port->root_busno && devfn > 0)
return false;
return true;
}
/**
PCI: xilinx: Convert to use generic config accessors Convert the Xilinx host PCI driver to use the generic config access functions. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com> CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com> CC: linux-arm-kernel@lists.infradead.org
2015-01-10 10:34:50 +08:00
* xilinx_pcie_map_bus - Get configuration base
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
* @bus: PCI Bus structure
* @devfn: Device/function
* @where: Offset from base
*
* Return: Base address of the configuration space needed to be
* accessed.
*/
PCI: xilinx: Convert to use generic config accessors Convert the Xilinx host PCI driver to use the generic config access functions. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com> CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com> CC: linux-arm-kernel@lists.infradead.org
2015-01-10 10:34:50 +08:00
static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
unsigned int devfn, int where)
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
{
PCI: xilinx: Remove dependency on ARM-specific struct hw_pci The Xilinx PCIe host controller driver uses pci_common_init_dev(), which is ARM-specific and requires the ARM struct hw_pci. The part of pci_common_init_dev() that is needed is limited and can be done here without using hw_pci. Create and scan the root bus directly without using the ARM pci_common_init_dev() interface. [bhelgaas: revise changelog to show similarity to 79953dd22c1d ("PCI: rcar: Remove dependency on ARM-specific struct hw_pci")] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-02-12 00:28:08 +08:00
struct xilinx_pcie_port *port = bus->sysdata;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
int relbus;
PCI: xilinx: Convert to use generic config accessors Convert the Xilinx host PCI driver to use the generic config access functions. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com> CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com> CC: linux-arm-kernel@lists.infradead.org
2015-01-10 10:34:50 +08:00
if (!xilinx_pcie_valid_device(bus, devfn))
return NULL;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
(devfn << ECAM_DEV_NUM_SHIFT);
return port->reg_base + relbus + where;
}
/* PCIe operations */
static struct pci_ops xilinx_pcie_ops = {
PCI: xilinx: Convert to use generic config accessors Convert the Xilinx host PCI driver to use the generic config access functions. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com> CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com> CC: linux-arm-kernel@lists.infradead.org
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.map_bus = xilinx_pcie_map_bus,
.read = pci_generic_config_read,
.write = pci_generic_config_write,
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
};
/* MSI functions */
/**
* xilinx_pcie_destroy_msi - Free MSI number
* @irq: IRQ to be freed
*/
static void xilinx_pcie_destroy_msi(unsigned int irq)
{
struct msi_desc *msi;
struct xilinx_pcie_port *port;
PCI: xilinx: Clear correct MSI set bit Kernel provides virtual IRQ number at teardown. Get hwirq number from virtual IRQ and clear correct MSI set bit. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-01 18:14:43 +08:00
struct irq_data *d = irq_get_irq_data(irq);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
PCI: xilinx: Clear correct MSI set bit Kernel provides virtual IRQ number at teardown. Get hwirq number from virtual IRQ and clear correct MSI set bit. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-01 18:14:43 +08:00
if (!test_bit(hwirq, msi_irq_in_use)) {
PCI: Use helper functions to access fields in struct msi_desc Use helper functions to access fields in struct msi_desc, so we could easily refine msi_desc later. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Reviewed-by: Yijing Wang <wangyijing@huawei.com> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Stuart Yoder <stuart.yoder@freescale.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Pratyush Anand <pratyush.anand@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Soeren Brinkmann <soren.brinkmann@xilinx.com> Cc: Srikanth Thokala <sthokal@xilinx.com> Cc: Rob Herring <robh@kernel.org> Link: http://lkml.kernel.org/r/1436428847-8886-9-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-09 16:00:43 +08:00
msi = irq_get_msi_desc(irq);
PCI: xilinx: Remove dependency on ARM-specific struct hw_pci The Xilinx PCIe host controller driver uses pci_common_init_dev(), which is ARM-specific and requires the ARM struct hw_pci. The part of pci_common_init_dev() that is needed is limited and can be done here without using hw_pci. Create and scan the root bus directly without using the ARM pci_common_init_dev() interface. [bhelgaas: revise changelog to show similarity to 79953dd22c1d ("PCI: rcar: Remove dependency on ARM-specific struct hw_pci")] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-02-12 00:28:08 +08:00
port = msi_desc_to_pci_sysdata(msi);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
PCI: Use helper functions to access fields in struct msi_desc Use helper functions to access fields in struct msi_desc, so we could easily refine msi_desc later. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Reviewed-by: Yijing Wang <wangyijing@huawei.com> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Stuart Yoder <stuart.yoder@freescale.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Pratyush Anand <pratyush.anand@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Soeren Brinkmann <soren.brinkmann@xilinx.com> Cc: Srikanth Thokala <sthokal@xilinx.com> Cc: Rob Herring <robh@kernel.org> Link: http://lkml.kernel.org/r/1436428847-8886-9-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-09 16:00:43 +08:00
} else {
PCI: xilinx: Clear correct MSI set bit Kernel provides virtual IRQ number at teardown. Get hwirq number from virtual IRQ and clear correct MSI set bit. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-01 18:14:43 +08:00
clear_bit(hwirq, msi_irq_in_use);
PCI: Use helper functions to access fields in struct msi_desc Use helper functions to access fields in struct msi_desc, so we could easily refine msi_desc later. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Reviewed-by: Yijing Wang <wangyijing@huawei.com> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Stuart Yoder <stuart.yoder@freescale.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Pratyush Anand <pratyush.anand@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Soeren Brinkmann <soren.brinkmann@xilinx.com> Cc: Srikanth Thokala <sthokal@xilinx.com> Cc: Rob Herring <robh@kernel.org> Link: http://lkml.kernel.org/r/1436428847-8886-9-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-09 16:00:43 +08:00
}
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
}
/**
* xilinx_pcie_assign_msi - Allocate MSI number
*
* Return: A valid IRQ on success and error value on failure.
*/
PCI: xilinx: Removed unused xilinx_pcie_assign_msi() argument xilinx_pcie_assign_msi() doesn't use the struct xilinx_pcie_port pointer passed to it, so remove the argument completely. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-12 00:36:49 +08:00
static int xilinx_pcie_assign_msi(void)
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
{
int pos;
pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
if (pos < XILINX_NUM_MSI_IRQS)
set_bit(pos, msi_irq_in_use);
else
return -ENOSPC;
return pos;
}
/**
* xilinx_msi_teardown_irq - Destroy the MSI
* @chip: MSI Chip descriptor
* @irq: MSI IRQ to destroy
*/
PCI/MSI: Rename "struct msi_chip" to "struct msi_controller" "msi_chip" isn't very descriptive, so rename it to "msi_controller". That tells a little more about what it does and is already used in device tree bindings. No functional change. [bhelgaas: changelog, change *only* the struct name so it's reviewable] Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-12 08:45:45 +08:00
static void xilinx_msi_teardown_irq(struct msi_controller *chip,
unsigned int irq)
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
{
xilinx_pcie_destroy_msi(irq);
PCI: xilinx: Dispose of MSI virtual IRQ Dispose of virtual IRQ being created for MSI interrupts. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-01 18:14:44 +08:00
irq_dispose_mapping(irq);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
}
/**
* xilinx_pcie_msi_setup_irq - Setup MSI request
* @chip: MSI chip pointer
* @pdev: PCIe device pointer
* @desc: MSI descriptor pointer
*
* Return: '0' on success and error value on failure
*/
PCI/MSI: Rename "struct msi_chip" to "struct msi_controller" "msi_chip" isn't very descriptive, so rename it to "msi_controller". That tells a little more about what it does and is already used in device tree bindings. No functional change. [bhelgaas: changelog, change *only* the struct name so it's reviewable] Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-12 08:45:45 +08:00
static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
struct pci_dev *pdev,
struct msi_desc *desc)
{
PCI: xilinx: Remove dependency on ARM-specific struct hw_pci The Xilinx PCIe host controller driver uses pci_common_init_dev(), which is ARM-specific and requires the ARM struct hw_pci. The part of pci_common_init_dev() that is needed is limited and can be done here without using hw_pci. Create and scan the root bus directly without using the ARM pci_common_init_dev() interface. [bhelgaas: revise changelog to show similarity to 79953dd22c1d ("PCI: rcar: Remove dependency on ARM-specific struct hw_pci")] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-02-12 00:28:08 +08:00
struct xilinx_pcie_port *port = pdev->bus->sysdata;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
unsigned int irq;
int hwirq;
struct msi_msg msg;
phys_addr_t msg_addr;
PCI: xilinx: Removed unused xilinx_pcie_assign_msi() argument xilinx_pcie_assign_msi() doesn't use the struct xilinx_pcie_port pointer passed to it, so remove the argument completely. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-12 00:36:49 +08:00
hwirq = xilinx_pcie_assign_msi();
PCI: xilinx: Fix xilinx_pcie_assign_msi() return value test We should be testing "hwirq" instead of "irq". "irq" is unsigned so it's never less than zero. Also it's uninitialized. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Srikanth Thokala <sthokal@xilinx.com>
2014-09-09 20:11:50 +08:00
if (hwirq < 0)
return hwirq;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
PCI: xilinx: Keep both legacy and MSI interrupt domain references When built with MSI support, the legacy domain reference was being overwritten with MSI. Create two separate domains for MSI and legacy interrupts. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-01 18:14:41 +08:00
irq = irq_create_mapping(port->msi_domain, hwirq);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (!irq)
return -EINVAL;
irq_set_msi_desc(irq, desc);
msg_addr = virt_to_phys((void *)port->msi_pages);
msg.address_hi = 0;
msg.address_lo = msg_addr;
msg.data = irq;
PCI/MSI: Rename write_msi_msg() to pci_write_msi_msg() Rename write_msi_msg() to pci_write_msi_msg() to mark it as PCI specific. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-11-09 23:10:34 +08:00
pci_write_msi_msg(irq, &msg);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
return 0;
}
/* MSI Chip Descriptor */
PCI/MSI: Rename "struct msi_chip" to "struct msi_controller" "msi_chip" isn't very descriptive, so rename it to "msi_controller". That tells a little more about what it does and is already used in device tree bindings. No functional change. [bhelgaas: changelog, change *only* the struct name so it's reviewable] Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-12 08:45:45 +08:00
static struct msi_controller xilinx_pcie_msi_chip = {
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
.setup_irq = xilinx_pcie_msi_setup_irq,
.teardown_irq = xilinx_msi_teardown_irq,
};
/* HW Interrupt Chip Descriptor */
static struct irq_chip xilinx_msi_irq_chip = {
.name = "Xilinx PCIe MSI",
PCI/MSI: Rename mask/unmask_msi_irq treewide The PCI/MSI irq chip callbacks mask/unmask_msi_irq have been renamed to pci_msi_mask/unmask_irq to mark them PCI specific. Rename all usage sites. The conversion helper functions are kept around to avoid conflicts in next and will be removed after merging into mainline. Coccinelle assisted conversion. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: x86@kernel.org Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Mohit Kumar <mohit.kumar@st.com> Cc: Simon Horman <horms@verge.net.au> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Yijing Wang <wangyijing@huawei.com>
2014-11-23 19:23:20 +08:00
.irq_enable = pci_msi_unmask_irq,
.irq_disable = pci_msi_mask_irq,
.irq_mask = pci_msi_mask_irq,
.irq_unmask = pci_msi_unmask_irq,
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
};
/**
* xilinx_pcie_msi_map - Set the handler for the MSI and mark IRQ as valid
* @domain: IRQ domain
* @irq: Virtual IRQ number
* @hwirq: HW interrupt number
*
* Return: Always returns 0.
*/
static int xilinx_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
irq_hw_number_t hwirq)
{
irq_set_chip_and_handler(irq, &xilinx_msi_irq_chip, handle_simple_irq);
irq_set_chip_data(irq, domain->host_data);
return 0;
}
/* IRQ Domain operations */
static const struct irq_domain_ops msi_domain_ops = {
.map = xilinx_pcie_msi_map,
};
/**
* xilinx_pcie_enable_msi - Enable MSI support
* @port: PCIe port information
*/
static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
{
phys_addr_t msg_addr;
port->msi_pages = __get_free_pages(GFP_KERNEL, 0);
msg_addr = virt_to_phys((void *)port->msi_pages);
pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
}
/* INTx Functions */
/**
* xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
* @domain: IRQ domain
* @irq: Virtual IRQ number
* @hwirq: HW interrupt number
*
* Return: Always returns 0.
*/
static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
irq_hw_number_t hwirq)
{
irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
irq_set_chip_data(irq, domain->host_data);
return 0;
}
/* INTx IRQ Domain operations */
static const struct irq_domain_ops intx_domain_ops = {
.map = xilinx_pcie_intx_map,
PCI: xilinx: Translate INTx range to hwirqs 0-3 The pcie-xilinx driver creates an IRQ domain of size 4 for legacy PCI INTx interrupts, which at first glance seems reasonable since there are 4 possible such interrupts. Unfortunately the driver then proceeds to use the range 1-4 as the hwirq numbers for INTA-INTD, causing warnings & broken interrupts when attempting to use INTD/hwirq=4 due to it being beyond the range of the IRQ domain: WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:365 irq_domain_associate+0x170/0x220 error: hwirq 0x4 is too large for dummy Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 4.12.0-rc5-00126-g19e1b3a10aad-dirty #427 Stack : 0000000000000000 0000000000000004 0000000000000006 ffffffff8092c78a 0000000000000061 ffffffff8018bf60 0000000000000000 0000000000000000 ffffffff8088c287 ffffffff80811d18 a8000000ffc60000 ffffffff80926678 0000000000000001 0000000000000000 ffffffff80887880 ffffffff80960000 ffffffff80920000 ffffffff801e6744 ffffffff80887880 a8000000ffc4f8f8 000000000000089c ffffffff8018d260 0000000000010000 ffffffff80811d18 0000000000000000 0000000000000001 0000000000000000 0000000000000000 0000000000000000 a8000000ffc4f840 0000000000000000 ffffffff8042cf34 0000000000000000 0000000000000000 0000000000000000 0000000000040c00 0000000000000000 ffffffff8010d1c8 0000000000000000 ffffffff8042cf34 ... Call Trace: [<ffffffff8010d1c8>] show_stack+0x80/0xa0 [<ffffffff8042cf34>] dump_stack+0xd4/0x110 [<ffffffff8013ea98>] __warn+0xf0/0x108 [<ffffffff8013eb14>] warn_slowpath_fmt+0x3c/0x48 [<ffffffff80196528>] irq_domain_associate+0x170/0x220 [<ffffffff80196bf0>] irq_create_mapping+0x88/0x118 [<ffffffff801976a8>] irq_create_fwspec_mapping+0xb8/0x320 [<ffffffff80197970>] irq_create_of_mapping+0x60/0x70 [<ffffffff805d1318>] of_irq_parse_and_map_pci+0x20/0x38 [<ffffffff8049c210>] pci_fixup_irqs+0x60/0xe0 [<ffffffff8049cd64>] xilinx_pcie_probe+0x28c/0x478 [<ffffffff804e8ca8>] platform_drv_probe+0x50/0xd0 [<ffffffff804e73a4>] driver_probe_device+0x2c4/0x3a0 [<ffffffff804e7544>] __driver_attach+0xc4/0xd0 [<ffffffff804e5254>] bus_for_each_dev+0x64/0xa8 [<ffffffff804e5e40>] bus_add_driver+0x1f0/0x268 [<ffffffff804e8000>] driver_register+0x68/0x118 [<ffffffff801001a4>] do_one_initcall+0x4c/0x178 [<ffffffff808d3ca8>] kernel_init_freeable+0x204/0x2b0 [<ffffffff80730b68>] kernel_init+0x10/0xf8 [<ffffffff80106218>] ret_from_kernel_thread+0x14/0x1c Fix this by making use of the new pci_irqd_intx_xlate() helper to translate the INTx 1-4 range into the 0-3 range suitable for the IRQ domain of size 4, and stop adding 1 to the hwirq number decoded from the interrupt FIFO which is already in the range 0-3. Whilst we're here we switch to using PCI_NUM_INTX rather than the magic number 4, making it clearer what the 4 means. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16 05:25:08 +08:00
.xlate = pci_irqd_intx_xlate,
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
};
/* PCIe HW Functions */
/**
* xilinx_pcie_intr_handler - Interrupt Service Handler
* @irq: IRQ number
* @data: PCIe port information
*
* Return: IRQ_HANDLED on success and IRQ_NONE on failure
*/
static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
{
struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data;
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
struct device *dev = port->dev;
PCI: xilinx: Unify INTx & MSI interrupt decode The INTx & MSI interrupt decode paths duplicated a fair bit of common functionality. They also strictly handled interrupts in order of INTx then MSI, so if both types of interrupt were to be asserted simultaneously and the MSI interrupt were first in the FIFO then the INTx code would read it & ignore it before the MSI code then had to read it again, wasting the original FIFO read. Unify the INTx & MSI decode in order to reduce that duplication & allow a single FIFO read to be performed for each interrupt regardless of its type. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16 05:25:21 +08:00
u32 val, mask, status;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
/* Read interrupt decode and mask registers */
val = pcie_read(port, XILINX_PCIE_REG_IDR);
mask = pcie_read(port, XILINX_PCIE_REG_IMR);
status = val & mask;
if (!status)
return IRQ_NONE;
if (status & XILINX_PCIE_INTR_LINK_DOWN)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Link Down\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_ECRC_ERR)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "ECRC failed\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_STR_ERR)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Streaming error\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_HOT_RESET)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_info(dev, "Hot reset\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "ECAM access timeout\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_CORRECTABLE) {
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Correctable error message\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
xilinx_pcie_clear_err_interrupts(port);
}
if (status & XILINX_PCIE_INTR_NONFATAL) {
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Non fatal error message\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
xilinx_pcie_clear_err_interrupts(port);
}
if (status & XILINX_PCIE_INTR_FATAL) {
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Fatal error message\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
xilinx_pcie_clear_err_interrupts(port);
}
PCI: xilinx: Unify INTx & MSI interrupt decode The INTx & MSI interrupt decode paths duplicated a fair bit of common functionality. They also strictly handled interrupts in order of INTx then MSI, so if both types of interrupt were to be asserted simultaneously and the MSI interrupt were first in the FIFO then the INTx code would read it & ignore it before the MSI code then had to read it again, wasting the original FIFO read. Unify the INTx & MSI decode in order to reduce that duplication & allow a single FIFO read to be performed for each interrupt regardless of its type. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16 05:25:21 +08:00
if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) {
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
/* Check whether interrupt valid */
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "RP Intr FIFO1 read error\n");
PCI: xilinx: Clear interrupt register for invalid interrupt The interrupt decode register is not being cleared if an invalid interrupt arises. Clear the decode register in this case. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-01 18:14:42 +08:00
goto error;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
}
PCI: xilinx: Unify INTx & MSI interrupt decode The INTx & MSI interrupt decode paths duplicated a fair bit of common functionality. They also strictly handled interrupts in order of INTx then MSI, so if both types of interrupt were to be asserted simultaneously and the MSI interrupt were first in the FIFO then the INTx code would read it & ignore it before the MSI code then had to read it again, wasting the original FIFO read. Unify the INTx & MSI decode in order to reduce that duplication & allow a single FIFO read to be performed for each interrupt regardless of its type. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16 05:25:21 +08:00
/* Decode the IRQ number */
if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
val = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
XILINX_PCIE_RPIFR2_MSG_DATA;
} else {
PCI: xilinx: Translate INTx range to hwirqs 0-3 The pcie-xilinx driver creates an IRQ domain of size 4 for legacy PCI INTx interrupts, which at first glance seems reasonable since there are 4 possible such interrupts. Unfortunately the driver then proceeds to use the range 1-4 as the hwirq numbers for INTA-INTD, causing warnings & broken interrupts when attempting to use INTD/hwirq=4 due to it being beyond the range of the IRQ domain: WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:365 irq_domain_associate+0x170/0x220 error: hwirq 0x4 is too large for dummy Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 4.12.0-rc5-00126-g19e1b3a10aad-dirty #427 Stack : 0000000000000000 0000000000000004 0000000000000006 ffffffff8092c78a 0000000000000061 ffffffff8018bf60 0000000000000000 0000000000000000 ffffffff8088c287 ffffffff80811d18 a8000000ffc60000 ffffffff80926678 0000000000000001 0000000000000000 ffffffff80887880 ffffffff80960000 ffffffff80920000 ffffffff801e6744 ffffffff80887880 a8000000ffc4f8f8 000000000000089c ffffffff8018d260 0000000000010000 ffffffff80811d18 0000000000000000 0000000000000001 0000000000000000 0000000000000000 0000000000000000 a8000000ffc4f840 0000000000000000 ffffffff8042cf34 0000000000000000 0000000000000000 0000000000000000 0000000000040c00 0000000000000000 ffffffff8010d1c8 0000000000000000 ffffffff8042cf34 ... Call Trace: [<ffffffff8010d1c8>] show_stack+0x80/0xa0 [<ffffffff8042cf34>] dump_stack+0xd4/0x110 [<ffffffff8013ea98>] __warn+0xf0/0x108 [<ffffffff8013eb14>] warn_slowpath_fmt+0x3c/0x48 [<ffffffff80196528>] irq_domain_associate+0x170/0x220 [<ffffffff80196bf0>] irq_create_mapping+0x88/0x118 [<ffffffff801976a8>] irq_create_fwspec_mapping+0xb8/0x320 [<ffffffff80197970>] irq_create_of_mapping+0x60/0x70 [<ffffffff805d1318>] of_irq_parse_and_map_pci+0x20/0x38 [<ffffffff8049c210>] pci_fixup_irqs+0x60/0xe0 [<ffffffff8049cd64>] xilinx_pcie_probe+0x28c/0x478 [<ffffffff804e8ca8>] platform_drv_probe+0x50/0xd0 [<ffffffff804e73a4>] driver_probe_device+0x2c4/0x3a0 [<ffffffff804e7544>] __driver_attach+0xc4/0xd0 [<ffffffff804e5254>] bus_for_each_dev+0x64/0xa8 [<ffffffff804e5e40>] bus_add_driver+0x1f0/0x268 [<ffffffff804e8000>] driver_register+0x68/0x118 [<ffffffff801001a4>] do_one_initcall+0x4c/0x178 [<ffffffff808d3ca8>] kernel_init_freeable+0x204/0x2b0 [<ffffffff80730b68>] kernel_init+0x10/0xf8 [<ffffffff80106218>] ret_from_kernel_thread+0x14/0x1c Fix this by making use of the new pci_irqd_intx_xlate() helper to translate the INTx 1-4 range into the 0-3 range suitable for the IRQ domain of size 4, and stop adding 1 to the hwirq number decoded from the interrupt FIFO which is already in the range 0-3. Whilst we're here we switch to using PCI_NUM_INTX rather than the magic number 4, making it clearer what the 4 means. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16 05:25:08 +08:00
val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
XILINX_PCIE_RPIFR1_INTR_SHIFT;
PCI: xilinx: Unify INTx & MSI interrupt decode The INTx & MSI interrupt decode paths duplicated a fair bit of common functionality. They also strictly handled interrupts in order of INTx then MSI, so if both types of interrupt were to be asserted simultaneously and the MSI interrupt were first in the FIFO then the INTx code would read it & ignore it before the MSI code then had to read it again, wasting the original FIFO read. Unify the INTx & MSI decode in order to reduce that duplication & allow a single FIFO read to be performed for each interrupt regardless of its type. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16 05:25:21 +08:00
val = irq_find_mapping(port->leg_domain, val);
PCI: xilinx: Check for MSI interrupt flag before handling as INTx Occasionally both MSI and INTx bits in the interrupt decode register are set at once by the Xilinx AXI PCIe Bridge, so the MSI flag in the interrupt message should be checked to ensure that the correct handler is used. If this check is not in place and the interrupt message type is MSI, the INTx handler will be used erroneously when both type bits are set. This will also be followed by a second read of the message FIFO, which can result in the function returning early and the interrupt decode register not being cleared if the FIFO is now empty. Signed-off-by: Russell Joyce <russell.joyce@york.ac.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-07-08 00:54:19 +08:00
}
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
PCI: xilinx: Unify INTx & MSI interrupt decode The INTx & MSI interrupt decode paths duplicated a fair bit of common functionality. They also strictly handled interrupts in order of INTx then MSI, so if both types of interrupt were to be asserted simultaneously and the MSI interrupt were first in the FIFO then the INTx code would read it & ignore it before the MSI code then had to read it again, wasting the original FIFO read. Unify the INTx & MSI decode in order to reduce that duplication & allow a single FIFO read to be performed for each interrupt regardless of its type. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16 05:25:21 +08:00
/* Clear interrupt FIFO register 1 */
pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
XILINX_PCIE_REG_RPIFR1);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
PCI: xilinx: Unify INTx & MSI interrupt decode The INTx & MSI interrupt decode paths duplicated a fair bit of common functionality. They also strictly handled interrupts in order of INTx then MSI, so if both types of interrupt were to be asserted simultaneously and the MSI interrupt were first in the FIFO then the INTx code would read it & ignore it before the MSI code then had to read it again, wasting the original FIFO read. Unify the INTx & MSI decode in order to reduce that duplication & allow a single FIFO read to be performed for each interrupt regardless of its type. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16 05:25:21 +08:00
/* Handle the interrupt */
if (IS_ENABLED(CONFIG_PCI_MSI) ||
!(val & XILINX_PCIE_RPIFR1_MSI_INTR))
generic_handle_irq(val);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
}
if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Slave unsupported request\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_SLV_UNEXP)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Slave unexpected completion\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_SLV_COMPL)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Slave completion timeout\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_SLV_ERRP)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Slave Error Poison\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_SLV_CMPABT)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Slave Completer Abort\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Slave Illegal Burst\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_MST_DECERR)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Master decode error\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_MST_SLVERR)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Master slave error\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (status & XILINX_PCIE_INTR_MST_ERRP)
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_warn(dev, "Master error poison\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
PCI: xilinx: Clear interrupt register for invalid interrupt The interrupt decode register is not being cleared if an invalid interrupt arises. Clear the decode register in this case. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-01 18:14:42 +08:00
error:
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
/* Clear the Interrupt Decode register */
pcie_write(port, status, XILINX_PCIE_REG_IDR);
return IRQ_HANDLED;
}
/**
* xilinx_pcie_init_irq_domain - Initialize IRQ domain
* @port: PCIe port information
*
* Return: '0' on success and error value on failure
*/
static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
{
struct device *dev = port->dev;
struct device_node *node = dev->of_node;
struct device_node *pcie_intc_node;
/* Setup INTx */
pcie_intc_node = of_get_next_child(node, NULL);
if (!pcie_intc_node) {
dev_err(dev, "No PCIe Intc node found\n");
PCI: xilinx: Fix return value in case of error In xilinx_pcie_init_irq_domain(), the pattern used to check and return error is: if (!var) { dev_err(...); return PTR_ERR(var); } So the returned value in case of error is always 0, which means 'success'. Change it to return -ENODEV instead. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
2016-07-14 18:10:46 +08:00
return -ENODEV;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
}
PCI: xilinx: Translate INTx range to hwirqs 0-3 The pcie-xilinx driver creates an IRQ domain of size 4 for legacy PCI INTx interrupts, which at first glance seems reasonable since there are 4 possible such interrupts. Unfortunately the driver then proceeds to use the range 1-4 as the hwirq numbers for INTA-INTD, causing warnings & broken interrupts when attempting to use INTD/hwirq=4 due to it being beyond the range of the IRQ domain: WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:365 irq_domain_associate+0x170/0x220 error: hwirq 0x4 is too large for dummy Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 4.12.0-rc5-00126-g19e1b3a10aad-dirty #427 Stack : 0000000000000000 0000000000000004 0000000000000006 ffffffff8092c78a 0000000000000061 ffffffff8018bf60 0000000000000000 0000000000000000 ffffffff8088c287 ffffffff80811d18 a8000000ffc60000 ffffffff80926678 0000000000000001 0000000000000000 ffffffff80887880 ffffffff80960000 ffffffff80920000 ffffffff801e6744 ffffffff80887880 a8000000ffc4f8f8 000000000000089c ffffffff8018d260 0000000000010000 ffffffff80811d18 0000000000000000 0000000000000001 0000000000000000 0000000000000000 0000000000000000 a8000000ffc4f840 0000000000000000 ffffffff8042cf34 0000000000000000 0000000000000000 0000000000000000 0000000000040c00 0000000000000000 ffffffff8010d1c8 0000000000000000 ffffffff8042cf34 ... Call Trace: [<ffffffff8010d1c8>] show_stack+0x80/0xa0 [<ffffffff8042cf34>] dump_stack+0xd4/0x110 [<ffffffff8013ea98>] __warn+0xf0/0x108 [<ffffffff8013eb14>] warn_slowpath_fmt+0x3c/0x48 [<ffffffff80196528>] irq_domain_associate+0x170/0x220 [<ffffffff80196bf0>] irq_create_mapping+0x88/0x118 [<ffffffff801976a8>] irq_create_fwspec_mapping+0xb8/0x320 [<ffffffff80197970>] irq_create_of_mapping+0x60/0x70 [<ffffffff805d1318>] of_irq_parse_and_map_pci+0x20/0x38 [<ffffffff8049c210>] pci_fixup_irqs+0x60/0xe0 [<ffffffff8049cd64>] xilinx_pcie_probe+0x28c/0x478 [<ffffffff804e8ca8>] platform_drv_probe+0x50/0xd0 [<ffffffff804e73a4>] driver_probe_device+0x2c4/0x3a0 [<ffffffff804e7544>] __driver_attach+0xc4/0xd0 [<ffffffff804e5254>] bus_for_each_dev+0x64/0xa8 [<ffffffff804e5e40>] bus_add_driver+0x1f0/0x268 [<ffffffff804e8000>] driver_register+0x68/0x118 [<ffffffff801001a4>] do_one_initcall+0x4c/0x178 [<ffffffff808d3ca8>] kernel_init_freeable+0x204/0x2b0 [<ffffffff80730b68>] kernel_init+0x10/0xf8 [<ffffffff80106218>] ret_from_kernel_thread+0x14/0x1c Fix this by making use of the new pci_irqd_intx_xlate() helper to translate the INTx 1-4 range into the 0-3 range suitable for the IRQ domain of size 4, and stop adding 1 to the hwirq number decoded from the interrupt FIFO which is already in the range 0-3. Whilst we're here we switch to using PCI_NUM_INTX rather than the magic number 4, making it clearer what the 4 means. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16 05:25:08 +08:00
port->leg_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
&intx_domain_ops,
port);
PCI: xilinx: Keep both legacy and MSI interrupt domain references When built with MSI support, the legacy domain reference was being overwritten with MSI. Create two separate domains for MSI and legacy interrupts. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-01 18:14:41 +08:00
if (!port->leg_domain) {
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
dev_err(dev, "Failed to get a INTx IRQ domain\n");
PCI: xilinx: Fix return value in case of error In xilinx_pcie_init_irq_domain(), the pattern used to check and return error is: if (!var) { dev_err(...); return PTR_ERR(var); } So the returned value in case of error is always 0, which means 'success'. Change it to return -ENODEV instead. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
2016-07-14 18:10:46 +08:00
return -ENODEV;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
}
/* Setup MSI */
if (IS_ENABLED(CONFIG_PCI_MSI)) {
PCI: xilinx: Keep both legacy and MSI interrupt domain references When built with MSI support, the legacy domain reference was being overwritten with MSI. Create two separate domains for MSI and legacy interrupts. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-01 18:14:41 +08:00
port->msi_domain = irq_domain_add_linear(node,
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
XILINX_NUM_MSI_IRQS,
&msi_domain_ops,
&xilinx_pcie_msi_chip);
PCI: xilinx: Keep both legacy and MSI interrupt domain references When built with MSI support, the legacy domain reference was being overwritten with MSI. Create two separate domains for MSI and legacy interrupts. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-01 18:14:41 +08:00
if (!port->msi_domain) {
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
dev_err(dev, "Failed to get a MSI IRQ domain\n");
PCI: xilinx: Fix return value in case of error In xilinx_pcie_init_irq_domain(), the pattern used to check and return error is: if (!var) { dev_err(...); return PTR_ERR(var); } So the returned value in case of error is always 0, which means 'success'. Change it to return -ENODEV instead. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
2016-07-14 18:10:46 +08:00
return -ENODEV;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
}
xilinx_pcie_enable_msi(port);
}
return 0;
}
/**
* xilinx_pcie_init_port - Initialize hardware
* @port: PCIe port information
*/
static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
{
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
struct device *dev = port->dev;
PCI: xilinx: Rename xilinx_pcie_link_is_up() to xilinx_pcie_link_up() Rename xilinx_pcie_link_is_up() to xilinx_pcie_link_up() to follow the convention of other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2017-11-10 06:19:47 +08:00
if (xilinx_pcie_link_up(port))
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_info(dev, "PCIe Link is UP\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
else
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
dev_info(dev, "PCIe Link is DOWN\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
/* Disable all interrupts */
pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK,
XILINX_PCIE_REG_IMR);
/* Clear pending interrupts */
pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) &
XILINX_PCIE_IMR_ALL_MASK,
XILINX_PCIE_REG_IDR);
PCI: xilinx: Don't enable config completion interrupts The Xilinx AXI bridge for PCI Express device provides interrupts indicating the completion of config space accesses. We have previously enabled/unmasked them but do nothing with them besides acknowledge them. Leave the interrupts masked in order to avoid servicing a large number of pointless interrupts during boot. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16 05:25:25 +08:00
/* Enable all interrupts we handle */
pcie_write(port, XILINX_PCIE_IMR_ENABLE_MASK, XILINX_PCIE_REG_IMR);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
/* Enable the Bridge enable bit */
pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |
XILINX_PCIE_REG_RPSC_BEN,
XILINX_PCIE_REG_RPSC);
}
/**
* xilinx_pcie_parse_dt - Parse Device tree
* @port: PCIe port information
*
* Return: '0' on success and error value on failure
*/
static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
{
struct device *dev = port->dev;
struct device_node *node = dev->of_node;
struct resource regs;
const char *type;
int err;
type = of_get_property(node, "device_type", NULL);
if (!type || strcmp(type, "pci")) {
dev_err(dev, "invalid \"device_type\" %s\n", type);
return -EINVAL;
}
err = of_address_to_resource(node, 0, &regs);
if (err) {
dev_err(dev, "missing \"reg\" property\n");
return err;
}
PCI: xilinx: Update PCI config space remap function PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
2017-04-20 00:48:57 +08:00
port->reg_base = devm_pci_remap_cfg_resource(dev, &regs);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (IS_ERR(port->reg_base))
return PTR_ERR(port->reg_base);
port->irq = irq_of_parse_and_map(node, 0);
err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler,
PCI: host: Mark PCIe/PCI (MSI) IRQ cascade handlers as IRQF_NO_THREAD On -RT and if kernel is booting with "threadirqs" cmd line parameter, PCIe/PCI (MSI) IRQ cascade handlers (like dra7xx_pcie_msi_irq_handler()) will be forced threaded and, as result, will generate warnings like this: WARNING: CPU: 1 PID: 82 at kernel/irq/handle.c:150 handle_irq_event_percpu+0x14c/0x174() irq 460 handler irq_default_primary_handler+0x0/0x14 enabled interrupts Backtrace: (warn_slowpath_common) from (warn_slowpath_fmt+0x38/0x40) (warn_slowpath_fmt) from (handle_irq_event_percpu+0x14c/0x174) (handle_irq_event_percpu) from (handle_irq_event+0x84/0xb8) (handle_irq_event) from (handle_simple_irq+0x90/0x118) (handle_simple_irq) from (generic_handle_irq+0x30/0x44) (generic_handle_irq) from (dra7xx_pcie_msi_irq_handler+0x7c/0x8c) (dra7xx_pcie_msi_irq_handler) from (irq_forced_thread_fn+0x28/0x5c) (irq_forced_thread_fn) from (irq_thread+0x128/0x204) This happens because all of them invoke generic_handle_irq() from the requested handler. generic_handle_irq() grabs raw_locks and thus needs to run in raw-IRQ context. This issue was originally reproduced on TI dra7-evem, but, as was identified during discussion [1], other hosts can also suffer from this issue. Fix all them at once by marking PCIe/PCI (MSI) IRQ cascade handlers IRQF_NO_THREAD explicitly. [1] http://lkml.kernel.org/r/1448027966-21610-1-git-send-email-grygorii.strashko@ti.com [bhelgaas: add stable tag, fix typos] Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> (for imx6) CC: stable@vger.kernel.org CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Kukjin Kim <kgene@kernel.org> CC: Krzysztof Kozlowski <k.kozlowski@samsung.com> CC: Richard Zhu <Richard.Zhu@freescale.com> CC: Thierry Reding <thierry.reding@gmail.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Alexandre Courbot <gnurou@gmail.com> CC: Simon Horman <horms@verge.net.au> CC: Pratyush Anand <pratyush.anand@gmail.com> CC: Michal Simek <michal.simek@xilinx.com> CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com> CC: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2015-12-11 03:18:20 +08:00
IRQF_SHARED | IRQF_NO_THREAD,
"xilinx-pcie", port);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (err) {
dev_err(dev, "unable to request irq %d\n", port->irq);
return err;
}
return 0;
}
/**
* xilinx_pcie_probe - Probe function
* @pdev: Platform device pointer
*
* Return: '0' on success and error value on failure
*/
static int xilinx_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
struct xilinx_pcie_port *port;
PCI: xilinx: Configure PCIe MPS settings Make sure PCIe MPS settings are valid when we enumerate a new hierarchy. Based-on-patch-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-09 05:37:47 +08:00
struct pci_bus *bus, *child;
PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge() The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI xilinx host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com>
2017-06-29 04:13:59 +08:00
struct pci_host_bridge *bridge;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
int err;
PCI: xilinx: Use of_pci_get_host_bridge_resources() to parse DT Use the new of_pci_get_host_bridge_resources() API in place of the PCI OF DT parser. [bhelgaas: revise changelog to show similarity to 0021d22b73d6 ("PCI: designware: Use of_pci_get_host_bridge_resources() to parse DT")] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-02-12 00:28:07 +08:00
resource_size_t iobase = 0;
LIST_HEAD(res);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (!dev->of_node)
return -ENODEV;
PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge() The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI xilinx host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com>
2017-06-29 04:13:59 +08:00
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
if (!bridge)
return -ENODEV;
port = pci_host_bridge_priv(bridge);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
port->dev = dev;
err = xilinx_pcie_parse_dt(port);
if (err) {
dev_err(dev, "Parsing DT failed\n");
return err;
}
xilinx_pcie_init_port(port);
err = xilinx_pcie_init_irq_domain(port);
if (err) {
dev_err(dev, "Failed creating IRQ Domain\n");
return err;
}
PCI: xilinx: Use of_pci_get_host_bridge_resources() to parse DT Use the new of_pci_get_host_bridge_resources() API in place of the PCI OF DT parser. [bhelgaas: revise changelog to show similarity to 0021d22b73d6 ("PCI: designware: Use of_pci_get_host_bridge_resources() to parse DT")] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-02-12 00:28:07 +08:00
err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff, &res,
&iobase);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
if (err) {
PCI: xilinx: Use of_pci_get_host_bridge_resources() to parse DT Use the new of_pci_get_host_bridge_resources() API in place of the PCI OF DT parser. [bhelgaas: revise changelog to show similarity to 0021d22b73d6 ("PCI: designware: Use of_pci_get_host_bridge_resources() to parse DT")] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-02-12 00:28:07 +08:00
dev_err(dev, "Getting bridge resources failed\n");
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
return err;
}
PCI: xilinx: Request host bridge window resources Request host bridge window resources so they appear in ioport_resource and iomem_resource and are reflected in /proc/ioports and /proc/iomem. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-05-29 07:27:03 +08:00
err = devm_request_pci_bus_resources(dev, &res);
if (err)
goto error;
PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge() The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI xilinx host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com>
2017-06-29 04:13:59 +08:00
list_splice_init(&res, &bridge->windows);
bridge->dev.parent = dev;
bridge->sysdata = port;
bridge->busnr = 0;
bridge->ops = &xilinx_pcie_ops;
PCI: xilinx: Drop pci_fixup_irqs() Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation. Drop pci_fixup_irqs() usage from PCI xilinx host bridge driver. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Michal Simek <michal.simek@xilinx.com>
2017-06-29 04:14:06 +08:00
bridge->map_irq = of_irq_parse_and_map_pci;
bridge->swizzle_irq = pci_common_swizzle;
PCI: xilinx: Save MSI controller in pci_sys_data Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every PCI bus in .add_bus(). [bhelgaas: use xilinx_pcie_msi_chip, not xilinx_pcie_msi_controller] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-12 06:45:31 +08:00
#ifdef CONFIG_PCI_MSI
PCI: xilinx: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-07 02:44:42 +08:00
xilinx_pcie_msi_chip.dev = dev;
PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge() The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI xilinx host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com>
2017-06-29 04:13:59 +08:00
bridge->msi = &xilinx_pcie_msi_chip;
PCI: xilinx: Save MSI controller in pci_sys_data Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every PCI bus in .add_bus(). [bhelgaas: use xilinx_pcie_msi_chip, not xilinx_pcie_msi_controller] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-12 06:45:31 +08:00
#endif
PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge() The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI xilinx host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com>
2017-06-29 04:13:59 +08:00
err = pci_scan_root_bus_bridge(bridge);
if (err < 0)
goto error;
bus = bridge->bus;
PCI: xilinx: Remove dependency on ARM-specific struct hw_pci The Xilinx PCIe host controller driver uses pci_common_init_dev(), which is ARM-specific and requires the ARM struct hw_pci. The part of pci_common_init_dev() that is needed is limited and can be done here without using hw_pci. Create and scan the root bus directly without using the ARM pci_common_init_dev() interface. [bhelgaas: revise changelog to show similarity to 79953dd22c1d ("PCI: rcar: Remove dependency on ARM-specific struct hw_pci")] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-02-12 00:28:08 +08:00
pci_assign_unassigned_bus_resources(bus);
PCI: xilinx: Configure PCIe MPS settings Make sure PCIe MPS settings are valid when we enumerate a new hierarchy. Based-on-patch-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-09 05:37:47 +08:00
list_for_each_entry(child, &bus->children, node)
pcie_bus_configure_settings(child);
PCI: xilinx: Remove dependency on ARM-specific struct hw_pci The Xilinx PCIe host controller driver uses pci_common_init_dev(), which is ARM-specific and requires the ARM struct hw_pci. The part of pci_common_init_dev() that is needed is limited and can be done here without using hw_pci. Create and scan the root bus directly without using the ARM pci_common_init_dev() interface. [bhelgaas: revise changelog to show similarity to 79953dd22c1d ("PCI: rcar: Remove dependency on ARM-specific struct hw_pci")] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-02-12 00:28:08 +08:00
pci_bus_add_devices(bus);
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
return 0;
PCI: xilinx: Free bridge resource list on failure of_pci_get_host_bridge_resources() allocates a list of resources for host bridge windows. If we fail after allocating that list, free it before we return error. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-06-01 00:49:14 +08:00
error:
pci_free_resource_list(&res);
return err;
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
}
PCI: xilinx: Make of_device_ids const of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. File size before: text data bss dec hex filename 195 600 0 795 31b drivers/pci/host/pcie-xilinx.o File size after constify xilinx_pcie_of_match: text data bss dec hex filename 595 184 0 779 30b drivers/pci/host/pcie-xilinx.o Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-06-20 13:47:48 +08:00
static const struct of_device_id xilinx_pcie_of_match[] = {
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-21 00:26:02 +08:00
{ .compatible = "xlnx,axi-pcie-host-1.00.a", },
{}
};
static struct platform_driver xilinx_pcie_driver = {
.driver = {
.name = "xilinx-pcie",
.of_match_table = xilinx_pcie_of_match,
.suppress_bind_attrs = true,
},
.probe = xilinx_pcie_probe,
};
PCI: xilinx: Make explicitly non-modular This code is not being built as a module by anyone: drivers/pci/host/Kconfig:config PCIE_XILINX drivers/pci/host/Kconfig: bool "Xilinx AXI PCIe host bridge support" Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(), etc., so that when reading the driver there is no doubt it is builtin-only. The information is preserved in comments at the top of the file. Note that for non-modular code, builtin_platform_driver() uses the same init level priority as module_platform_driver(), so this doesn't change init ordering. [bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com> CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
2016-08-25 04:57:49 +08:00
builtin_platform_driver(xilinx_pcie_driver);
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