2009-12-11 17:24:15 +08:00
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/*
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* Copyright 2007 Stephane Marchesin
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drm.h"
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#include "nouveau_drv.h"
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static uint32_t nv04_graph_ctx_regs[] = {
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NV04_PGRAPH_CTX_SWITCH1,
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NV04_PGRAPH_CTX_SWITCH2,
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NV04_PGRAPH_CTX_SWITCH3,
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NV04_PGRAPH_CTX_SWITCH4,
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NV04_PGRAPH_CTX_CACHE1,
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NV04_PGRAPH_CTX_CACHE2,
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NV04_PGRAPH_CTX_CACHE3,
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NV04_PGRAPH_CTX_CACHE4,
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0x00400184,
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0x004001a4,
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0x004001c4,
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0x004001e4,
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0x00400188,
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0x004001a8,
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0x004001c8,
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0x004001e8,
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0x0040018c,
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0x004001ac,
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0x004001cc,
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0x004001ec,
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0x00400190,
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0x004001b0,
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0x004001d0,
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0x004001f0,
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0x00400194,
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0x004001b4,
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0x004001d4,
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0x004001f4,
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0x00400198,
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0x004001b8,
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0x004001d8,
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0x004001f8,
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0x0040019c,
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0x004001bc,
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0x004001dc,
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0x004001fc,
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0x00400174,
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NV04_PGRAPH_DMA_START_0,
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NV04_PGRAPH_DMA_START_1,
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NV04_PGRAPH_DMA_LENGTH,
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NV04_PGRAPH_DMA_MISC,
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NV04_PGRAPH_DMA_PITCH,
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NV04_PGRAPH_BOFFSET0,
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NV04_PGRAPH_BBASE0,
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NV04_PGRAPH_BLIMIT0,
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NV04_PGRAPH_BOFFSET1,
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NV04_PGRAPH_BBASE1,
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NV04_PGRAPH_BLIMIT1,
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NV04_PGRAPH_BOFFSET2,
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NV04_PGRAPH_BBASE2,
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NV04_PGRAPH_BLIMIT2,
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NV04_PGRAPH_BOFFSET3,
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NV04_PGRAPH_BBASE3,
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NV04_PGRAPH_BLIMIT3,
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NV04_PGRAPH_BOFFSET4,
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NV04_PGRAPH_BBASE4,
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NV04_PGRAPH_BLIMIT4,
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NV04_PGRAPH_BOFFSET5,
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NV04_PGRAPH_BBASE5,
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NV04_PGRAPH_BLIMIT5,
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NV04_PGRAPH_BPITCH0,
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NV04_PGRAPH_BPITCH1,
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NV04_PGRAPH_BPITCH2,
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NV04_PGRAPH_BPITCH3,
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NV04_PGRAPH_BPITCH4,
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NV04_PGRAPH_SURFACE,
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NV04_PGRAPH_STATE,
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NV04_PGRAPH_BSWIZZLE2,
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NV04_PGRAPH_BSWIZZLE5,
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NV04_PGRAPH_BPIXEL,
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NV04_PGRAPH_NOTIFY,
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NV04_PGRAPH_PATT_COLOR0,
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NV04_PGRAPH_PATT_COLOR1,
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NV04_PGRAPH_PATT_COLORRAM+0x00,
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NV04_PGRAPH_PATT_COLORRAM+0x01,
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NV04_PGRAPH_PATT_COLORRAM+0x02,
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NV04_PGRAPH_PATT_COLORRAM+0x03,
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NV04_PGRAPH_PATT_COLORRAM+0x04,
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NV04_PGRAPH_PATT_COLORRAM+0x05,
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NV04_PGRAPH_PATT_COLORRAM+0x06,
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NV04_PGRAPH_PATT_COLORRAM+0x07,
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NV04_PGRAPH_PATT_COLORRAM+0x08,
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NV04_PGRAPH_PATT_COLORRAM+0x09,
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NV04_PGRAPH_PATT_COLORRAM+0x0A,
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NV04_PGRAPH_PATT_COLORRAM+0x0B,
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NV04_PGRAPH_PATT_COLORRAM+0x0C,
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NV04_PGRAPH_PATT_COLORRAM+0x0D,
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NV04_PGRAPH_PATT_COLORRAM+0x0E,
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NV04_PGRAPH_PATT_COLORRAM+0x0F,
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NV04_PGRAPH_PATT_COLORRAM+0x10,
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NV04_PGRAPH_PATT_COLORRAM+0x11,
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NV04_PGRAPH_PATT_COLORRAM+0x12,
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NV04_PGRAPH_PATT_COLORRAM+0x13,
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NV04_PGRAPH_PATT_COLORRAM+0x14,
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NV04_PGRAPH_PATT_COLORRAM+0x15,
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NV04_PGRAPH_PATT_COLORRAM+0x16,
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NV04_PGRAPH_PATT_COLORRAM+0x17,
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NV04_PGRAPH_PATT_COLORRAM+0x18,
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NV04_PGRAPH_PATT_COLORRAM+0x19,
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NV04_PGRAPH_PATT_COLORRAM+0x1A,
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NV04_PGRAPH_PATT_COLORRAM+0x1B,
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NV04_PGRAPH_PATT_COLORRAM+0x1C,
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NV04_PGRAPH_PATT_COLORRAM+0x1D,
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NV04_PGRAPH_PATT_COLORRAM+0x1E,
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NV04_PGRAPH_PATT_COLORRAM+0x1F,
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NV04_PGRAPH_PATT_COLORRAM+0x20,
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NV04_PGRAPH_PATT_COLORRAM+0x21,
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NV04_PGRAPH_PATT_COLORRAM+0x22,
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NV04_PGRAPH_PATT_COLORRAM+0x23,
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NV04_PGRAPH_PATT_COLORRAM+0x24,
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NV04_PGRAPH_PATT_COLORRAM+0x25,
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NV04_PGRAPH_PATT_COLORRAM+0x26,
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NV04_PGRAPH_PATT_COLORRAM+0x27,
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NV04_PGRAPH_PATT_COLORRAM+0x28,
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NV04_PGRAPH_PATT_COLORRAM+0x29,
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NV04_PGRAPH_PATT_COLORRAM+0x2A,
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NV04_PGRAPH_PATT_COLORRAM+0x2B,
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NV04_PGRAPH_PATT_COLORRAM+0x2C,
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NV04_PGRAPH_PATT_COLORRAM+0x2D,
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NV04_PGRAPH_PATT_COLORRAM+0x2E,
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NV04_PGRAPH_PATT_COLORRAM+0x2F,
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NV04_PGRAPH_PATT_COLORRAM+0x30,
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NV04_PGRAPH_PATT_COLORRAM+0x31,
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NV04_PGRAPH_PATT_COLORRAM+0x32,
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NV04_PGRAPH_PATT_COLORRAM+0x33,
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NV04_PGRAPH_PATT_COLORRAM+0x34,
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NV04_PGRAPH_PATT_COLORRAM+0x35,
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NV04_PGRAPH_PATT_COLORRAM+0x36,
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NV04_PGRAPH_PATT_COLORRAM+0x37,
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NV04_PGRAPH_PATT_COLORRAM+0x38,
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NV04_PGRAPH_PATT_COLORRAM+0x39,
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NV04_PGRAPH_PATT_COLORRAM+0x3A,
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NV04_PGRAPH_PATT_COLORRAM+0x3B,
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NV04_PGRAPH_PATT_COLORRAM+0x3C,
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NV04_PGRAPH_PATT_COLORRAM+0x3D,
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NV04_PGRAPH_PATT_COLORRAM+0x3E,
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NV04_PGRAPH_PATT_COLORRAM+0x3F,
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NV04_PGRAPH_PATTERN,
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0x0040080c,
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NV04_PGRAPH_PATTERN_SHAPE,
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0x00400600,
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NV04_PGRAPH_ROP3,
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NV04_PGRAPH_CHROMA,
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NV04_PGRAPH_BETA_AND,
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NV04_PGRAPH_BETA_PREMULT,
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NV04_PGRAPH_CONTROL0,
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NV04_PGRAPH_CONTROL1,
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NV04_PGRAPH_CONTROL2,
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NV04_PGRAPH_BLEND,
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NV04_PGRAPH_STORED_FMT,
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NV04_PGRAPH_SOURCE_COLOR,
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0x00400560,
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0x00400568,
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0x00400564,
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0x0040056c,
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0x00400400,
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0x00400480,
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0x00400404,
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0x00400484,
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0x00400408,
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0x00400488,
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0x0040040c,
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0x0040048c,
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0x00400410,
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0x00400490,
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0x00400414,
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0x00400494,
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0x00400418,
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0x00400498,
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0x0040041c,
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0x0040049c,
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0x00400420,
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0x004004a0,
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0x00400424,
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0x004004a4,
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0x00400428,
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0x004004a8,
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0x0040042c,
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0x004004ac,
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0x00400430,
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0x004004b0,
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0x00400434,
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0x004004b4,
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0x00400438,
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0x004004b8,
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0x0040043c,
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0x004004bc,
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0x00400440,
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0x004004c0,
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0x00400444,
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0x004004c4,
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0x00400448,
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0x004004c8,
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0x0040044c,
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0x004004cc,
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0x00400450,
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0x004004d0,
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0x00400454,
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0x004004d4,
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0x00400458,
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0x004004d8,
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0x0040045c,
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0x004004dc,
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0x00400460,
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0x004004e0,
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0x00400464,
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0x004004e4,
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0x00400468,
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0x004004e8,
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0x0040046c,
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0x004004ec,
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0x00400470,
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0x004004f0,
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0x00400474,
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0x004004f4,
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0x00400478,
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0x004004f8,
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0x0040047c,
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0x004004fc,
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0x0040053c,
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0x00400544,
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0x00400540,
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0x00400548,
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0x00400560,
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0x00400568,
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0x00400564,
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0x0040056c,
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0x00400534,
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0x00400538,
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0x00400514,
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0x00400518,
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0x0040051c,
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0x00400520,
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0x00400524,
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0x00400528,
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0x0040052c,
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0x00400530,
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0x00400d00,
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0x00400d40,
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0x00400d80,
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0x00400d04,
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0x00400d44,
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0x00400d84,
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0x00400d08,
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0x00400d48,
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0x00400d88,
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0x00400d0c,
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0x00400d4c,
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0x00400d8c,
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0x00400d10,
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0x00400d50,
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0x00400d90,
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0x00400d14,
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0x00400d54,
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0x00400d94,
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0x00400d18,
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0x00400d58,
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0x00400d98,
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0x00400d1c,
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0x00400d5c,
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0x00400d9c,
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0x00400d20,
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0x00400d60,
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0x00400da0,
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0x00400d24,
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0x00400d64,
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0x00400da4,
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0x00400d28,
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0x00400d68,
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0x00400da8,
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|
0x00400d2c,
|
|
|
|
|
0x00400d6c,
|
|
|
|
|
0x00400dac,
|
|
|
|
|
0x00400d30,
|
|
|
|
|
0x00400d70,
|
|
|
|
|
0x00400db0,
|
|
|
|
|
0x00400d34,
|
|
|
|
|
0x00400d74,
|
|
|
|
|
0x00400db4,
|
|
|
|
|
0x00400d38,
|
|
|
|
|
0x00400d78,
|
|
|
|
|
0x00400db8,
|
|
|
|
|
0x00400d3c,
|
|
|
|
|
0x00400d7c,
|
|
|
|
|
0x00400dbc,
|
|
|
|
|
0x00400590,
|
|
|
|
|
0x00400594,
|
|
|
|
|
0x00400598,
|
|
|
|
|
0x0040059c,
|
|
|
|
|
0x004005a8,
|
|
|
|
|
0x004005ac,
|
|
|
|
|
0x004005b0,
|
|
|
|
|
0x004005b4,
|
|
|
|
|
0x004005c0,
|
|
|
|
|
0x004005c4,
|
|
|
|
|
0x004005c8,
|
|
|
|
|
0x004005cc,
|
|
|
|
|
0x004005d0,
|
|
|
|
|
0x004005d4,
|
|
|
|
|
0x004005d8,
|
|
|
|
|
0x004005dc,
|
|
|
|
|
0x004005e0,
|
|
|
|
|
NV04_PGRAPH_PASSTHRU_0,
|
|
|
|
|
NV04_PGRAPH_PASSTHRU_1,
|
|
|
|
|
NV04_PGRAPH_PASSTHRU_2,
|
|
|
|
|
NV04_PGRAPH_DVD_COLORFMT,
|
|
|
|
|
NV04_PGRAPH_SCALED_FORMAT,
|
|
|
|
|
NV04_PGRAPH_MISC24_0,
|
|
|
|
|
NV04_PGRAPH_MISC24_1,
|
|
|
|
|
NV04_PGRAPH_MISC24_2,
|
|
|
|
|
0x00400500,
|
|
|
|
|
0x00400504,
|
|
|
|
|
NV04_PGRAPH_VALID1,
|
|
|
|
|
NV04_PGRAPH_VALID2
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct graph_state {
|
|
|
|
|
int nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct nouveau_channel *
|
|
|
|
|
nv04_graph_channel(struct drm_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
|
int chid = dev_priv->engine.fifo.channels;
|
|
|
|
|
|
|
|
|
|
if (nv_rd32(dev, NV04_PGRAPH_CTX_CONTROL) & 0x00010000)
|
|
|
|
|
chid = nv_rd32(dev, NV04_PGRAPH_CTX_USER) >> 24;
|
|
|
|
|
|
|
|
|
|
if (chid >= dev_priv->engine.fifo.channels)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
return dev_priv->fifos[chid];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
nv04_graph_context_switch(struct drm_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
|
struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
|
|
|
|
|
struct nouveau_channel *chan = NULL;
|
|
|
|
|
int chid;
|
|
|
|
|
|
|
|
|
|
pgraph->fifo_access(dev, false);
|
|
|
|
|
nouveau_wait_for_idle(dev);
|
|
|
|
|
|
|
|
|
|
/* If previous context is valid, we need to save it */
|
|
|
|
|
pgraph->unload_context(dev);
|
|
|
|
|
|
|
|
|
|
/* Load context for next channel */
|
|
|
|
|
chid = dev_priv->engine.fifo.channel_id(dev);
|
|
|
|
|
chan = dev_priv->fifos[chid];
|
|
|
|
|
if (chan)
|
|
|
|
|
nv04_graph_load_context(chan);
|
|
|
|
|
|
|
|
|
|
pgraph->fifo_access(dev, true);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int nv04_graph_create_context(struct nouveau_channel *chan)
|
|
|
|
|
{
|
|
|
|
|
struct graph_state *pgraph_ctx;
|
|
|
|
|
NV_DEBUG(chan->dev, "nv04_graph_context_create %d\n", chan->id);
|
|
|
|
|
|
|
|
|
|
chan->pgraph_ctx = pgraph_ctx = kzalloc(sizeof(*pgraph_ctx),
|
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
if (pgraph_ctx == NULL)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
/* dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; */
|
|
|
|
|
pgraph_ctx->nv04[0] = 0x0001ffff;
|
|
|
|
|
/* is it really needed ??? */
|
|
|
|
|
#if 0
|
|
|
|
|
dev_priv->fifos[channel].pgraph_ctx[1] =
|
|
|
|
|
nv_rd32(dev, NV_PGRAPH_DEBUG_4);
|
|
|
|
|
dev_priv->fifos[channel].pgraph_ctx[2] =
|
|
|
|
|
nv_rd32(dev, 0x004006b0);
|
|
|
|
|
#endif
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void nv04_graph_destroy_context(struct nouveau_channel *chan)
|
|
|
|
|
{
|
|
|
|
|
struct graph_state *pgraph_ctx = chan->pgraph_ctx;
|
|
|
|
|
|
|
|
|
|
kfree(pgraph_ctx);
|
|
|
|
|
chan->pgraph_ctx = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int nv04_graph_load_context(struct nouveau_channel *chan)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *dev = chan->dev;
|
|
|
|
|
struct graph_state *pgraph_ctx = chan->pgraph_ctx;
|
|
|
|
|
uint32_t tmp;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
|
|
|
|
|
nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
|
|
|
|
|
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_USER, chan->id << 24);
|
|
|
|
|
tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2);
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
nv04_graph_unload_context(struct drm_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
|
struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
|
|
|
|
|
struct nouveau_channel *chan = NULL;
|
|
|
|
|
struct graph_state *ctx;
|
|
|
|
|
uint32_t tmp;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
chan = pgraph->channel(dev);
|
|
|
|
|
if (!chan)
|
|
|
|
|
return 0;
|
|
|
|
|
ctx = chan->pgraph_ctx;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
|
|
|
|
|
ctx->nv04[i] = nv_rd32(dev, nv04_graph_ctx_regs[i]);
|
|
|
|
|
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
|
|
|
|
|
tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
|
|
|
|
|
tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int nv04_graph_init(struct drm_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
|
uint32_t tmp;
|
|
|
|
|
|
|
|
|
|
nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
|
|
|
|
|
~NV_PMC_ENABLE_PGRAPH);
|
|
|
|
|
nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
|
|
|
|
|
NV_PMC_ENABLE_PGRAPH);
|
|
|
|
|
|
|
|
|
|
/* Enable PGRAPH interrupts */
|
|
|
|
|
nv_wr32(dev, NV03_PGRAPH_INTR, 0xFFFFFFFF);
|
|
|
|
|
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
|
|
|
|
|
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_VALID1, 0);
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_VALID2, 0);
|
|
|
|
|
/*nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x000001FF);
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x1231c000);
|
|
|
|
|
/*1231C000 blob, 001 haiku*/
|
|
|
|
|
//*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x72111100);
|
|
|
|
|
/*0x72111100 blob , 01 haiku*/
|
|
|
|
|
/*nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f071);
|
|
|
|
|
/*haiku same*/
|
|
|
|
|
|
|
|
|
|
/*nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
|
|
|
|
|
/*haiku and blob 10d4*/
|
|
|
|
|
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF);
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100);
|
|
|
|
|
tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
|
|
|
|
|
tmp |= dev_priv->engine.fifo.channels << 24;
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
|
|
|
|
|
|
|
|
|
|
/* These don't belong here, they're part of a per-channel context */
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void nv04_graph_takedown(struct drm_device *dev)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
nv04_graph_fifo_access(struct drm_device *dev, bool enabled)
|
|
|
|
|
{
|
|
|
|
|
if (enabled)
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_FIFO,
|
|
|
|
|
nv_rd32(dev, NV04_PGRAPH_FIFO) | 1);
|
|
|
|
|
else
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_FIFO,
|
|
|
|
|
nv_rd32(dev, NV04_PGRAPH_FIFO) & ~1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
nv04_graph_mthd_set_ref(struct nouveau_channel *chan, int grclass,
|
|
|
|
|
int mthd, uint32_t data)
|
|
|
|
|
{
|
|
|
|
|
chan->fence.last_sequence_irq = data;
|
|
|
|
|
nouveau_fence_handler(chan->dev, chan->id);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
|
|
|
|
|
int mthd, uint32_t data)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *dev = chan->dev;
|
|
|
|
|
uint32_t instance = nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff;
|
|
|
|
|
int subc = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
|
|
|
|
|
uint32_t tmp;
|
|
|
|
|
|
|
|
|
|
tmp = nv_ri32(dev, instance);
|
|
|
|
|
tmp &= ~0x00038000;
|
|
|
|
|
tmp |= ((data & 7) << 15);
|
|
|
|
|
|
|
|
|
|
nv_wi32(dev, instance, tmp);
|
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp);
|
2009-12-15 04:38:17 +08:00
|
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
|
2009-12-11 17:24:15 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2009-12-26 09:09:36 +08:00
|
|
|
static struct nouveau_pgraph_object_method nv04_graph_mthds_sw[] = {
|
2009-12-11 17:24:15 +08:00
|
|
|
{ 0x0150, nv04_graph_mthd_set_ref },
|
|
|
|
|
{}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct nouveau_pgraph_object_method nv04_graph_mthds_set_operation[] = {
|
|
|
|
|
{ 0x02fc, nv04_graph_mthd_set_operation },
|
|
|
|
|
{},
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct nouveau_pgraph_object_class nv04_graph_grclass[] = {
|
2009-12-26 09:09:36 +08:00
|
|
|
{ 0x0039, false, NULL },
|
2009-12-11 17:24:15 +08:00
|
|
|
{ 0x004a, false, nv04_graph_mthds_set_operation }, /* gdirect */
|
|
|
|
|
{ 0x005f, false, nv04_graph_mthds_set_operation }, /* imageblit */
|
|
|
|
|
{ 0x0061, false, nv04_graph_mthds_set_operation }, /* ifc */
|
|
|
|
|
{ 0x0077, false, nv04_graph_mthds_set_operation }, /* sifm */
|
|
|
|
|
{ 0x0030, false, NULL }, /* null */
|
|
|
|
|
{ 0x0042, false, NULL }, /* surf2d */
|
|
|
|
|
{ 0x0043, false, NULL }, /* rop */
|
|
|
|
|
{ 0x0012, false, NULL }, /* beta1 */
|
|
|
|
|
{ 0x0072, false, NULL }, /* beta4 */
|
|
|
|
|
{ 0x0019, false, NULL }, /* cliprect */
|
|
|
|
|
{ 0x0044, false, NULL }, /* pattern */
|
|
|
|
|
{ 0x0052, false, NULL }, /* swzsurf */
|
|
|
|
|
{ 0x0053, false, NULL }, /* surf3d */
|
|
|
|
|
{ 0x0054, false, NULL }, /* tex_tri */
|
|
|
|
|
{ 0x0055, false, NULL }, /* multitex_tri */
|
2009-12-26 09:09:36 +08:00
|
|
|
{ 0x506e, true, nv04_graph_mthds_sw },
|
2009-12-11 17:24:15 +08:00
|
|
|
{}
|
|
|
|
|
};
|
|
|
|
|
|
