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68 lines
2.0 KiB
C
68 lines
2.0 KiB
C
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2014-2018 Intel Corporation
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*/
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#ifndef _INTEL_LRC_REG_H_
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#define _INTEL_LRC_REG_H_
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#include <linux/types.h>
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/* GEN8+ Reg State Context */
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#define CTX_LRI_HEADER_0 0x01
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#define CTX_CONTEXT_CONTROL 0x02
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#define CTX_RING_HEAD 0x04
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#define CTX_RING_TAIL 0x06
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#define CTX_RING_BUFFER_START 0x08
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#define CTX_RING_BUFFER_CONTROL 0x0a
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#define CTX_BB_HEAD_U 0x0c
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#define CTX_BB_HEAD_L 0x0e
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#define CTX_BB_STATE 0x10
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#define CTX_SECOND_BB_HEAD_U 0x12
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#define CTX_SECOND_BB_HEAD_L 0x14
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#define CTX_SECOND_BB_STATE 0x16
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#define CTX_BB_PER_CTX_PTR 0x18
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#define CTX_RCS_INDIRECT_CTX 0x1a
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#define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
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#define CTX_LRI_HEADER_1 0x21
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#define CTX_CTX_TIMESTAMP 0x22
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#define CTX_PDP3_UDW 0x24
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#define CTX_PDP3_LDW 0x26
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#define CTX_PDP2_UDW 0x28
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#define CTX_PDP2_LDW 0x2a
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#define CTX_PDP1_UDW 0x2c
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#define CTX_PDP1_LDW 0x2e
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#define CTX_PDP0_UDW 0x30
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#define CTX_PDP0_LDW 0x32
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#define CTX_LRI_HEADER_2 0x41
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#define CTX_R_PWR_CLK_STATE 0x42
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#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
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#define CTX_REG(reg_state, pos, reg, val) do { \
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u32 *reg_state__ = (reg_state); \
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const u32 pos__ = (pos); \
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(reg_state__)[(pos__) + 0] = i915_mmio_reg_offset(reg); \
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(reg_state__)[(pos__) + 1] = (val); \
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} while (0)
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#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
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u32 *reg_state__ = (reg_state); \
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const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \
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(reg_state__)[CTX_PDP ## n ## _UDW + 1] = upper_32_bits(addr__); \
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(reg_state__)[CTX_PDP ## n ## _LDW + 1] = lower_32_bits(addr__); \
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} while (0)
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#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
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u32 *reg_state__ = (reg_state); \
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const u64 addr__ = px_dma(&ppgtt->pml4); \
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(reg_state__)[CTX_PDP0_UDW + 1] = upper_32_bits(addr__); \
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(reg_state__)[CTX_PDP0_LDW + 1] = lower_32_bits(addr__); \
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} while (0)
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#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
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#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
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#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19
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#endif /* _INTEL_LRC_REG_H_ */
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