2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
|
|
* for more details.
|
|
|
|
*
|
|
|
|
* Copyright (C) 2003 Ralf Baechle
|
|
|
|
*/
|
|
|
|
#ifndef _ASM_ASMMACRO_H
|
|
|
|
#define _ASM_ASMMACRO_H
|
2005-09-04 06:56:17 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <asm/hazards.h>
|
2005-09-04 06:56:17 +08:00
|
|
|
|
2005-09-04 06:56:16 +08:00
|
|
|
#ifdef CONFIG_32BIT
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <asm/asmmacro-32.h>
|
|
|
|
#endif
|
2005-09-04 06:56:16 +08:00
|
|
|
#ifdef CONFIG_64BIT
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <asm/asmmacro-64.h>
|
|
|
|
#endif
|
2006-04-05 16:45:45 +08:00
|
|
|
#ifdef CONFIG_MIPS_MT_SMTC
|
|
|
|
#include <asm/mipsmtregs.h>
|
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-04-05 16:45:45 +08:00
|
|
|
#ifdef CONFIG_MIPS_MT_SMTC
|
|
|
|
.macro local_irq_enable reg=t0
|
|
|
|
mfc0 \reg, CP0_TCSTATUS
|
|
|
|
ori \reg, \reg, TCSTATUS_IXMT
|
|
|
|
xori \reg, \reg, TCSTATUS_IXMT
|
|
|
|
mtc0 \reg, CP0_TCSTATUS
|
2006-06-04 05:40:15 +08:00
|
|
|
_ehb
|
2006-04-05 16:45:45 +08:00
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro local_irq_disable reg=t0
|
|
|
|
mfc0 \reg, CP0_TCSTATUS
|
|
|
|
ori \reg, \reg, TCSTATUS_IXMT
|
|
|
|
mtc0 \reg, CP0_TCSTATUS
|
2006-06-04 05:40:15 +08:00
|
|
|
_ehb
|
2006-04-05 16:45:45 +08:00
|
|
|
.endm
|
2008-12-11 00:37:25 +08:00
|
|
|
#elif defined(CONFIG_CPU_MIPSR2)
|
|
|
|
.macro local_irq_enable reg=t0
|
|
|
|
ei
|
|
|
|
irq_enable_hazard
|
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro local_irq_disable reg=t0
|
|
|
|
di
|
|
|
|
irq_disable_hazard
|
|
|
|
.endm
|
2006-04-05 16:45:45 +08:00
|
|
|
#else
|
2005-04-17 06:20:36 +08:00
|
|
|
.macro local_irq_enable reg=t0
|
|
|
|
mfc0 \reg, CP0_STATUS
|
|
|
|
ori \reg, \reg, 1
|
|
|
|
mtc0 \reg, CP0_STATUS
|
|
|
|
irq_enable_hazard
|
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro local_irq_disable reg=t0
|
|
|
|
mfc0 \reg, CP0_STATUS
|
|
|
|
ori \reg, \reg, 1
|
|
|
|
xori \reg, \reg, 1
|
|
|
|
mtc0 \reg, CP0_STATUS
|
|
|
|
irq_disable_hazard
|
|
|
|
.endm
|
2006-04-05 16:45:45 +08:00
|
|
|
#endif /* CONFIG_MIPS_MT_SMTC */
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-04-05 16:45:45 +08:00
|
|
|
/*
|
|
|
|
* Temporary until all gas have MT ASE support
|
|
|
|
*/
|
|
|
|
.macro DMT reg=0
|
2007-10-12 06:46:15 +08:00
|
|
|
.word 0x41600bc1 | (\reg << 16)
|
2006-04-05 16:45:45 +08:00
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro EMT reg=0
|
2007-10-12 06:46:15 +08:00
|
|
|
.word 0x41600be1 | (\reg << 16)
|
2006-04-05 16:45:45 +08:00
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro DVPE reg=0
|
2007-10-12 06:46:15 +08:00
|
|
|
.word 0x41600001 | (\reg << 16)
|
2006-04-05 16:45:45 +08:00
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro EVPE reg=0
|
2007-10-12 06:46:15 +08:00
|
|
|
.word 0x41600021 | (\reg << 16)
|
2006-04-05 16:45:45 +08:00
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro MFTR rt=0, rd=0, u=0, sel=0
|
2007-10-12 06:46:15 +08:00
|
|
|
.word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
|
2006-04-05 16:45:45 +08:00
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro MTTR rt=0, rd=0, u=0, sel=0
|
2007-10-12 06:46:15 +08:00
|
|
|
.word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
|
2006-04-05 16:45:45 +08:00
|
|
|
.endm
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#endif /* _ASM_ASMMACRO_H */
|