2023-05-10 17:25:34 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2022-04-05 21:54:19 +08:00
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//
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// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
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//
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// Copyright 2019-2022 Cirrus Logic, Inc.
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//
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// Author: James Schulman <james.schulman@cirrus.com>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include "cs35l45.h"
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static const struct reg_sequence cs35l45_patch[] = {
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{ 0x00000040, 0x00000055 },
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{ 0x00000040, 0x000000AA },
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{ 0x00000044, 0x00000055 },
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{ 0x00000044, 0x000000AA },
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{ 0x00006480, 0x0830500A },
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{ 0x00007C60, 0x1000850B },
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{ CS35L45_BOOST_OV_CFG, 0x007000D0 },
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{ CS35L45_LDPM_CONFIG, 0x0001B636 },
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{ 0x00002C08, 0x00000009 },
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{ 0x00006850, 0x0A30FFC4 },
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{ 0x00003820, 0x00040100 },
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{ 0x00003824, 0x00000000 },
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{ 0x00007CFC, 0x62870004 },
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{ 0x00007C60, 0x1001850B },
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{ 0x00000040, 0x00000000 },
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{ 0x00000044, 0x00000000 },
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{ CS35L45_BOOST_CCM_CFG, 0xF0000003 },
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{ CS35L45_BOOST_DCM_CFG, 0x08710220 },
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{ CS35L45_ERROR_RELEASE, 0x00200000 },
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};
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int cs35l45_apply_patch(struct cs35l45_private *cs35l45)
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{
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return regmap_register_patch(cs35l45->regmap, cs35l45_patch,
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ARRAY_SIZE(cs35l45_patch));
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}
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2023-02-15 18:58:18 +08:00
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EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45);
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2022-04-05 21:54:19 +08:00
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static const struct reg_default cs35l45_defaults[] = {
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{ CS35L45_BLOCK_ENABLES, 0x00003323 },
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{ CS35L45_BLOCK_ENABLES2, 0x00000010 },
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2023-03-15 23:47:18 +08:00
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{ CS35L45_SYNC_GPIO1, 0x00000007 },
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{ CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005 },
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{ CS35L45_GPIO3, 0x00000005 },
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2023-03-15 23:47:21 +08:00
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{ CS35L45_PWRMGT_CTL, 0x00000000 },
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2023-03-15 23:47:22 +08:00
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{ CS35L45_WAKESRC_CTL, 0x00000008 },
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{ CS35L45_WKI2C_CTL, 0x00000030 },
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2022-04-05 21:54:19 +08:00
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{ CS35L45_REFCLK_INPUT, 0x00000510 },
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{ CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 },
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{ CS35L45_ASP_ENABLES1, 0x00000000 },
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{ CS35L45_ASP_CONTROL1, 0x00000028 },
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{ CS35L45_ASP_CONTROL2, 0x18180200 },
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{ CS35L45_ASP_CONTROL3, 0x00000002 },
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{ CS35L45_ASP_FRAME_CONTROL1, 0x03020100 },
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{ CS35L45_ASP_FRAME_CONTROL2, 0x00000004 },
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{ CS35L45_ASP_FRAME_CONTROL5, 0x00000100 },
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{ CS35L45_ASP_DATA_CONTROL1, 0x00000018 },
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{ CS35L45_ASP_DATA_CONTROL5, 0x00000018 },
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{ CS35L45_DACPCM1_INPUT, 0x00000008 },
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{ CS35L45_ASPTX1_INPUT, 0x00000018 },
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{ CS35L45_ASPTX2_INPUT, 0x00000019 },
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{ CS35L45_ASPTX3_INPUT, 0x00000020 },
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{ CS35L45_ASPTX4_INPUT, 0x00000028 },
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{ CS35L45_ASPTX5_INPUT, 0x00000048 },
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2023-03-15 23:47:21 +08:00
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{ CS35L45_DSP1_RX1_RATE, 0x00000001 },
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{ CS35L45_DSP1_RX2_RATE, 0x00000001 },
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{ CS35L45_DSP1_RX3_RATE, 0x00000001 },
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{ CS35L45_DSP1_RX4_RATE, 0x00000001 },
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{ CS35L45_DSP1_RX5_RATE, 0x00000001 },
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{ CS35L45_DSP1_RX6_RATE, 0x00000001 },
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{ CS35L45_DSP1_RX7_RATE, 0x00000001 },
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{ CS35L45_DSP1_RX8_RATE, 0x00000001 },
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{ CS35L45_DSP1_TX1_RATE, 0x00000001 },
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{ CS35L45_DSP1_TX2_RATE, 0x00000001 },
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{ CS35L45_DSP1_TX3_RATE, 0x00000001 },
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{ CS35L45_DSP1_TX4_RATE, 0x00000001 },
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{ CS35L45_DSP1_TX5_RATE, 0x00000001 },
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{ CS35L45_DSP1_TX6_RATE, 0x00000001 },
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{ CS35L45_DSP1_TX7_RATE, 0x00000001 },
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{ CS35L45_DSP1_TX8_RATE, 0x00000001 },
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{ CS35L45_DSP1RX1_INPUT, 0x00000008 },
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{ CS35L45_DSP1RX2_INPUT, 0x00000009 },
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{ CS35L45_DSP1RX3_INPUT, 0x00000018 },
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{ CS35L45_DSP1RX4_INPUT, 0x00000019 },
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{ CS35L45_DSP1RX5_INPUT, 0x00000020 },
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{ CS35L45_DSP1RX6_INPUT, 0x00000028 },
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{ CS35L45_DSP1RX7_INPUT, 0x0000003A },
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{ CS35L45_DSP1RX8_INPUT, 0x00000028 },
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2022-04-05 21:54:19 +08:00
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{ CS35L45_AMP_PCM_CONTROL, 0x00100000 },
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2023-09-01 00:20:40 +08:00
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{ CS35L45_AMP_GAIN, 0x00002300 },
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2023-03-15 23:47:20 +08:00
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{ CS35L45_IRQ1_CFG, 0x00000000 },
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{ CS35L45_IRQ1_MASK_1, 0xBFEFFFBF },
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{ CS35L45_IRQ1_MASK_2, 0xFFFFFFFF },
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{ CS35L45_IRQ1_MASK_3, 0xFFFF87FF },
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{ CS35L45_IRQ1_MASK_4, 0xF8FFFFFF },
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{ CS35L45_IRQ1_MASK_5, 0x0EF80000 },
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{ CS35L45_IRQ1_MASK_6, 0x00000000 },
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{ CS35L45_IRQ1_MASK_7, 0xFFFFFF78 },
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{ CS35L45_IRQ1_MASK_8, 0x00003FFF },
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{ CS35L45_IRQ1_MASK_9, 0x00000000 },
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{ CS35L45_IRQ1_MASK_10, 0x00000000 },
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{ CS35L45_IRQ1_MASK_11, 0x00000000 },
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{ CS35L45_IRQ1_MASK_12, 0x00000000 },
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{ CS35L45_IRQ1_MASK_13, 0x00000000 },
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{ CS35L45_IRQ1_MASK_14, 0x00000001 },
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{ CS35L45_IRQ1_MASK_15, 0x00000000 },
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{ CS35L45_IRQ1_MASK_16, 0x00000000 },
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{ CS35L45_IRQ1_MASK_17, 0x00000000 },
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{ CS35L45_IRQ1_MASK_18, 0x3FE5D0FF },
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2023-03-15 23:47:18 +08:00
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{ CS35L45_GPIO1_CTRL1, 0x81000001 },
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{ CS35L45_GPIO2_CTRL1, 0x81000001 },
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{ CS35L45_GPIO3_CTRL1, 0x81000001 },
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2022-04-05 21:54:19 +08:00
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};
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static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case CS35L45_DEVID ... CS35L45_OTPID:
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case CS35L45_SFT_RESET:
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case CS35L45_GLOBAL_ENABLES:
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case CS35L45_BLOCK_ENABLES:
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case CS35L45_BLOCK_ENABLES2:
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case CS35L45_ERROR_RELEASE:
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2023-03-15 23:47:18 +08:00
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case CS35L45_SYNC_GPIO1:
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case CS35L45_INTB_GPIO2_MCLK_REF:
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case CS35L45_GPIO3:
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2023-03-15 23:47:21 +08:00
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case CS35L45_PWRMGT_CTL:
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2023-03-15 23:47:22 +08:00
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case CS35L45_WAKESRC_CTL:
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case CS35L45_WKI2C_CTL:
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case CS35L45_PWRMGT_STS:
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2022-04-05 21:54:19 +08:00
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case CS35L45_REFCLK_INPUT:
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case CS35L45_GLOBAL_SAMPLE_RATE:
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case CS35L45_ASP_ENABLES1:
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case CS35L45_ASP_CONTROL1:
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case CS35L45_ASP_CONTROL2:
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case CS35L45_ASP_CONTROL3:
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case CS35L45_ASP_FRAME_CONTROL1:
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case CS35L45_ASP_FRAME_CONTROL2:
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case CS35L45_ASP_FRAME_CONTROL5:
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case CS35L45_ASP_DATA_CONTROL1:
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case CS35L45_ASP_DATA_CONTROL5:
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case CS35L45_DACPCM1_INPUT:
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case CS35L45_ASPTX1_INPUT:
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case CS35L45_ASPTX2_INPUT:
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case CS35L45_ASPTX3_INPUT:
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case CS35L45_ASPTX4_INPUT:
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case CS35L45_ASPTX5_INPUT:
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2023-03-15 23:47:21 +08:00
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case CS35L45_DSP1RX1_INPUT:
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case CS35L45_DSP1RX2_INPUT:
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case CS35L45_DSP1RX3_INPUT:
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case CS35L45_DSP1RX4_INPUT:
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case CS35L45_DSP1RX5_INPUT:
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case CS35L45_DSP1RX6_INPUT:
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case CS35L45_DSP1RX7_INPUT:
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case CS35L45_DSP1RX8_INPUT:
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2023-09-01 00:20:40 +08:00
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case CS35L45_HVLV_CONFIG:
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2022-04-05 21:54:19 +08:00
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case CS35L45_AMP_PCM_CONTROL:
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2023-09-01 00:20:40 +08:00
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case CS35L45_AMP_GAIN:
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2022-04-05 21:54:19 +08:00
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case CS35L45_AMP_PCM_HPF_TST:
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2023-03-15 23:47:20 +08:00
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case CS35L45_IRQ1_CFG:
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case CS35L45_IRQ1_STATUS:
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case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
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case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
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case CS35L45_IRQ1_MASK_1 ... CS35L45_IRQ1_MASK_18:
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2023-03-15 23:47:18 +08:00
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case CS35L45_GPIO_STATUS1:
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case CS35L45_GPIO1_CTRL1:
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case CS35L45_GPIO2_CTRL1:
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case CS35L45_GPIO3_CTRL1:
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2023-03-15 23:47:21 +08:00
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case CS35L45_DSP_MBOX_1:
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case CS35L45_DSP_MBOX_2:
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case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4:
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case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4:
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case CS35L45_DSP1_SYS_ID:
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case CS35L45_DSP1_CLOCK_FREQ:
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case CS35L45_DSP1_RX1_RATE:
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case CS35L45_DSP1_RX2_RATE:
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case CS35L45_DSP1_RX3_RATE:
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case CS35L45_DSP1_RX4_RATE:
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case CS35L45_DSP1_RX5_RATE:
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case CS35L45_DSP1_RX6_RATE:
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case CS35L45_DSP1_RX7_RATE:
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case CS35L45_DSP1_RX8_RATE:
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case CS35L45_DSP1_TX1_RATE:
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case CS35L45_DSP1_TX2_RATE:
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case CS35L45_DSP1_TX3_RATE:
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case CS35L45_DSP1_TX4_RATE:
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case CS35L45_DSP1_TX5_RATE:
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case CS35L45_DSP1_TX6_RATE:
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case CS35L45_DSP1_TX7_RATE:
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case CS35L45_DSP1_TX8_RATE:
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case CS35L45_DSP1_SCRATCH1:
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case CS35L45_DSP1_SCRATCH2:
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case CS35L45_DSP1_SCRATCH3:
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case CS35L45_DSP1_SCRATCH4:
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case CS35L45_DSP1_CCM_CORE_CONTROL:
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case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607:
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case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071:
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case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143:
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case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532:
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case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022:
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case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043:
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case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834:
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2022-04-05 21:54:19 +08:00
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return true;
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default:
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return false;
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}
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}
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static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case CS35L45_DEVID ... CS35L45_OTPID:
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case CS35L45_SFT_RESET:
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case CS35L45_GLOBAL_ENABLES:
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case CS35L45_ERROR_RELEASE:
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case CS35L45_AMP_PCM_HPF_TST: /* not cachable */
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2023-03-15 23:47:22 +08:00
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case CS35L45_PWRMGT_STS:
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2023-03-15 23:47:20 +08:00
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case CS35L45_IRQ1_STATUS:
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case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
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case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
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2023-03-15 23:47:18 +08:00
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case CS35L45_GPIO_STATUS1:
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2023-03-15 23:47:21 +08:00
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case CS35L45_DSP_MBOX_1:
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case CS35L45_DSP_MBOX_2:
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case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4:
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case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4:
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case CS35L45_DSP1_SYS_ID:
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case CS35L45_DSP1_CLOCK_FREQ:
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case CS35L45_DSP1_SCRATCH1:
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case CS35L45_DSP1_SCRATCH2:
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case CS35L45_DSP1_SCRATCH3:
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case CS35L45_DSP1_SCRATCH4:
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case CS35L45_DSP1_CCM_CORE_CONTROL:
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case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607:
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case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071:
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case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143:
|
|
|
|
|
case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532:
|
|
|
|
|
case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022:
|
|
|
|
|
case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043:
|
|
|
|
|
case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834:
|
2022-04-05 21:54:19 +08:00
|
|
|
return true;
|
|
|
|
|
default:
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const struct regmap_config cs35l45_i2c_regmap = {
|
|
|
|
|
.reg_bits = 32,
|
|
|
|
|
.val_bits = 32,
|
|
|
|
|
.reg_stride = 4,
|
|
|
|
|
.reg_format_endian = REGMAP_ENDIAN_BIG,
|
|
|
|
|
.val_format_endian = REGMAP_ENDIAN_BIG,
|
|
|
|
|
.max_register = CS35L45_LASTREG,
|
|
|
|
|
.reg_defaults = cs35l45_defaults,
|
|
|
|
|
.num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
|
|
|
|
|
.volatile_reg = cs35l45_volatile_reg,
|
|
|
|
|
.readable_reg = cs35l45_readable_reg,
|
2023-07-13 08:13:16 +08:00
|
|
|
.cache_type = REGCACHE_MAPLE,
|
2022-04-05 21:54:19 +08:00
|
|
|
};
|
2023-02-15 18:58:18 +08:00
|
|
|
EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45);
|
2022-04-05 21:54:19 +08:00
|
|
|
|
|
|
|
|
const struct regmap_config cs35l45_spi_regmap = {
|
|
|
|
|
.reg_bits = 32,
|
|
|
|
|
.val_bits = 32,
|
|
|
|
|
.pad_bits = 16,
|
|
|
|
|
.reg_stride = 4,
|
|
|
|
|
.reg_format_endian = REGMAP_ENDIAN_BIG,
|
|
|
|
|
.val_format_endian = REGMAP_ENDIAN_BIG,
|
|
|
|
|
.max_register = CS35L45_LASTREG,
|
|
|
|
|
.reg_defaults = cs35l45_defaults,
|
|
|
|
|
.num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
|
|
|
|
|
.volatile_reg = cs35l45_volatile_reg,
|
|
|
|
|
.readable_reg = cs35l45_readable_reg,
|
2023-07-13 08:13:16 +08:00
|
|
|
.cache_type = REGCACHE_MAPLE,
|
2022-04-05 21:54:19 +08:00
|
|
|
};
|
2023-02-15 18:58:18 +08:00
|
|
|
EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45);
|
2022-04-05 21:54:19 +08:00
|
|
|
|
|
|
|
|
static const struct {
|
|
|
|
|
u8 cfg_id;
|
|
|
|
|
u32 freq;
|
|
|
|
|
} cs35l45_pll_refclk_freq[] = {
|
|
|
|
|
{ 0x0C, 128000 },
|
|
|
|
|
{ 0x0F, 256000 },
|
|
|
|
|
{ 0x11, 384000 },
|
|
|
|
|
{ 0x12, 512000 },
|
|
|
|
|
{ 0x15, 768000 },
|
|
|
|
|
{ 0x17, 1024000 },
|
|
|
|
|
{ 0x19, 1411200 },
|
|
|
|
|
{ 0x1B, 1536000 },
|
|
|
|
|
{ 0x1C, 2116800 },
|
|
|
|
|
{ 0x1D, 2048000 },
|
|
|
|
|
{ 0x1E, 2304000 },
|
|
|
|
|
{ 0x1F, 2822400 },
|
|
|
|
|
{ 0x21, 3072000 },
|
|
|
|
|
{ 0x23, 4233600 },
|
|
|
|
|
{ 0x24, 4096000 },
|
|
|
|
|
{ 0x25, 4608000 },
|
|
|
|
|
{ 0x26, 5644800 },
|
|
|
|
|
{ 0x27, 6000000 },
|
|
|
|
|
{ 0x28, 6144000 },
|
|
|
|
|
{ 0x29, 6350400 },
|
|
|
|
|
{ 0x2A, 6912000 },
|
|
|
|
|
{ 0x2D, 7526400 },
|
|
|
|
|
{ 0x2E, 8467200 },
|
|
|
|
|
{ 0x2F, 8192000 },
|
|
|
|
|
{ 0x30, 9216000 },
|
|
|
|
|
{ 0x31, 11289600 },
|
|
|
|
|
{ 0x33, 12288000 },
|
|
|
|
|
{ 0x37, 16934400 },
|
|
|
|
|
{ 0x38, 18432000 },
|
|
|
|
|
{ 0x39, 22579200 },
|
|
|
|
|
{ 0x3B, 24576000 },
|
|
|
|
|
};
|
|
|
|
|
|
2024-09-19 23:16:52 +08:00
|
|
|
int cs35l45_get_clk_freq_id(unsigned int freq)
|
2022-04-05 21:54:19 +08:00
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
if (freq == 0)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(cs35l45_pll_refclk_freq); ++i) {
|
|
|
|
|
if (cs35l45_pll_refclk_freq[i].freq == freq)
|
|
|
|
|
return cs35l45_pll_refclk_freq[i].cfg_id;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
2023-02-15 18:58:18 +08:00
|
|
|
EXPORT_SYMBOL_NS_GPL(cs35l45_get_clk_freq_id, SND_SOC_CS35L45);
|
