2018-11-06 04:27:27 +08:00
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// SPDX-License-Identifier: GPL-2.0+
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2012-07-19 06:07:18 +08:00
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/*
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2018-11-06 04:27:27 +08:00
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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2012-07-19 06:07:18 +08:00
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*/
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2014-04-03 10:31:31 +08:00
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#include "socfpga_cyclone5.dtsi"
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2012-07-19 06:07:18 +08:00
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/ {
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2013-10-07 23:38:41 +08:00
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model = "Altera SOCFPGA Cyclone V SoC Development Kit";
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2016-11-01 22:57:06 +08:00
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compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
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2012-07-19 06:07:18 +08:00
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chosen {
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2015-07-15 06:19:02 +08:00
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bootargs = "earlyprintk";
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stdout-path = "serial0:115200n8";
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2012-07-19 06:07:18 +08:00
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};
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2017-02-28 00:38:39 +08:00
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memory@0 {
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2012-07-19 06:07:18 +08:00
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name = "memory";
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device_type = "memory";
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2013-02-12 07:30:30 +08:00
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reg = <0x0 0x40000000>; /* 1GB */
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};
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2013-06-05 23:02:53 +08:00
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aliases {
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/* this allow the ethaddr uboot environmnet variable contents
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* to be added to the gmac1 device tree blob.
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*/
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ethernet0 = &gmac1;
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};
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2014-10-17 03:43:53 +08:00
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2016-12-13 12:02:44 +08:00
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leds {
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compatible = "gpio-leds";
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hps0 {
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label = "hps_led0";
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gpios = <&portb 15 1>;
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};
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hps1 {
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label = "hps_led1";
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gpios = <&portb 14 1>;
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};
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hps2 {
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label = "hps_led2";
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gpios = <&portb 13 1>;
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};
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hps3 {
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label = "hps_led3";
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gpios = <&portb 12 1>;
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};
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};
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2014-10-17 03:43:53 +08:00
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regulator_3_3v: 3-3-v-regulator {
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compatible = "regulator-fixed";
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regulator-name = "3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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2012-07-19 06:07:18 +08:00
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};
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2014-03-27 11:45:11 +08:00
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2016-12-17 06:55:44 +08:00
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&can0 {
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status = "okay";
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};
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2014-03-27 11:45:11 +08:00
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&gmac1 {
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status = "okay";
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phy-mode = "rgmii";
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rxd0-skew-ps = <0>;
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rxd1-skew-ps = <0>;
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rxd2-skew-ps = <0>;
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rxd3-skew-ps = <0>;
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txen-skew-ps = <0>;
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txc-skew-ps = <2600>;
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rxdv-skew-ps = <0>;
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rxc-skew-ps = <2000>;
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};
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2014-04-03 03:02:42 +08:00
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2016-12-13 12:02:44 +08:00
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&gpio0 {
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status = "okay";
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};
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2014-10-17 03:54:51 +08:00
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&gpio1 {
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status = "okay";
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};
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2016-12-13 12:02:44 +08:00
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&gpio2 {
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status = "okay";
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};
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2014-04-03 03:02:42 +08:00
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&i2c0 {
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status = "okay";
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2016-12-14 06:52:11 +08:00
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clock-frequency = <100000>;
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/*
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* adjust the falling times to decrease the i2c frequency to 50Khz
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* because the LCD module does not work at the standard 100Khz
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*/
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i2c-sda-falling-time-ns = <5000>;
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i2c-scl-falling-time-ns = <5000>;
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2014-04-03 03:02:42 +08:00
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eeprom@51 {
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compatible = "atmel,24c32";
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reg = <0x51>;
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pagesize = <32>;
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};
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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2013-10-28 22:48:32 +08:00
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2014-08-14 23:21:48 +08:00
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&mmc0 {
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2014-10-17 03:54:51 +08:00
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cd-gpios = <&portb 18 0>;
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2014-10-17 03:43:53 +08:00
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vmmc-supply = <®ulator_3_3v>;
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vqmmc-supply = <®ulator_3_3v>;
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2015-12-21 14:42:01 +08:00
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status = "okay";
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2014-08-14 23:21:48 +08:00
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};
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2016-10-19 11:51:42 +08:00
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&qspi {
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status = "okay";
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flash0: n25q00@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q00";
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reg = <0>; /* chip select */
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spi-max-frequency = <100000000>;
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m25p,fast-read;
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cdns,page-size = <256>;
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cdns,block-size = <16>;
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cdns,read-delay = <4>;
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cdns,tshsl-ns = <50>;
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cdns,tsd2d-ns = <50>;
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cdns,tchsh-ns = <4>;
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cdns,tslch-ns = <4>;
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partition@qspi-boot {
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/* 8MB for raw data. */
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label = "Flash 0 Raw Data";
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reg = <0x0 0x800000>;
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};
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partition@qspi-rootfs {
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/* 120MB for jffs2 data. */
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label = "Flash 0 jffs2 Filesystem";
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reg = <0x800000 0x7800000>;
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};
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};
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};
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2016-12-16 13:30:03 +08:00
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&spi0 {
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status = "okay";
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spidev@0 {
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compatible = "rohm,dh2228fv";
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reg = <0>;
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spi-max-frequency = <1000000>;
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};
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};
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2013-10-28 22:48:32 +08:00
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&usb1 {
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status = "okay";
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};
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