2010-10-19 11:05:51 +08:00
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/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_dma.h"
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#include "nouveau_ramht.h"
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static void
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2010-10-19 12:18:06 +08:00
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nv50_evo_channel_del(struct nouveau_channel **pevo)
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2010-10-19 11:05:51 +08:00
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{
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2010-10-19 12:18:06 +08:00
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struct drm_nouveau_private *dev_priv;
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struct nouveau_channel *evo = *pevo;
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2010-10-19 11:05:51 +08:00
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2010-10-19 12:18:06 +08:00
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if (!evo)
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2010-10-19 11:05:51 +08:00
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return;
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2010-10-19 12:18:06 +08:00
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*pevo = NULL;
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2010-10-19 11:05:51 +08:00
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2010-10-19 12:18:06 +08:00
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dev_priv = evo->dev->dev_private;
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dev_priv->evo_alloc &= ~(1 << evo->id);
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2010-10-19 11:05:51 +08:00
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2010-10-19 12:18:06 +08:00
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nouveau_gpuobj_channel_takedown(evo);
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nouveau_bo_unmap(evo->pushbuf_bo);
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nouveau_bo_ref(NULL, &evo->pushbuf_bo);
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2010-10-19 11:05:51 +08:00
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2010-10-19 12:18:06 +08:00
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if (evo->user)
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iounmap(evo->user);
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kfree(evo);
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2010-10-19 11:05:51 +08:00
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}
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int
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nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
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u32 tile_flags, u32 magic_flags, u32 offset, u32 limit)
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{
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struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
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struct drm_device *dev = evo->dev;
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struct nouveau_gpuobj *obj = NULL;
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int ret;
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2010-10-19 12:18:06 +08:00
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ret = nouveau_gpuobj_new(dev, dev_priv->evo, 6*4, 32, 0, &obj);
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2010-10-19 11:05:51 +08:00
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if (ret)
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return ret;
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obj->engine = NVOBJ_ENGINE_DISPLAY;
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nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
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nv_wo32(obj, 4, limit);
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nv_wo32(obj, 8, offset);
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nv_wo32(obj, 12, 0x00000000);
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nv_wo32(obj, 16, 0x00000000);
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if (dev_priv->card_type < NV_C0)
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nv_wo32(obj, 20, 0x00010000);
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else
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nv_wo32(obj, 20, 0x00020000);
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dev_priv->engine.instmem.flush(dev);
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ret = nouveau_ramht_insert(evo, name, obj);
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nouveau_gpuobj_ref(NULL, &obj);
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if (ret) {
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return ret;
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}
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return 0;
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}
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static int
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2010-10-19 12:18:06 +08:00
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nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pevo)
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2010-10-19 11:05:51 +08:00
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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2010-10-19 12:18:06 +08:00
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struct nouveau_channel *evo;
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2010-10-19 11:05:51 +08:00
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int ret;
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2010-10-19 12:18:06 +08:00
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evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
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if (!evo)
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2010-10-19 11:05:51 +08:00
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return -ENOMEM;
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2010-10-19 12:18:06 +08:00
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*pevo = evo;
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2010-10-19 11:05:51 +08:00
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2010-10-19 12:18:06 +08:00
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for (evo->id = 0; evo->id < 5; evo->id++) {
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if (dev_priv->evo_alloc & (1 << evo->id))
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continue;
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2010-10-19 11:05:51 +08:00
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2010-10-19 12:18:06 +08:00
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dev_priv->evo_alloc |= (1 << evo->id);
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break;
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2010-10-19 11:05:51 +08:00
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}
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2010-10-19 12:18:06 +08:00
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if (evo->id == 5) {
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kfree(evo);
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return -ENODEV;
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2010-10-19 11:05:51 +08:00
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}
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2010-10-19 12:18:06 +08:00
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evo->dev = dev;
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evo->user_get = 4;
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evo->user_put = 0;
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2010-10-19 11:05:51 +08:00
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ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
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2010-10-19 12:18:06 +08:00
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false, true, &evo->pushbuf_bo);
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2010-10-19 11:05:51 +08:00
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if (ret == 0)
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2010-10-19 12:18:06 +08:00
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ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM);
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2010-10-19 11:05:51 +08:00
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if (ret) {
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NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
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2010-10-19 12:18:06 +08:00
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nv50_evo_channel_del(pevo);
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2010-10-19 11:05:51 +08:00
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return ret;
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}
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2010-10-19 12:18:06 +08:00
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ret = nouveau_bo_map(evo->pushbuf_bo);
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2010-10-19 11:05:51 +08:00
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if (ret) {
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NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
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2010-10-19 12:18:06 +08:00
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nv50_evo_channel_del(pevo);
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2010-10-19 11:05:51 +08:00
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return ret;
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}
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2010-10-19 12:18:06 +08:00
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evo->user = ioremap(pci_resource_start(dev->pdev, 0) +
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NV50_PDISPLAY_USER(evo->id), PAGE_SIZE);
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if (!evo->user) {
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2010-10-19 11:05:51 +08:00
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NV_ERROR(dev, "Error mapping EVO control regs.\n");
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2010-10-19 12:18:06 +08:00
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nv50_evo_channel_del(pevo);
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2010-10-19 11:05:51 +08:00
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return -ENOMEM;
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}
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2010-10-19 12:18:06 +08:00
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/* bind primary evo channel's ramht to the channel */
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if (dev_priv->evo && evo != dev_priv->evo)
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nouveau_ramht_ref(dev_priv->evo->ramht, &evo->ramht, NULL);
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2010-10-19 11:05:51 +08:00
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return 0;
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}
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static int
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nv50_evo_channel_init(struct nouveau_channel *evo)
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{
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struct drm_device *dev = evo->dev;
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2010-10-19 12:18:06 +08:00
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int id = evo->id, ret, i;
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2010-10-19 16:01:41 +08:00
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u64 pushbuf = evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT;
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2010-10-19 11:05:51 +08:00
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u32 tmp;
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2010-10-19 16:01:41 +08:00
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tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
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if ((tmp & 0x009f0000) == 0x00020000)
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nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00800000);
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2010-10-19 11:05:51 +08:00
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2010-10-19 16:01:41 +08:00
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tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
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if ((tmp & 0x003f0000) == 0x00030000)
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nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00600000);
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2010-10-19 11:05:51 +08:00
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/* initialise fifo */
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2010-10-19 16:01:41 +08:00
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nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id), pushbuf >> 8 |
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NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
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NV50_PDISPLAY_EVO_DMA_CB_VALID);
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2010-10-19 12:18:06 +08:00
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nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
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nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
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2010-10-19 16:01:41 +08:00
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nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), NV50_PDISPLAY_EVO_CTRL_DMA,
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NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
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nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0x00000000);
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nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
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NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
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2010-10-19 12:18:06 +08:00
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if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
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2010-10-19 16:01:41 +08:00
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NV_ERROR(dev, "EvoCh %d init timeout: 0x%08x\n", id,
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2010-10-19 12:18:06 +08:00
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nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
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2010-10-19 11:05:51 +08:00
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return -EBUSY;
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}
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/* enable error reporting on the channel */
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2010-10-19 12:18:06 +08:00
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nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
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2010-10-19 11:05:51 +08:00
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evo->dma.max = (4096/4) - 2;
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evo->dma.put = 0;
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evo->dma.cur = evo->dma.put;
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evo->dma.free = evo->dma.max - evo->dma.cur;
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ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
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if (ret)
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return ret;
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for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
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OUT_RING(evo, 0);
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return 0;
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}
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static void
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nv50_evo_channel_fini(struct nouveau_channel *evo)
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{
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struct drm_device *dev = evo->dev;
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2010-10-19 16:01:41 +08:00
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int id = evo->id;
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nv_mask(dev, 0x610028, 0x00010001 << id, 0x00000000);
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nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000);
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nv_wr32(dev, NV50_PDISPLAY_INTR_0, (1 << id));
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nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00000003, 0x00000000);
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if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x001e0000, 0x00000000)) {
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NV_ERROR(dev, "EvoCh %d takedown timeout: 0x%08x\n", id,
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nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
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2010-10-19 12:18:06 +08:00
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}
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}
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static int
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nv50_evo_create(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramht = NULL;
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struct nouveau_channel *evo;
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int ret;
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/* create primary evo channel, the one we use for modesetting
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* purporses
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*/
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ret = nv50_evo_channel_new(dev, &dev_priv->evo);
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if (ret)
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return ret;
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evo = dev_priv->evo;
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/* setup object management on it, any other evo channel will
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* use this also as there's no per-channel support on the
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* hardware
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*/
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ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
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if (ret) {
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NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
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nv50_evo_channel_del(&dev_priv->evo);
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return ret;
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}
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ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
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if (ret) {
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NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
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nv50_evo_channel_del(&dev_priv->evo);
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return ret;
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}
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ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
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if (ret) {
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NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
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nv50_evo_channel_del(&dev_priv->evo);
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return ret;
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}
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ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
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nouveau_gpuobj_ref(NULL, &ramht);
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if (ret) {
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nv50_evo_channel_del(&dev_priv->evo);
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return ret;
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}
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/* create some default objects for the scanout memtypes we support */
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if (dev_priv->chipset != 0x50) {
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ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
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0, 0xffffffff);
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if (ret) {
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nv50_evo_channel_del(&dev_priv->evo);
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return ret;
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}
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ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19,
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0, 0xffffffff);
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if (ret) {
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nv50_evo_channel_del(&dev_priv->evo);
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return ret;
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}
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}
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ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
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0, dev_priv->vram_size);
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if (ret) {
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nv50_evo_channel_del(&dev_priv->evo);
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return ret;
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2010-10-19 11:05:51 +08:00
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}
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2010-10-19 12:18:06 +08:00
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return 0;
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2010-10-19 11:05:51 +08:00
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}
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int
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nv50_evo_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int ret;
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if (!dev_priv->evo) {
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2010-10-19 12:18:06 +08:00
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ret = nv50_evo_create(dev);
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2010-10-19 11:05:51 +08:00
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if (ret)
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return ret;
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}
|
|
|
|
|
|
|
|
return nv50_evo_channel_init(dev_priv->evo);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
nv50_evo_fini(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (dev_priv->evo) {
|
|
|
|
nv50_evo_channel_fini(dev_priv->evo);
|
|
|
|
nv50_evo_channel_del(&dev_priv->evo);
|
|
|
|
}
|
|
|
|
}
|