2017-11-03 18:28:30 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2017-04-19 19:59:27 +08:00
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/*
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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* core.h - DesignWare USB3 DRD Core Header
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*/
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#ifndef __DRIVERS_USB_DWC3_CORE_H
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#define __DRIVERS_USB_DWC3_CORE_H
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#include <linux/device.h>
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#include <linux/spinlock.h>
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2011-10-12 19:08:26 +08:00
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#include <linux/ioport.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#include <linux/list.h>
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2017-03-30 14:46:40 +08:00
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#include <linux/bitops.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#include <linux/dma-mapping.h>
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#include <linux/mm.h>
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#include <linux/debugfs.h>
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2016-10-31 19:38:36 +08:00
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#include <linux/wait.h>
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2017-04-04 17:49:18 +08:00
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#include <linux/workqueue.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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2013-07-06 20:52:49 +08:00
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#include <linux/usb/otg.h>
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2015-05-13 20:26:51 +08:00
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#include <linux/ulpi/interface.h>
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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2014-03-03 19:38:11 +08:00
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#include <linux/phy/phy.h>
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2014-05-01 06:45:10 +08:00
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#define DWC3_MSG_MAX 500
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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/* Global constants */
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2016-10-14 17:11:33 +08:00
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#define DWC3_PULL_UP_TIMEOUT 500 /* ms */
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2017-01-05 20:46:52 +08:00
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#define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
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2017-04-07 19:09:13 +08:00
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#define DWC3_EP0_SETUP_SIZE 512
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#define DWC3_ENDPOINTS_NUM 32
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2012-04-24 19:18:39 +08:00
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#define DWC3_XHCI_RESOURCES_NUM 2
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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2013-12-20 03:04:28 +08:00
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#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
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2016-12-23 20:40:40 +08:00
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#define DWC3_EVENT_BUFFERS_SIZE 4096
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#define DWC3_EVENT_TYPE_MASK 0xfe
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#define DWC3_EVENT_TYPE_DEV 0
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#define DWC3_EVENT_TYPE_CARKIT 3
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#define DWC3_EVENT_TYPE_I2C 4
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#define DWC3_DEVICE_EVENT_DISCONNECT 0
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#define DWC3_DEVICE_EVENT_RESET 1
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#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
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#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
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#define DWC3_DEVICE_EVENT_WAKEUP 4
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2012-02-16 10:56:58 +08:00
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#define DWC3_DEVICE_EVENT_HIBER_REQ 5
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#define DWC3_DEVICE_EVENT_EOPF 6
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#define DWC3_DEVICE_EVENT_SOF 7
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#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
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#define DWC3_DEVICE_EVENT_CMD_CMPL 10
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#define DWC3_DEVICE_EVENT_OVERFLOW 11
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2018-02-27 19:30:19 +08:00
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/* Controller's role while using the OTG block */
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#define DWC3_OTG_ROLE_IDLE 0
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#define DWC3_OTG_ROLE_HOST 1
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#define DWC3_OTG_ROLE_DEVICE 2
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#define DWC3_GEVNTCOUNT_MASK 0xfffc
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2017-03-30 14:46:40 +08:00
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#define DWC3_GEVNTCOUNT_EHB BIT(31)
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#define DWC3_GSNPSID_MASK 0xffff0000
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#define DWC3_GSNPSREV_MASK 0xffff
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2012-04-24 19:18:39 +08:00
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/* DWC3 registers memory space boundries */
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#define DWC3_XHCI_REGS_START 0x0
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#define DWC3_XHCI_REGS_END 0x7fff
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#define DWC3_GLOBALS_REGS_START 0xc100
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#define DWC3_GLOBALS_REGS_END 0xc6ff
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#define DWC3_DEVICE_REGS_START 0xc700
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#define DWC3_DEVICE_REGS_END 0xcbff
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#define DWC3_OTG_REGS_START 0xcc00
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#define DWC3_OTG_REGS_END 0xccff
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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/* Global Registers */
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#define DWC3_GSBUSCFG0 0xc100
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#define DWC3_GSBUSCFG1 0xc104
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#define DWC3_GTXTHRCFG 0xc108
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#define DWC3_GRXTHRCFG 0xc10c
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#define DWC3_GCTL 0xc110
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#define DWC3_GEVTEN 0xc114
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#define DWC3_GSTS 0xc118
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2016-05-13 18:13:46 +08:00
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#define DWC3_GUCTL1 0xc11c
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#define DWC3_GSNPSID 0xc120
|
|
|
|
#define DWC3_GGPIO 0xc124
|
|
|
|
#define DWC3_GUID 0xc128
|
|
|
|
#define DWC3_GUCTL 0xc12c
|
|
|
|
#define DWC3_GBUSERRADDR0 0xc130
|
|
|
|
#define DWC3_GBUSERRADDR1 0xc134
|
|
|
|
#define DWC3_GPRTBIMAP0 0xc138
|
|
|
|
#define DWC3_GPRTBIMAP1 0xc13c
|
|
|
|
#define DWC3_GHWPARAMS0 0xc140
|
|
|
|
#define DWC3_GHWPARAMS1 0xc144
|
|
|
|
#define DWC3_GHWPARAMS2 0xc148
|
|
|
|
#define DWC3_GHWPARAMS3 0xc14c
|
|
|
|
#define DWC3_GHWPARAMS4 0xc150
|
|
|
|
#define DWC3_GHWPARAMS5 0xc154
|
|
|
|
#define DWC3_GHWPARAMS6 0xc158
|
|
|
|
#define DWC3_GHWPARAMS7 0xc15c
|
|
|
|
#define DWC3_GDBGFIFOSPACE 0xc160
|
|
|
|
#define DWC3_GDBGLTSSM 0xc164
|
|
|
|
#define DWC3_GPRTBIMAP_HS0 0xc180
|
|
|
|
#define DWC3_GPRTBIMAP_HS1 0xc184
|
|
|
|
#define DWC3_GPRTBIMAP_FS0 0xc188
|
|
|
|
#define DWC3_GPRTBIMAP_FS1 0xc18c
|
2016-08-23 06:39:13 +08:00
|
|
|
#define DWC3_GUCTL2 0xc19c
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2015-09-05 10:15:10 +08:00
|
|
|
#define DWC3_VER_NUMBER 0xc1a0
|
|
|
|
#define DWC3_VER_TYPE 0xc1a4
|
|
|
|
|
2017-04-06 18:14:28 +08:00
|
|
|
#define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
|
|
|
|
#define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2017-04-06 18:14:28 +08:00
|
|
|
#define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2017-04-06 18:14:28 +08:00
|
|
|
#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2017-04-06 18:14:28 +08:00
|
|
|
#define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
|
|
|
|
#define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2017-04-06 18:14:28 +08:00
|
|
|
#define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
|
|
|
|
#define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
|
|
|
|
#define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
|
|
|
|
#define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
#define DWC3_GHWPARAMS8 0xc600
|
2015-09-04 12:45:58 +08:00
|
|
|
#define DWC3_GFLADJ 0xc630
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
/* Device Registers */
|
|
|
|
#define DWC3_DCFG 0xc700
|
|
|
|
#define DWC3_DCTL 0xc704
|
|
|
|
#define DWC3_DEVTEN 0xc708
|
|
|
|
#define DWC3_DSTS 0xc70c
|
|
|
|
#define DWC3_DGCMDPAR 0xc710
|
|
|
|
#define DWC3_DGCMD 0xc714
|
|
|
|
#define DWC3_DALEPENA 0xc720
|
2016-04-12 21:53:39 +08:00
|
|
|
|
2017-04-06 18:14:28 +08:00
|
|
|
#define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
|
2016-04-12 21:53:39 +08:00
|
|
|
#define DWC3_DEPCMDPAR2 0x00
|
|
|
|
#define DWC3_DEPCMDPAR1 0x04
|
|
|
|
#define DWC3_DEPCMDPAR0 0x08
|
|
|
|
#define DWC3_DEPCMD 0x0c
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2017-04-06 18:14:28 +08:00
|
|
|
#define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
|
2016-11-15 04:32:43 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* OTG Registers */
|
|
|
|
#define DWC3_OCFG 0xcc00
|
|
|
|
#define DWC3_OCTL 0xcc04
|
2013-03-14 18:35:24 +08:00
|
|
|
#define DWC3_OEVT 0xcc08
|
|
|
|
#define DWC3_OEVTEN 0xcc0C
|
|
|
|
#define DWC3_OSTS 0xcc10
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
/* Bit fields */
|
|
|
|
|
2016-04-14 20:03:39 +08:00
|
|
|
/* Global Debug Queue/FIFO Space Available Register */
|
|
|
|
#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
|
|
|
|
#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
|
|
|
|
#define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
|
|
|
|
|
2018-02-03 05:21:35 +08:00
|
|
|
#define DWC3_TXFIFOQ 0
|
|
|
|
#define DWC3_RXFIFOQ 1
|
|
|
|
#define DWC3_TXREQQ 2
|
|
|
|
#define DWC3_RXREQQ 3
|
|
|
|
#define DWC3_RXINFOQ 4
|
|
|
|
#define DWC3_PSTATQ 5
|
|
|
|
#define DWC3_DESCFETCHQ 6
|
|
|
|
#define DWC3_EVENTQ 7
|
|
|
|
#define DWC3_AUXEVENTQ 8
|
2016-04-14 20:03:39 +08:00
|
|
|
|
2016-04-28 15:56:28 +08:00
|
|
|
/* Global RX Threshold Configuration Register */
|
|
|
|
#define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
|
|
|
|
#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
|
2016-04-28 15:56:28 +08:00
|
|
|
|
2018-03-17 06:34:07 +08:00
|
|
|
/* Global RX Threshold Configuration Register for DWC_usb31 only */
|
|
|
|
#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
|
|
|
|
#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
|
|
|
|
#define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
|
|
|
|
#define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
|
|
|
|
#define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
|
|
|
|
#define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
|
|
|
|
#define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
|
|
|
|
#define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
|
|
|
|
|
2018-03-17 06:34:20 +08:00
|
|
|
/* Global TX Threshold Configuration Register for DWC_usb31 only */
|
|
|
|
#define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
|
|
|
|
#define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
|
|
|
|
#define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
|
|
|
|
#define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
|
|
|
|
#define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
|
|
|
|
#define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
|
|
|
|
#define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
|
|
|
|
#define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* Global Configuration Register */
|
2012-02-16 10:56:56 +08:00
|
|
|
#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GCTL_U2RSTECN BIT(16)
|
2012-02-16 10:56:56 +08:00
|
|
|
#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#define DWC3_GCTL_CLK_BUS (0)
|
|
|
|
#define DWC3_GCTL_CLK_PIPE (1)
|
|
|
|
#define DWC3_GCTL_CLK_PIPEHALF (2)
|
|
|
|
#define DWC3_GCTL_CLK_MASK (3)
|
|
|
|
|
2011-10-17 13:50:39 +08:00
|
|
|
#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
|
2012-02-16 10:56:56 +08:00
|
|
|
#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#define DWC3_GCTL_PRTCAP_HOST 1
|
|
|
|
#define DWC3_GCTL_PRTCAP_DEVICE 2
|
|
|
|
#define DWC3_GCTL_PRTCAP_OTG 3
|
|
|
|
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GCTL_CORESOFTRESET BIT(11)
|
|
|
|
#define DWC3_GCTL_SOFITPSYNC BIT(10)
|
2012-02-16 10:56:58 +08:00
|
|
|
#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
|
|
|
|
#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GCTL_DISSCRAMBLE BIT(3)
|
|
|
|
#define DWC3_GCTL_U2EXIT_LFPS BIT(2)
|
|
|
|
#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
|
|
|
|
#define DWC3_GCTL_DSBLCLKGTNG BIT(0)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2016-10-13 09:00:55 +08:00
|
|
|
/* Global User Control 1 Register */
|
2017-04-19 20:11:38 +08:00
|
|
|
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
|
2016-10-13 09:00:55 +08:00
|
|
|
|
2018-02-27 19:29:11 +08:00
|
|
|
/* Global Status Register */
|
|
|
|
#define DWC3_GSTS_OTG_IP BIT(10)
|
|
|
|
#define DWC3_GSTS_BC_IP BIT(9)
|
|
|
|
#define DWC3_GSTS_ADP_IP BIT(8)
|
|
|
|
#define DWC3_GSTS_HOST_IP BIT(7)
|
|
|
|
#define DWC3_GSTS_DEVICE_IP BIT(6)
|
|
|
|
#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
|
|
|
|
#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* Global USB2 PHY Configuration Register */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
|
|
|
|
#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
|
|
|
|
#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
|
|
|
|
#define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
|
|
|
|
#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
|
2016-08-16 22:44:38 +08:00
|
|
|
#define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
|
|
|
|
#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
|
|
|
|
#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
|
|
|
|
#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
|
|
|
|
#define USBTRDTIM_UTMI_8_BIT 9
|
|
|
|
#define USBTRDTIM_UTMI_16_BIT 5
|
|
|
|
#define UTMI_PHYIF_16_BIT 1
|
|
|
|
#define UTMI_PHYIF_8_BIT 0
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2015-05-13 20:26:43 +08:00
|
|
|
/* Global USB2 PHY Vendor Control Register */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
|
|
|
|
#define DWC3_GUSB2PHYACC_BUSY BIT(23)
|
|
|
|
#define DWC3_GUSB2PHYACC_WRITE BIT(22)
|
2015-05-13 20:26:43 +08:00
|
|
|
#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
|
|
|
|
#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
|
|
|
|
#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* Global USB3 PIPE Control Register */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
|
|
|
|
#define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
|
|
|
|
#define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
|
|
|
|
#define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
|
|
|
|
#define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
|
2014-10-28 19:54:30 +08:00
|
|
|
#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
|
|
|
|
#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
|
|
|
|
#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
|
|
|
|
#define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
|
|
|
|
#define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
|
|
|
|
#define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
|
2014-10-31 11:11:12 +08:00
|
|
|
#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
|
|
|
|
#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-01-19 00:04:09 +08:00
|
|
|
/* Global TX Fifo Size Register */
|
2018-03-17 06:33:54 +08:00
|
|
|
#define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
|
|
|
|
#define DWC31_GTXFIFOSIZ_TXFDEF(n) ((n) & 0x7fff) /* DWC_usb31 only */
|
2012-02-16 10:56:58 +08:00
|
|
|
#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
|
|
|
|
#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
|
2012-01-19 00:04:09 +08:00
|
|
|
|
2013-06-13 02:09:26 +08:00
|
|
|
/* Global Event Size Registers */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GEVNTSIZ_INTMASK BIT(31)
|
2013-06-13 02:09:26 +08:00
|
|
|
#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
|
|
|
|
|
2016-05-13 19:09:59 +08:00
|
|
|
/* Global HWPARAMS0 Register */
|
2016-09-07 10:22:03 +08:00
|
|
|
#define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
|
|
|
|
#define DWC3_GHWPARAMS0_MODE_GADGET 0
|
|
|
|
#define DWC3_GHWPARAMS0_MODE_HOST 1
|
|
|
|
#define DWC3_GHWPARAMS0_MODE_DRD 2
|
2016-05-13 19:09:59 +08:00
|
|
|
#define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
|
|
|
|
#define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
|
|
|
|
#define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
|
|
|
|
#define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
|
|
|
|
#define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
|
|
|
|
|
2011-09-30 15:58:50 +08:00
|
|
|
/* Global HWPARAMS1 Register */
|
2012-02-16 10:56:56 +08:00
|
|
|
#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
|
2011-09-30 15:58:50 +08:00
|
|
|
#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
|
|
|
|
#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
|
2012-02-16 10:56:58 +08:00
|
|
|
#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
|
|
|
|
#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
|
|
|
|
#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
|
|
|
|
|
2014-05-24 02:39:24 +08:00
|
|
|
/* Global HWPARAMS3 Register */
|
|
|
|
#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
|
|
|
|
#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
|
2016-02-06 09:08:31 +08:00
|
|
|
#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
|
|
|
|
#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
|
2014-05-24 02:39:24 +08:00
|
|
|
#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
|
|
|
|
#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
|
|
|
|
#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
|
|
|
|
#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
|
|
|
|
#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
|
|
|
|
#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
|
|
|
|
#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
|
|
|
|
#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
|
|
|
|
|
2012-02-16 10:56:58 +08:00
|
|
|
/* Global HWPARAMS4 Register */
|
|
|
|
#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
|
|
|
|
#define DWC3_MAX_HIBER_SCRATCHBUFS 15
|
2011-09-30 15:58:50 +08:00
|
|
|
|
2014-10-28 19:54:23 +08:00
|
|
|
/* Global HWPARAMS6 Register */
|
2018-02-27 19:29:11 +08:00
|
|
|
#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
|
|
|
|
#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
|
|
|
|
#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
|
|
|
|
#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
|
|
|
|
#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
|
2014-10-28 19:54:23 +08:00
|
|
|
|
2016-05-13 19:09:59 +08:00
|
|
|
/* Global HWPARAMS7 Register */
|
|
|
|
#define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
|
|
|
|
#define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
|
|
|
|
|
2015-09-04 12:45:58 +08:00
|
|
|
/* Global Frame Length Adjustment Register */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
|
2015-09-04 12:45:58 +08:00
|
|
|
#define DWC3_GFLADJ_30MHZ_MASK 0x3f
|
|
|
|
|
2016-08-23 06:39:13 +08:00
|
|
|
/* Global User Control Register 2 */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
|
2016-08-23 06:39:13 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* Device Configuration Register */
|
|
|
|
#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
|
|
|
|
#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
|
|
|
|
|
|
|
|
#define DWC3_DCFG_SPEED_MASK (7 << 0)
|
2016-02-06 09:08:31 +08:00
|
|
|
#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#define DWC3_DCFG_SUPERSPEED (4 << 0)
|
|
|
|
#define DWC3_DCFG_HIGHSPEED (0 << 0)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DCFG_FULLSPEED BIT(0)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#define DWC3_DCFG_LOWSPEED (2 << 0)
|
|
|
|
|
2016-04-26 15:49:07 +08:00
|
|
|
#define DWC3_DCFG_NUMP_SHIFT 17
|
2016-05-03 15:49:00 +08:00
|
|
|
#define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
|
2016-04-26 15:49:07 +08:00
|
|
|
#define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DCFG_LPM_CAP BIT(22)
|
2012-02-16 10:56:58 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* Device Control Register */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DCTL_RUN_STOP BIT(31)
|
|
|
|
#define DWC3_DCTL_CSFTRST BIT(30)
|
|
|
|
#define DWC3_DCTL_LSFTRST BIT(29)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
|
2012-06-06 21:48:29 +08:00
|
|
|
#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DCTL_APPL1RES BIT(23)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-02-16 10:56:58 +08:00
|
|
|
/* These apply for core versions 1.87a and earlier */
|
|
|
|
#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
|
|
|
|
#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
|
|
|
|
#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
|
|
|
|
#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
|
|
|
|
#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
|
|
|
|
#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
|
|
|
|
#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
|
|
|
|
|
|
|
|
/* These apply for core versions 1.94a and later */
|
2014-10-28 19:54:26 +08:00
|
|
|
#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
|
|
|
|
#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
|
2012-01-19 00:32:29 +08:00
|
|
|
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DCTL_KEEP_CONNECT BIT(19)
|
|
|
|
#define DWC3_DCTL_L1_HIBER_EN BIT(18)
|
|
|
|
#define DWC3_DCTL_CRS BIT(17)
|
|
|
|
#define DWC3_DCTL_CSS BIT(16)
|
2014-10-28 19:54:26 +08:00
|
|
|
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DCTL_INITU2ENA BIT(12)
|
|
|
|
#define DWC3_DCTL_ACCEPTU2ENA BIT(11)
|
|
|
|
#define DWC3_DCTL_INITU1ENA BIT(10)
|
|
|
|
#define DWC3_DCTL_ACCEPTU1ENA BIT(9)
|
2014-10-28 19:54:26 +08:00
|
|
|
#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
|
|
|
|
#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
|
|
|
|
|
|
|
|
#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
|
|
|
|
#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
|
|
|
|
#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
|
|
|
|
#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
|
|
|
|
#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
|
|
|
|
#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
|
|
|
|
#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
|
|
|
|
|
|
|
|
/* Device Event Enable Register */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
|
|
|
|
#define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
|
|
|
|
#define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
|
|
|
|
#define DWC3_DEVTEN_ERRTICERREN BIT(9)
|
|
|
|
#define DWC3_DEVTEN_SOFEN BIT(7)
|
|
|
|
#define DWC3_DEVTEN_EOPFEN BIT(6)
|
|
|
|
#define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
|
|
|
|
#define DWC3_DEVTEN_WKUPEVTEN BIT(4)
|
|
|
|
#define DWC3_DEVTEN_ULSTCNGEN BIT(3)
|
|
|
|
#define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
|
|
|
|
#define DWC3_DEVTEN_USBRSTEN BIT(1)
|
|
|
|
#define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
/* Device Status Register */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DSTS_DCNRD BIT(29)
|
2012-02-16 10:56:58 +08:00
|
|
|
|
|
|
|
/* This applies for core versions 1.87a and earlier */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DSTS_PWRUPREQ BIT(24)
|
2012-02-16 10:56:58 +08:00
|
|
|
|
|
|
|
/* These apply for core versions 1.94a and later */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DSTS_RSS BIT(25)
|
|
|
|
#define DWC3_DSTS_SSS BIT(24)
|
2012-02-16 10:56:58 +08:00
|
|
|
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DSTS_COREIDLE BIT(23)
|
|
|
|
#define DWC3_DSTS_DEVCTRLHLT BIT(22)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
|
|
|
|
#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
|
|
|
|
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DSTS_RXFIFOEMPTY BIT(17)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-05-21 17:21:30 +08:00
|
|
|
#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
|
|
|
|
|
|
|
|
#define DWC3_DSTS_CONNECTSPD (7 << 0)
|
|
|
|
|
2016-02-06 09:08:31 +08:00
|
|
|
#define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#define DWC3_DSTS_SUPERSPEED (4 << 0)
|
|
|
|
#define DWC3_DSTS_HIGHSPEED (0 << 0)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DSTS_FULLSPEED BIT(0)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#define DWC3_DSTS_LOWSPEED (2 << 0)
|
|
|
|
|
|
|
|
/* Device Generic Command Register */
|
|
|
|
#define DWC3_DGCMD_SET_LMP 0x01
|
|
|
|
#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
|
|
|
|
#define DWC3_DGCMD_XMIT_FUNCTION 0x03
|
2012-02-16 10:56:58 +08:00
|
|
|
|
|
|
|
/* These apply for core versions 1.94a and later */
|
|
|
|
#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
|
|
|
|
#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
|
|
|
|
#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
|
|
|
|
#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
|
|
|
|
#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
|
|
|
|
|
2015-05-21 18:16:46 +08:00
|
|
|
#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DGCMD_CMDACT BIT(10)
|
|
|
|
#define DWC3_DGCMD_CMDIOC BIT(8)
|
2012-02-16 10:56:58 +08:00
|
|
|
|
|
|
|
/* Device Generic Command Parameter Register */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
|
2012-02-16 10:56:58 +08:00
|
|
|
#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
|
|
|
|
#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DGCMDPAR_TX_FIFO BIT(5)
|
2012-02-16 10:56:58 +08:00
|
|
|
#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
|
2012-04-24 21:19:11 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* Device Endpoint Command Register */
|
|
|
|
#define DWC3_DEPCMD_PARAM_SHIFT 16
|
2012-02-16 10:56:56 +08:00
|
|
|
#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
|
2013-12-20 04:02:53 +08:00
|
|
|
#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
|
2015-05-21 18:16:46 +08:00
|
|
|
#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
|
|
|
|
#define DWC3_DEPCMD_CLEARPENDIN BIT(11)
|
|
|
|
#define DWC3_DEPCMD_CMDACT BIT(10)
|
|
|
|
#define DWC3_DEPCMD_CMDIOC BIT(8)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
|
|
|
|
#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
|
|
|
|
#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
|
|
|
|
#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
|
|
|
|
#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
|
|
|
|
#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
|
2012-02-16 10:56:58 +08:00
|
|
|
/* This applies for core versions 1.90a and earlier */
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
|
2012-02-16 10:56:58 +08:00
|
|
|
/* This applies for core versions 1.94a and later */
|
|
|
|
#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
|
|
|
|
#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
|
|
|
|
|
2016-09-22 17:25:28 +08:00
|
|
|
#define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_DALEPENA_EP(n) BIT(n)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
#define DWC3_DEPCMD_TYPE_CONTROL 0
|
|
|
|
#define DWC3_DEPCMD_TYPE_ISOC 1
|
|
|
|
#define DWC3_DEPCMD_TYPE_BULK 2
|
|
|
|
#define DWC3_DEPCMD_TYPE_INTR 3
|
|
|
|
|
2016-11-15 04:32:43 +08:00
|
|
|
#define DWC3_DEV_IMOD_COUNT_SHIFT 16
|
|
|
|
#define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
|
|
|
|
#define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
|
|
|
|
#define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
|
|
|
|
|
2018-02-27 19:29:11 +08:00
|
|
|
/* OTG Configuration Register */
|
|
|
|
#define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
|
|
|
|
#define DWC3_OCFG_HIBDISMASK BIT(4)
|
|
|
|
#define DWC3_OCFG_SFTRSTMASK BIT(3)
|
|
|
|
#define DWC3_OCFG_OTGVERSION BIT(2)
|
|
|
|
#define DWC3_OCFG_HNPCAP BIT(1)
|
|
|
|
#define DWC3_OCFG_SRPCAP BIT(0)
|
|
|
|
|
|
|
|
/* OTG CTL Register */
|
|
|
|
#define DWC3_OCTL_OTG3GOERR BIT(7)
|
|
|
|
#define DWC3_OCTL_PERIMODE BIT(6)
|
|
|
|
#define DWC3_OCTL_PRTPWRCTL BIT(5)
|
|
|
|
#define DWC3_OCTL_HNPREQ BIT(4)
|
|
|
|
#define DWC3_OCTL_SESREQ BIT(3)
|
|
|
|
#define DWC3_OCTL_TERMSELIDPULSE BIT(2)
|
|
|
|
#define DWC3_OCTL_DEVSETHNPEN BIT(1)
|
|
|
|
#define DWC3_OCTL_HSTSETHNPEN BIT(0)
|
|
|
|
|
|
|
|
/* OTG Event Register */
|
|
|
|
#define DWC3_OEVT_DEVICEMODE BIT(31)
|
|
|
|
#define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
|
|
|
|
#define DWC3_OEVT_DEVRUNSTPSET BIT(26)
|
|
|
|
#define DWC3_OEVT_HIBENTRY BIT(25)
|
|
|
|
#define DWC3_OEVT_CONIDSTSCHNG BIT(24)
|
|
|
|
#define DWC3_OEVT_HRRCONFNOTIF BIT(23)
|
|
|
|
#define DWC3_OEVT_HRRINITNOTIF BIT(22)
|
|
|
|
#define DWC3_OEVT_ADEVIDLE BIT(21)
|
|
|
|
#define DWC3_OEVT_ADEVBHOSTEND BIT(20)
|
|
|
|
#define DWC3_OEVT_ADEVHOST BIT(19)
|
|
|
|
#define DWC3_OEVT_ADEVHNPCHNG BIT(18)
|
|
|
|
#define DWC3_OEVT_ADEVSRPDET BIT(17)
|
|
|
|
#define DWC3_OEVT_ADEVSESSENDDET BIT(16)
|
|
|
|
#define DWC3_OEVT_BDEVBHOSTEND BIT(11)
|
|
|
|
#define DWC3_OEVT_BDEVHNPCHNG BIT(10)
|
|
|
|
#define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
|
|
|
|
#define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
|
|
|
|
#define DWC3_OEVT_BSESSVLD BIT(3)
|
|
|
|
#define DWC3_OEVT_HSTNEGSTS BIT(2)
|
|
|
|
#define DWC3_OEVT_SESREQSTS BIT(1)
|
|
|
|
#define DWC3_OEVT_ERROR BIT(0)
|
|
|
|
|
|
|
|
/* OTG Event Enable Register */
|
|
|
|
#define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
|
|
|
|
#define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
|
|
|
|
#define DWC3_OEVTEN_HIBENTRYEN BIT(25)
|
|
|
|
#define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
|
|
|
|
#define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
|
|
|
|
#define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
|
|
|
|
#define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
|
|
|
|
#define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
|
|
|
|
#define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
|
|
|
|
#define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
|
|
|
|
#define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
|
|
|
|
#define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
|
|
|
|
#define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
|
|
|
|
#define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
|
|
|
|
#define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
|
|
|
|
#define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
|
|
|
|
|
|
|
|
/* OTG Status Register */
|
|
|
|
#define DWC3_OSTS_DEVRUNSTP BIT(13)
|
|
|
|
#define DWC3_OSTS_XHCIRUNSTP BIT(12)
|
|
|
|
#define DWC3_OSTS_PERIPHERALSTATE BIT(4)
|
|
|
|
#define DWC3_OSTS_XHCIPRTPOWER BIT(3)
|
|
|
|
#define DWC3_OSTS_BSESVLD BIT(2)
|
|
|
|
#define DWC3_OSTS_VBUSVLD BIT(1)
|
|
|
|
#define DWC3_OSTS_CONIDSTS BIT(0)
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* Structures */
|
|
|
|
|
2012-02-06 17:04:53 +08:00
|
|
|
struct dwc3_trb;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* struct dwc3_event_buffer - Software event buffer representation
|
|
|
|
* @buf: _THE_ buffer
|
2016-11-15 18:54:15 +08:00
|
|
|
* @cache: The buffer cache used in the threaded interrupt
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @length: size of this buffer
|
2011-07-05 01:20:04 +08:00
|
|
|
* @lpos: event offset
|
2011-07-05 01:23:14 +08:00
|
|
|
* @count: cache of last read event count register
|
2011-07-05 01:20:04 +08:00
|
|
|
* @flags: flags related to this event buffer
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @dma: dma_addr_t
|
|
|
|
* @dwc: pointer to DWC controller
|
|
|
|
*/
|
|
|
|
struct dwc3_event_buffer {
|
|
|
|
void *buf;
|
2016-11-15 18:54:15 +08:00
|
|
|
void *cache;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
unsigned length;
|
|
|
|
unsigned int lpos;
|
2011-07-05 01:23:14 +08:00
|
|
|
unsigned int count;
|
2011-07-05 01:20:04 +08:00
|
|
|
unsigned int flags;
|
|
|
|
|
|
|
|
#define DWC3_EVENT_PENDING BIT(0)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
dma_addr_t dma;
|
|
|
|
|
|
|
|
struct dwc3 *dwc;
|
|
|
|
};
|
|
|
|
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_EP_FLAG_STALLED BIT(0)
|
|
|
|
#define DWC3_EP_FLAG_WEDGED BIT(1)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
#define DWC3_EP_DIRECTION_TX true
|
|
|
|
#define DWC3_EP_DIRECTION_RX false
|
|
|
|
|
2016-03-10 20:40:31 +08:00
|
|
|
#define DWC3_TRB_NUM 256
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* struct dwc3_ep - device side endpoint representation
|
|
|
|
* @endpoint: usb endpoint
|
2016-03-14 17:01:31 +08:00
|
|
|
* @pending_list: list of pending requests for this endpoint
|
|
|
|
* @started_list: list of started requests on this endpoint
|
2016-10-31 19:38:36 +08:00
|
|
|
* @wait_end_transfer: wait_queue_head_t for waiting on End Transfer complete
|
2016-04-13 21:44:39 +08:00
|
|
|
* @lock: spinlock for endpoint request queue traversal
|
2016-04-12 21:53:39 +08:00
|
|
|
* @regs: pointer to first endpoint register
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @trb_pool: array of transaction buffers
|
|
|
|
* @trb_pool_dma: dma address of @trb_pool
|
2016-04-04 20:33:41 +08:00
|
|
|
* @trb_enqueue: enqueue 'pointer' into TRB array
|
|
|
|
* @trb_dequeue: dequeue 'pointer' into TRB array
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @dwc: pointer to DWC controller
|
2012-04-27 18:56:23 +08:00
|
|
|
* @saved_state: ep state saved during hibernation
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @flags: endpoint flags (wedged, stalled, ...)
|
|
|
|
* @number: endpoint number (1 - 15)
|
|
|
|
* @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
|
2012-06-06 17:04:13 +08:00
|
|
|
* @resource_index: Resource transfer index
|
2017-09-05 19:36:13 +08:00
|
|
|
* @frame_number: set to the frame number we want this transfer to start (ISOC)
|
2013-06-12 23:43:11 +08:00
|
|
|
* @interval: the interval on which the ISOC transfer is started
|
2016-05-30 18:34:58 +08:00
|
|
|
* @allocated_requests: number of requests allocated
|
|
|
|
* @queued_requests: number of requests queued for transfer
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @name: a human readable name e.g. ep1out-bulk
|
|
|
|
* @direction: true for TX, false for RX
|
2011-09-30 15:58:47 +08:00
|
|
|
* @stream_capable: true when streams are enabled
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*/
|
|
|
|
struct dwc3_ep {
|
|
|
|
struct usb_ep endpoint;
|
2016-03-14 17:01:31 +08:00
|
|
|
struct list_head pending_list;
|
|
|
|
struct list_head started_list;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2016-10-31 19:38:36 +08:00
|
|
|
wait_queue_head_t wait_end_transfer;
|
|
|
|
|
2016-04-13 21:44:39 +08:00
|
|
|
spinlock_t lock;
|
2016-04-12 21:53:39 +08:00
|
|
|
void __iomem *regs;
|
|
|
|
|
2012-02-06 17:04:53 +08:00
|
|
|
struct dwc3_trb *trb_pool;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dma_addr_t trb_pool_dma;
|
|
|
|
struct dwc3 *dwc;
|
|
|
|
|
2012-04-27 18:56:23 +08:00
|
|
|
u32 saved_state;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
unsigned flags;
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_EP_ENABLED BIT(0)
|
|
|
|
#define DWC3_EP_STALL BIT(1)
|
|
|
|
#define DWC3_EP_WEDGE BIT(2)
|
|
|
|
#define DWC3_EP_BUSY BIT(4)
|
|
|
|
#define DWC3_EP_PENDING_REQUEST BIT(5)
|
|
|
|
#define DWC3_EP_MISSED_ISOC BIT(6)
|
|
|
|
#define DWC3_EP_END_TRANSFER_PENDING BIT(7)
|
|
|
|
#define DWC3_EP_TRANSFER_STARTED BIT(8)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-08-28 03:26:00 +08:00
|
|
|
/* This last one is specific to EP0 */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_EP0_DIR_IN BIT(31)
|
2011-08-28 03:26:00 +08:00
|
|
|
|
2016-04-05 17:42:15 +08:00
|
|
|
/*
|
|
|
|
* IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
|
|
|
|
* use a u8 type here. If anybody decides to increase number of TRBs to
|
|
|
|
* anything larger than 256 - I can't see why people would want to do
|
|
|
|
* this though - then this type needs to be changed.
|
|
|
|
*
|
|
|
|
* By using u8 types we ensure that our % operator when incrementing
|
|
|
|
* enqueue and dequeue get optimized away by the compiler.
|
|
|
|
*/
|
|
|
|
u8 trb_enqueue;
|
|
|
|
u8 trb_dequeue;
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
u8 number;
|
|
|
|
u8 type;
|
2012-06-06 17:04:13 +08:00
|
|
|
u8 resource_index;
|
2016-05-30 18:34:58 +08:00
|
|
|
u32 allocated_requests;
|
|
|
|
u32 queued_requests;
|
2017-09-05 19:36:13 +08:00
|
|
|
u32 frame_number;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
u32 interval;
|
|
|
|
|
|
|
|
char name[20];
|
|
|
|
|
|
|
|
unsigned direction:1;
|
2011-09-30 15:58:47 +08:00
|
|
|
unsigned stream_capable:1;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
enum dwc3_phy {
|
|
|
|
DWC3_PHY_UNKNOWN = 0,
|
|
|
|
DWC3_PHY_USB3,
|
|
|
|
DWC3_PHY_USB2,
|
|
|
|
};
|
|
|
|
|
2011-08-30 20:50:40 +08:00
|
|
|
enum dwc3_ep0_next {
|
|
|
|
DWC3_EP0_UNKNOWN = 0,
|
|
|
|
DWC3_EP0_COMPLETE,
|
|
|
|
DWC3_EP0_NRDY_DATA,
|
|
|
|
DWC3_EP0_NRDY_STATUS,
|
|
|
|
};
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
enum dwc3_ep0_state {
|
|
|
|
EP0_UNCONNECTED = 0,
|
2011-08-28 03:28:36 +08:00
|
|
|
EP0_SETUP_PHASE,
|
|
|
|
EP0_DATA_PHASE,
|
|
|
|
EP0_STATUS_PHASE,
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
enum dwc3_link_state {
|
|
|
|
/* In SuperSpeed */
|
|
|
|
DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
|
|
|
|
DWC3_LINK_STATE_U1 = 0x01,
|
|
|
|
DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
|
|
|
|
DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
|
|
|
|
DWC3_LINK_STATE_SS_DIS = 0x04,
|
|
|
|
DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
|
|
|
|
DWC3_LINK_STATE_SS_INACT = 0x06,
|
|
|
|
DWC3_LINK_STATE_POLL = 0x07,
|
|
|
|
DWC3_LINK_STATE_RECOV = 0x08,
|
|
|
|
DWC3_LINK_STATE_HRESET = 0x09,
|
|
|
|
DWC3_LINK_STATE_CMPLY = 0x0a,
|
|
|
|
DWC3_LINK_STATE_LPBK = 0x0b,
|
2012-02-16 10:56:58 +08:00
|
|
|
DWC3_LINK_STATE_RESET = 0x0e,
|
|
|
|
DWC3_LINK_STATE_RESUME = 0x0f,
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
DWC3_LINK_STATE_MASK = 0x0f,
|
|
|
|
};
|
|
|
|
|
2012-02-06 17:04:53 +08:00
|
|
|
/* TRB Length, PCM and Status */
|
|
|
|
#define DWC3_TRB_SIZE_MASK (0x00ffffff)
|
|
|
|
#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
|
|
|
|
#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
|
2012-05-21 15:16:26 +08:00
|
|
|
#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
|
2012-02-06 17:04:53 +08:00
|
|
|
|
|
|
|
#define DWC3_TRBSTS_OK 0
|
|
|
|
#define DWC3_TRBSTS_MISSED_ISOC 1
|
|
|
|
#define DWC3_TRBSTS_SETUP_PENDING 2
|
2012-02-16 10:56:58 +08:00
|
|
|
#define DWC3_TRB_STS_XFER_IN_PROG 4
|
2012-02-06 17:04:53 +08:00
|
|
|
|
|
|
|
/* TRB Control */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_TRB_CTRL_HWO BIT(0)
|
|
|
|
#define DWC3_TRB_CTRL_LST BIT(1)
|
|
|
|
#define DWC3_TRB_CTRL_CHN BIT(2)
|
|
|
|
#define DWC3_TRB_CTRL_CSP BIT(3)
|
2012-02-06 17:04:53 +08:00
|
|
|
#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DWC3_TRB_CTRL_ISP_IMI BIT(10)
|
|
|
|
#define DWC3_TRB_CTRL_IOC BIT(11)
|
2012-02-06 17:04:53 +08:00
|
|
|
#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
|
|
|
|
|
2016-04-14 21:05:54 +08:00
|
|
|
#define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
|
2012-02-06 17:04:53 +08:00
|
|
|
#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
|
|
|
|
#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
|
|
|
|
#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
|
|
|
|
#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
|
|
|
|
#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
|
|
|
|
#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
|
|
|
|
#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
|
|
|
|
#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
/**
|
2012-02-06 17:04:53 +08:00
|
|
|
* struct dwc3_trb - transfer request block (hw format)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @bpl: DW0-3
|
|
|
|
* @bph: DW4-7
|
|
|
|
* @size: DW8-B
|
2017-04-19 19:59:27 +08:00
|
|
|
* @ctrl: DWC-F
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*/
|
2012-02-06 17:04:53 +08:00
|
|
|
struct dwc3_trb {
|
|
|
|
u32 bpl;
|
|
|
|
u32 bph;
|
|
|
|
u32 size;
|
|
|
|
u32 ctrl;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
} __packed;
|
|
|
|
|
2011-09-30 15:58:48 +08:00
|
|
|
/**
|
2017-04-19 19:59:27 +08:00
|
|
|
* struct dwc3_hwparams - copy of HWPARAMS registers
|
|
|
|
* @hwparams0: GHWPARAMS0
|
|
|
|
* @hwparams1: GHWPARAMS1
|
|
|
|
* @hwparams2: GHWPARAMS2
|
|
|
|
* @hwparams3: GHWPARAMS3
|
|
|
|
* @hwparams4: GHWPARAMS4
|
|
|
|
* @hwparams5: GHWPARAMS5
|
|
|
|
* @hwparams6: GHWPARAMS6
|
|
|
|
* @hwparams7: GHWPARAMS7
|
|
|
|
* @hwparams8: GHWPARAMS8
|
2011-09-30 15:58:48 +08:00
|
|
|
*/
|
|
|
|
struct dwc3_hwparams {
|
|
|
|
u32 hwparams0;
|
|
|
|
u32 hwparams1;
|
|
|
|
u32 hwparams2;
|
|
|
|
u32 hwparams3;
|
|
|
|
u32 hwparams4;
|
|
|
|
u32 hwparams5;
|
|
|
|
u32 hwparams6;
|
|
|
|
u32 hwparams7;
|
|
|
|
u32 hwparams8;
|
|
|
|
};
|
|
|
|
|
2011-10-12 15:44:56 +08:00
|
|
|
/* HWPARAMS0 */
|
|
|
|
#define DWC3_MODE(n) ((n) & 0x7)
|
|
|
|
|
2012-01-19 00:04:09 +08:00
|
|
|
#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
|
|
|
|
|
2011-10-12 15:44:56 +08:00
|
|
|
/* HWPARAMS1 */
|
2012-01-19 00:04:09 +08:00
|
|
|
#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
|
|
|
|
|
2011-05-05 20:53:10 +08:00
|
|
|
/* HWPARAMS3 */
|
|
|
|
#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
|
|
|
|
#define DWC3_NUM_EPS_MASK (0x3f << 12)
|
|
|
|
#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
|
|
|
|
(DWC3_NUM_EPS_MASK)) >> 12)
|
|
|
|
#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
|
|
|
|
(DWC3_NUM_IN_EPS_MASK)) >> 18)
|
|
|
|
|
2012-01-19 00:04:09 +08:00
|
|
|
/* HWPARAMS7 */
|
|
|
|
#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
|
2011-10-12 15:31:04 +08:00
|
|
|
|
2016-04-05 16:33:30 +08:00
|
|
|
/**
|
|
|
|
* struct dwc3_request - representation of a transfer request
|
|
|
|
* @request: struct usb_request to be transferred
|
|
|
|
* @list: a list_head used for request queueing
|
|
|
|
* @dep: struct dwc3_ep owning this request
|
2016-08-12 18:10:10 +08:00
|
|
|
* @sg: pointer to first incomplete sg
|
|
|
|
* @num_pending_sgs: counter to pending sgs
|
2016-10-25 18:47:21 +08:00
|
|
|
* @remaining: amount of data remaining
|
2016-04-05 16:33:30 +08:00
|
|
|
* @epnum: endpoint number to which this request refers
|
|
|
|
* @trb: pointer to struct dwc3_trb
|
|
|
|
* @trb_dma: DMA address of @trb
|
2017-01-05 20:58:46 +08:00
|
|
|
* @unaligned: true for OUT endpoints with length not divisible by maxp
|
2016-04-05 16:33:30 +08:00
|
|
|
* @direction: IN or OUT direction flag
|
|
|
|
* @mapped: true when request has been dma-mapped
|
2017-04-19 19:59:27 +08:00
|
|
|
* @started: request is started
|
|
|
|
* @zero: wants a ZLP
|
2016-04-05 16:33:30 +08:00
|
|
|
*/
|
2011-11-25 19:03:46 +08:00
|
|
|
struct dwc3_request {
|
|
|
|
struct usb_request request;
|
|
|
|
struct list_head list;
|
|
|
|
struct dwc3_ep *dep;
|
2016-08-12 18:10:10 +08:00
|
|
|
struct scatterlist *sg;
|
2011-11-25 19:03:46 +08:00
|
|
|
|
2016-08-12 18:10:10 +08:00
|
|
|
unsigned num_pending_sgs;
|
2016-10-25 18:47:21 +08:00
|
|
|
unsigned remaining;
|
2011-11-25 19:03:46 +08:00
|
|
|
u8 epnum;
|
2012-02-06 17:04:53 +08:00
|
|
|
struct dwc3_trb *trb;
|
2011-11-25 19:03:46 +08:00
|
|
|
dma_addr_t trb_dma;
|
|
|
|
|
2017-01-05 20:58:46 +08:00
|
|
|
unsigned unaligned:1;
|
2011-11-25 19:03:46 +08:00
|
|
|
unsigned direction:1;
|
|
|
|
unsigned mapped:1;
|
2016-03-14 17:01:31 +08:00
|
|
|
unsigned started:1;
|
2017-04-07 21:34:38 +08:00
|
|
|
unsigned zero:1;
|
2011-11-25 19:03:46 +08:00
|
|
|
};
|
|
|
|
|
2012-02-16 10:56:58 +08:00
|
|
|
/*
|
|
|
|
* struct dwc3_scratchpad_array - hibernation scratchpad array
|
|
|
|
* (format defined by hw)
|
|
|
|
*/
|
|
|
|
struct dwc3_scratchpad_array {
|
|
|
|
__le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
|
|
|
|
};
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/**
|
|
|
|
* struct dwc3 - representation of our controller
|
2017-04-19 19:59:27 +08:00
|
|
|
* @drd_work: workqueue used for role swapping
|
2011-08-27 06:40:52 +08:00
|
|
|
* @ep0_trb: trb which is used for the ctrl_req
|
2017-04-19 19:59:27 +08:00
|
|
|
* @bounce: address of bounce buffer
|
|
|
|
* @scratchbuf: address of scratch buffer
|
2011-08-27 06:40:52 +08:00
|
|
|
* @setup_buf: used while precessing STD USB requests
|
2017-04-19 19:59:27 +08:00
|
|
|
* @ep0_trb_addr: dma address of @ep0_trb
|
|
|
|
* @bounce_addr: dma address of @bounce
|
2011-08-27 06:40:52 +08:00
|
|
|
* @ep0_usb_req: dummy req used while handling STD USB requests
|
2013-12-20 03:04:28 +08:00
|
|
|
* @scratch_addr: dma address of scratchbuf
|
2016-10-14 17:11:33 +08:00
|
|
|
* @ep0_in_setup: one control transfer is completed and enter setup phase
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @lock: for synchronizing
|
|
|
|
* @dev: pointer to our struct device
|
2017-04-19 19:59:27 +08:00
|
|
|
* @sysdev: pointer to the DMA-capable device
|
2011-10-12 19:08:26 +08:00
|
|
|
* @xhci: pointer to our xHCI child
|
2017-04-19 19:59:27 +08:00
|
|
|
* @xhci_resources: struct resources for our @xhci child
|
|
|
|
* @ev_buf: struct dwc3_event_buffer pointer
|
|
|
|
* @eps: endpoint array
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @gadget: device side representation of the peripheral controller
|
|
|
|
* @gadget_driver: pointer to the gadget driver
|
|
|
|
* @regs: base address for our registers
|
|
|
|
* @regs_size: address space size
|
2016-05-16 15:42:23 +08:00
|
|
|
* @fladj: frame length adjustment
|
2016-05-16 19:17:06 +08:00
|
|
|
* @irq_gadget: peripheral controller's IRQ number
|
2018-02-27 19:30:19 +08:00
|
|
|
* @otg_irq: IRQ number for OTG IRQs
|
|
|
|
* @current_otg_role: current role of operation while using the OTG block
|
|
|
|
* @desired_otg_role: desired role of operation while using the OTG block
|
|
|
|
* @otg_restart_host: flag that OTG controller needs to restart host
|
2013-12-20 03:04:28 +08:00
|
|
|
* @nr_scratch: number of scratch buffers
|
2011-10-14 18:00:30 +08:00
|
|
|
* @u1u2: only used on revisions <1.83a for workaround
|
2011-10-08 03:55:04 +08:00
|
|
|
* @maximum_speed: maximum speed requested (mainly for testing purposes)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @revision: revision register contents
|
2013-07-06 20:52:49 +08:00
|
|
|
* @dr_mode: requested mode of operation
|
2017-04-04 16:25:27 +08:00
|
|
|
* @current_dr_role: current role of operation when in dual-role mode
|
2017-04-04 17:49:18 +08:00
|
|
|
* @desired_dr_role: desired role of operation when in dual-role mode
|
2017-04-05 18:39:31 +08:00
|
|
|
* @edev: extcon handle
|
|
|
|
* @edev_nb: extcon notifier
|
2016-08-16 22:44:38 +08:00
|
|
|
* @hsphy_mode: UTMI phy mode, one of following:
|
|
|
|
* - USBPHY_INTERFACE_MODE_UTMI
|
|
|
|
* - USBPHY_INTERFACE_MODE_UTMIW
|
2012-07-19 19:09:48 +08:00
|
|
|
* @usb2_phy: pointer to USB2 PHY
|
|
|
|
* @usb3_phy: pointer to USB3 PHY
|
2014-03-03 19:38:11 +08:00
|
|
|
* @usb2_generic_phy: pointer to USB2 PHY
|
|
|
|
* @usb3_generic_phy: pointer to USB3 PHY
|
2018-02-12 21:30:08 +08:00
|
|
|
* @phys_ready: flag to indicate that PHYs are ready
|
2015-05-13 20:26:51 +08:00
|
|
|
* @ulpi: pointer to ulpi interface
|
2018-02-12 21:30:08 +08:00
|
|
|
* @ulpi_ready: flag to indicate that ULPI is initialized
|
2012-04-24 21:19:49 +08:00
|
|
|
* @u2sel: parameter from Set SEL request.
|
|
|
|
* @u2pel: parameter from Set SEL request.
|
|
|
|
* @u1sel: parameter from Set SEL request.
|
|
|
|
* @u1pel: parameter from Set SEL request.
|
2017-02-01 04:58:10 +08:00
|
|
|
* @num_eps: number of endpoints
|
2011-08-30 20:50:40 +08:00
|
|
|
* @ep0_next_event: hold the next expected event
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @ep0state: state of endpoint zero
|
|
|
|
* @link_state: link state
|
|
|
|
* @speed: device speed (super, high, full, low)
|
2011-09-30 15:58:48 +08:00
|
|
|
* @hwparams: copy of hwparams registers
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @root: debugfs root folder pointer
|
2013-12-20 02:12:37 +08:00
|
|
|
* @regset: debugfs pointer to regdump file
|
|
|
|
* @test_mode: true when we're entering a USB test mode
|
|
|
|
* @test_mode_nr: test feature selector
|
2014-10-28 19:54:26 +08:00
|
|
|
* @lpm_nyet_threshold: LPM NYET response threshold
|
2014-10-31 11:11:18 +08:00
|
|
|
* @hird_threshold: HIRD threshold
|
2018-03-17 06:35:44 +08:00
|
|
|
* @rx_thr_num_pkt_prd: periodic ESS receive packet count
|
|
|
|
* @rx_max_burst_prd: max periodic ESS receive burst size
|
|
|
|
* @tx_thr_num_pkt_prd: periodic ESS transmit packet count
|
|
|
|
* @tx_max_burst_prd: max periodic ESS transmit burst size
|
2015-05-13 20:26:49 +08:00
|
|
|
* @hsphy_interface: "utmi" or "ulpi"
|
2016-05-16 18:14:48 +08:00
|
|
|
* @connected: true when we're connected to a host, false otherwise
|
2013-12-20 02:12:37 +08:00
|
|
|
* @delayed_status: true when gadget driver asks for delayed status
|
|
|
|
* @ep0_bounced: true when we used bounce buffer
|
|
|
|
* @ep0_expect_in: true when we expect a DATA IN transfer
|
2013-12-20 02:14:29 +08:00
|
|
|
* @has_hibernation: true when dwc3 was configured with Hibernation
|
2016-11-17 19:43:47 +08:00
|
|
|
* @sysdev_is_parent: true when dwc3 device has a parent driver
|
2014-10-28 19:54:26 +08:00
|
|
|
* @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
|
|
|
|
* there's now way for software to detect this in runtime.
|
2014-10-31 11:11:18 +08:00
|
|
|
* @is_utmi_l1_suspend: the core asserts output signal
|
|
|
|
* 0 - utmi_sleep_n
|
|
|
|
* 1 - utmi_l1_suspend_n
|
2014-10-28 19:54:23 +08:00
|
|
|
* @is_fpga: true when we are using the FPGA board
|
2016-05-16 18:14:48 +08:00
|
|
|
* @pending_events: true when we have pending IRQs to be handled
|
2013-12-20 02:12:37 +08:00
|
|
|
* @pullups_connected: true when Run/Stop bit is set
|
|
|
|
* @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
|
|
|
|
* @three_stage_setup: set if we perform a three phase setup
|
2015-03-09 22:06:12 +08:00
|
|
|
* @usb3_lpm_capable: set if hadrware supports Link Power Management
|
2014-10-28 19:54:25 +08:00
|
|
|
* @disable_scramble_quirk: set if we enable the disable scramble quirk
|
2014-10-28 19:54:27 +08:00
|
|
|
* @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
|
2014-10-28 19:54:28 +08:00
|
|
|
* @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
|
2014-10-28 19:54:29 +08:00
|
|
|
* @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
|
2014-10-28 19:54:30 +08:00
|
|
|
* @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
|
2014-10-28 19:54:31 +08:00
|
|
|
* @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
|
2014-10-28 19:54:32 +08:00
|
|
|
* @lfps_filter_quirk: set if we enable LFPS filter quirk
|
2014-10-28 19:54:33 +08:00
|
|
|
* @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
|
2014-10-31 11:11:13 +08:00
|
|
|
* @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
|
2014-10-31 11:11:14 +08:00
|
|
|
* @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
|
2015-10-03 11:30:57 +08:00
|
|
|
* @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
|
|
|
|
* disabling the suspend signal to the PHY.
|
2017-04-19 19:59:27 +08:00
|
|
|
* @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
|
2016-08-16 22:44:37 +08:00
|
|
|
* @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
|
|
|
|
* in GUSB2PHYCFG, specify that USB2 PHY doesn't
|
|
|
|
* provide a free-running PHY clock.
|
2016-08-16 22:44:39 +08:00
|
|
|
* @dis_del_phy_power_chg_quirk: set if we disable delay phy power
|
|
|
|
* change quirk.
|
2017-04-19 20:11:38 +08:00
|
|
|
* @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
|
|
|
|
* check during HS transmit.
|
2014-10-31 11:11:12 +08:00
|
|
|
* @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
|
|
|
|
* @tx_de_emphasis: Tx de-emphasis value
|
|
|
|
* 0 - -6dB de-emphasis
|
|
|
|
* 1 - -3.5dB de-emphasis
|
|
|
|
* 2 - No de-emphasis
|
|
|
|
* 3 - Reserved
|
2017-10-31 21:11:55 +08:00
|
|
|
* @dis_metastability_quirk: set to disable metastability quirk.
|
2016-11-15 04:32:43 +08:00
|
|
|
* @imod_interval: set the interrupt moderation interval in 250ns
|
|
|
|
* increments or 0 to disable.
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*/
|
|
|
|
struct dwc3 {
|
2017-04-04 17:49:18 +08:00
|
|
|
struct work_struct drd_work;
|
2012-02-06 17:04:53 +08:00
|
|
|
struct dwc3_trb *ep0_trb;
|
2017-01-05 20:46:52 +08:00
|
|
|
void *bounce;
|
2013-12-20 03:04:28 +08:00
|
|
|
void *scratchbuf;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
u8 *setup_buf;
|
|
|
|
dma_addr_t ep0_trb_addr;
|
2017-01-05 20:46:52 +08:00
|
|
|
dma_addr_t bounce_addr;
|
2013-12-20 03:04:28 +08:00
|
|
|
dma_addr_t scratch_addr;
|
2011-11-25 19:03:46 +08:00
|
|
|
struct dwc3_request ep0_usb_req;
|
2016-10-14 17:11:33 +08:00
|
|
|
struct completion ep0_in_setup;
|
2011-05-05 20:53:10 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* device lock */
|
|
|
|
spinlock_t lock;
|
2011-05-05 20:53:10 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
struct device *dev;
|
2016-11-17 19:43:47 +08:00
|
|
|
struct device *sysdev;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-10-12 19:08:26 +08:00
|
|
|
struct platform_device *xhci;
|
2012-04-24 19:18:39 +08:00
|
|
|
struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
|
2011-10-12 19:08:26 +08:00
|
|
|
|
2016-03-30 14:37:03 +08:00
|
|
|
struct dwc3_event_buffer *ev_buf;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
|
|
|
|
|
|
|
|
struct usb_gadget gadget;
|
|
|
|
struct usb_gadget_driver *gadget_driver;
|
|
|
|
|
2012-07-19 19:09:48 +08:00
|
|
|
struct usb_phy *usb2_phy;
|
|
|
|
struct usb_phy *usb3_phy;
|
|
|
|
|
2014-03-03 19:38:11 +08:00
|
|
|
struct phy *usb2_generic_phy;
|
|
|
|
struct phy *usb3_generic_phy;
|
|
|
|
|
2018-02-12 21:30:08 +08:00
|
|
|
bool phys_ready;
|
|
|
|
|
2015-05-13 20:26:51 +08:00
|
|
|
struct ulpi *ulpi;
|
2018-02-12 21:30:08 +08:00
|
|
|
bool ulpi_ready;
|
2015-05-13 20:26:51 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
void __iomem *regs;
|
|
|
|
size_t regs_size;
|
|
|
|
|
2013-07-06 20:52:49 +08:00
|
|
|
enum usb_dr_mode dr_mode;
|
2017-04-04 16:25:27 +08:00
|
|
|
u32 current_dr_role;
|
2017-04-04 17:49:18 +08:00
|
|
|
u32 desired_dr_role;
|
2017-04-05 18:39:31 +08:00
|
|
|
struct extcon_dev *edev;
|
|
|
|
struct notifier_block edev_nb;
|
2016-08-16 22:44:38 +08:00
|
|
|
enum usb_phy_interface hsphy_mode;
|
2013-07-06 20:52:49 +08:00
|
|
|
|
2016-05-16 15:42:23 +08:00
|
|
|
u32 fladj;
|
2016-05-16 19:17:06 +08:00
|
|
|
u32 irq_gadget;
|
2018-02-27 19:30:19 +08:00
|
|
|
u32 otg_irq;
|
|
|
|
u32 current_otg_role;
|
|
|
|
u32 desired_otg_role;
|
|
|
|
bool otg_restart_host;
|
2013-12-20 03:04:28 +08:00
|
|
|
u32 nr_scratch;
|
2011-10-14 18:00:30 +08:00
|
|
|
u32 u1u2;
|
2011-10-08 03:55:04 +08:00
|
|
|
u32 maximum_speed;
|
2015-09-05 10:15:10 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* All 3.1 IP version constants are greater than the 3.0 IP
|
|
|
|
* version constants. This works for most version checks in
|
|
|
|
* dwc3. However, in the future, this may not apply as
|
|
|
|
* features may be developed on newer versions of the 3.0 IP
|
|
|
|
* that are not in the 3.1 IP.
|
|
|
|
*/
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
u32 revision;
|
|
|
|
|
|
|
|
#define DWC3_REVISION_173A 0x5533173a
|
|
|
|
#define DWC3_REVISION_175A 0x5533175a
|
|
|
|
#define DWC3_REVISION_180A 0x5533180a
|
|
|
|
#define DWC3_REVISION_183A 0x5533183a
|
|
|
|
#define DWC3_REVISION_185A 0x5533185a
|
2012-02-16 10:56:58 +08:00
|
|
|
#define DWC3_REVISION_187A 0x5533187a
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#define DWC3_REVISION_188A 0x5533188a
|
|
|
|
#define DWC3_REVISION_190A 0x5533190a
|
2012-02-16 10:56:58 +08:00
|
|
|
#define DWC3_REVISION_194A 0x5533194a
|
2012-03-23 18:10:48 +08:00
|
|
|
#define DWC3_REVISION_200A 0x5533200a
|
|
|
|
#define DWC3_REVISION_202A 0x5533202a
|
|
|
|
#define DWC3_REVISION_210A 0x5533210a
|
|
|
|
#define DWC3_REVISION_220A 0x5533220a
|
2012-09-19 02:22:32 +08:00
|
|
|
#define DWC3_REVISION_230A 0x5533230a
|
|
|
|
#define DWC3_REVISION_240A 0x5533240a
|
|
|
|
#define DWC3_REVISION_250A 0x5533250a
|
2014-03-04 23:35:02 +08:00
|
|
|
#define DWC3_REVISION_260A 0x5533260a
|
|
|
|
#define DWC3_REVISION_270A 0x5533270a
|
|
|
|
#define DWC3_REVISION_280A 0x5533280a
|
2016-10-13 09:00:55 +08:00
|
|
|
#define DWC3_REVISION_290A 0x5533290a
|
2016-08-20 02:57:52 +08:00
|
|
|
#define DWC3_REVISION_300A 0x5533300a
|
|
|
|
#define DWC3_REVISION_310A 0x5533310a
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2015-09-05 10:15:10 +08:00
|
|
|
/*
|
|
|
|
* NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
|
|
|
|
* just so dwc31 revisions are always larger than dwc3.
|
|
|
|
*/
|
|
|
|
#define DWC3_REVISION_IS_DWC31 0x80000000
|
2016-05-21 07:34:23 +08:00
|
|
|
#define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31)
|
2016-11-15 04:32:43 +08:00
|
|
|
#define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31)
|
2015-09-05 10:15:10 +08:00
|
|
|
|
2011-08-30 20:50:40 +08:00
|
|
|
enum dwc3_ep0_next ep0_next_event;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
enum dwc3_ep0_state ep0state;
|
|
|
|
enum dwc3_link_state link_state;
|
|
|
|
|
2012-04-24 21:19:49 +08:00
|
|
|
u16 u2sel;
|
|
|
|
u16 u2pel;
|
|
|
|
u8 u1sel;
|
|
|
|
u8 u1pel;
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
u8 speed;
|
2012-04-24 21:19:49 +08:00
|
|
|
|
2017-02-01 04:58:10 +08:00
|
|
|
u8 num_eps;
|
2011-05-05 20:53:10 +08:00
|
|
|
|
2011-09-30 15:58:48 +08:00
|
|
|
struct dwc3_hwparams hwparams;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
struct dentry *root;
|
2013-01-18 16:21:34 +08:00
|
|
|
struct debugfs_regset32 *regset;
|
2012-02-10 18:21:18 +08:00
|
|
|
|
|
|
|
u8 test_mode;
|
|
|
|
u8 test_mode_nr;
|
2014-10-28 19:54:26 +08:00
|
|
|
u8 lpm_nyet_threshold;
|
2014-10-31 11:11:18 +08:00
|
|
|
u8 hird_threshold;
|
2018-03-17 06:35:44 +08:00
|
|
|
u8 rx_thr_num_pkt_prd;
|
|
|
|
u8 rx_max_burst_prd;
|
|
|
|
u8 tx_thr_num_pkt_prd;
|
|
|
|
u8 tx_max_burst_prd;
|
2013-12-20 02:12:37 +08:00
|
|
|
|
2015-05-13 20:26:49 +08:00
|
|
|
const char *hsphy_interface;
|
|
|
|
|
2016-05-16 18:14:48 +08:00
|
|
|
unsigned connected:1;
|
2013-12-20 02:12:37 +08:00
|
|
|
unsigned delayed_status:1;
|
|
|
|
unsigned ep0_bounced:1;
|
|
|
|
unsigned ep0_expect_in:1;
|
2013-12-20 02:14:29 +08:00
|
|
|
unsigned has_hibernation:1;
|
2016-11-17 19:43:47 +08:00
|
|
|
unsigned sysdev_is_parent:1;
|
2014-10-28 19:54:26 +08:00
|
|
|
unsigned has_lpm_erratum:1;
|
2014-10-31 11:11:18 +08:00
|
|
|
unsigned is_utmi_l1_suspend:1;
|
2014-10-28 19:54:23 +08:00
|
|
|
unsigned is_fpga:1;
|
2016-05-16 18:14:48 +08:00
|
|
|
unsigned pending_events:1;
|
2013-12-20 02:12:37 +08:00
|
|
|
unsigned pullups_connected:1;
|
|
|
|
unsigned setup_packet_pending:1;
|
|
|
|
unsigned three_stage_setup:1;
|
2015-03-09 22:06:12 +08:00
|
|
|
unsigned usb3_lpm_capable:1;
|
2014-10-28 19:54:25 +08:00
|
|
|
|
|
|
|
unsigned disable_scramble_quirk:1;
|
2014-10-28 19:54:27 +08:00
|
|
|
unsigned u2exit_lfps_quirk:1;
|
2014-10-28 19:54:28 +08:00
|
|
|
unsigned u2ss_inp3_quirk:1;
|
2014-10-28 19:54:29 +08:00
|
|
|
unsigned req_p1p2p3_quirk:1;
|
2014-10-28 19:54:30 +08:00
|
|
|
unsigned del_p1p2p3_quirk:1;
|
2014-10-28 19:54:31 +08:00
|
|
|
unsigned del_phy_power_chg_quirk:1;
|
2014-10-28 19:54:32 +08:00
|
|
|
unsigned lfps_filter_quirk:1;
|
2014-10-28 19:54:33 +08:00
|
|
|
unsigned rx_detect_poll_quirk:1;
|
2014-10-31 11:11:13 +08:00
|
|
|
unsigned dis_u3_susphy_quirk:1;
|
2014-10-31 11:11:14 +08:00
|
|
|
unsigned dis_u2_susphy_quirk:1;
|
2015-10-03 11:30:57 +08:00
|
|
|
unsigned dis_enblslpm_quirk:1;
|
2016-03-14 17:10:50 +08:00
|
|
|
unsigned dis_rxdet_inp3_quirk:1;
|
2016-08-16 22:44:37 +08:00
|
|
|
unsigned dis_u2_freeclk_exists_quirk:1;
|
2016-08-16 22:44:39 +08:00
|
|
|
unsigned dis_del_phy_power_chg_quirk:1;
|
2017-04-19 20:11:38 +08:00
|
|
|
unsigned dis_tx_ipgap_linecheck_quirk:1;
|
2014-10-31 11:11:12 +08:00
|
|
|
|
|
|
|
unsigned tx_de_emphasis_quirk:1;
|
|
|
|
unsigned tx_de_emphasis:2;
|
2016-11-15 04:32:43 +08:00
|
|
|
|
2017-10-31 21:11:55 +08:00
|
|
|
unsigned dis_metastability_quirk:1;
|
|
|
|
|
2016-11-15 04:32:43 +08:00
|
|
|
u16 imod_interval;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
};
|
|
|
|
|
2017-04-04 17:49:18 +08:00
|
|
|
#define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
struct dwc3_event_type {
|
|
|
|
u32 is_devspec:1;
|
2013-06-27 01:08:11 +08:00
|
|
|
u32 type:7;
|
|
|
|
u32 reserved8_31:24;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
} __packed;
|
|
|
|
|
|
|
|
#define DWC3_DEPEVT_XFERCOMPLETE 0x01
|
|
|
|
#define DWC3_DEPEVT_XFERINPROGRESS 0x02
|
|
|
|
#define DWC3_DEPEVT_XFERNOTREADY 0x03
|
|
|
|
#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
|
|
|
|
#define DWC3_DEPEVT_STREAMEVT 0x06
|
|
|
|
#define DWC3_DEPEVT_EPCMDCMPLT 0x07
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct dwc3_event_depvt - Device Endpoint Events
|
|
|
|
* @one_bit: indicates this is an endpoint event (not used)
|
|
|
|
* @endpoint_number: number of the endpoint
|
|
|
|
* @endpoint_event: The event we have:
|
|
|
|
* 0x00 - Reserved
|
|
|
|
* 0x01 - XferComplete
|
|
|
|
* 0x02 - XferInProgress
|
|
|
|
* 0x03 - XferNotReady
|
|
|
|
* 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
|
|
|
|
* 0x05 - Reserved
|
|
|
|
* 0x06 - StreamEvt
|
|
|
|
* 0x07 - EPCmdCmplt
|
|
|
|
* @reserved11_10: Reserved, don't use.
|
|
|
|
* @status: Indicates the status of the event. Refer to databook for
|
|
|
|
* more information.
|
|
|
|
* @parameters: Parameters of the current event. Refer to databook for
|
|
|
|
* more information.
|
|
|
|
*/
|
|
|
|
struct dwc3_event_depevt {
|
|
|
|
u32 one_bit:1;
|
|
|
|
u32 endpoint_number:5;
|
|
|
|
u32 endpoint_event:4;
|
|
|
|
u32 reserved11_10:2;
|
|
|
|
u32 status:4;
|
2012-01-18 23:06:03 +08:00
|
|
|
|
|
|
|
/* Within XferNotReady */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
|
2012-01-18 23:06:03 +08:00
|
|
|
|
|
|
|
/* Within XferComplete */
|
2017-03-30 14:46:40 +08:00
|
|
|
#define DEPEVT_STATUS_BUSERR BIT(0)
|
|
|
|
#define DEPEVT_STATUS_SHORT BIT(1)
|
|
|
|
#define DEPEVT_STATUS_IOC BIT(2)
|
|
|
|
#define DEPEVT_STATUS_LST BIT(3)
|
2011-08-28 03:04:32 +08:00
|
|
|
|
2011-09-30 15:58:47 +08:00
|
|
|
/* Stream event only */
|
|
|
|
#define DEPEVT_STREAMEVT_FOUND 1
|
|
|
|
#define DEPEVT_STREAMEVT_NOTFOUND 2
|
|
|
|
|
2011-08-28 03:04:32 +08:00
|
|
|
/* Control-only Status */
|
|
|
|
#define DEPEVT_STATUS_CONTROL_DATA 1
|
|
|
|
#define DEPEVT_STATUS_CONTROL_STATUS 2
|
2016-09-26 17:54:04 +08:00
|
|
|
#define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
|
2011-08-28 03:04:32 +08:00
|
|
|
|
2016-02-12 23:21:46 +08:00
|
|
|
/* In response to Start Transfer */
|
|
|
|
#define DEPEVT_TRANSFER_NO_RESOURCE 1
|
|
|
|
#define DEPEVT_TRANSFER_BUS_EXPIRY 2
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
u32 parameters:16;
|
2016-10-31 19:38:36 +08:00
|
|
|
|
|
|
|
/* For Command Complete Events */
|
|
|
|
#define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
} __packed;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct dwc3_event_devt - Device Events
|
|
|
|
* @one_bit: indicates this is a non-endpoint event (not used)
|
|
|
|
* @device_event: indicates it's a device event. Should read as 0x00
|
|
|
|
* @type: indicates the type of device event.
|
|
|
|
* 0 - DisconnEvt
|
|
|
|
* 1 - USBRst
|
|
|
|
* 2 - ConnectDone
|
|
|
|
* 3 - ULStChng
|
|
|
|
* 4 - WkUpEvt
|
|
|
|
* 5 - Reserved
|
|
|
|
* 6 - EOPF
|
|
|
|
* 7 - SOF
|
|
|
|
* 8 - Reserved
|
|
|
|
* 9 - ErrticErr
|
|
|
|
* 10 - CmdCmplt
|
|
|
|
* 11 - EvntOverflow
|
|
|
|
* 12 - VndrDevTstRcved
|
|
|
|
* @reserved15_12: Reserved, not used
|
|
|
|
* @event_info: Information about this event
|
2014-01-07 17:45:50 +08:00
|
|
|
* @reserved31_25: Reserved, not used
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*/
|
|
|
|
struct dwc3_event_devt {
|
|
|
|
u32 one_bit:1;
|
|
|
|
u32 device_event:7;
|
|
|
|
u32 type:4;
|
|
|
|
u32 reserved15_12:4;
|
2014-01-07 17:45:50 +08:00
|
|
|
u32 event_info:9;
|
|
|
|
u32 reserved31_25:7;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
} __packed;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct dwc3_event_gevt - Other Core Events
|
|
|
|
* @one_bit: indicates this is a non-endpoint event (not used)
|
|
|
|
* @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
|
|
|
|
* @phy_port_number: self-explanatory
|
|
|
|
* @reserved31_12: Reserved, not used.
|
|
|
|
*/
|
|
|
|
struct dwc3_event_gevt {
|
|
|
|
u32 one_bit:1;
|
|
|
|
u32 device_event:7;
|
|
|
|
u32 phy_port_number:4;
|
|
|
|
u32 reserved31_12:20;
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* union dwc3_event - representation of Event Buffer contents
|
|
|
|
* @raw: raw 32-bit event
|
|
|
|
* @type: the type of the event
|
|
|
|
* @depevt: Device Endpoint Event
|
|
|
|
* @devt: Device Event
|
|
|
|
* @gevt: Global Event
|
|
|
|
*/
|
|
|
|
union dwc3_event {
|
|
|
|
u32 raw;
|
|
|
|
struct dwc3_event_type type;
|
|
|
|
struct dwc3_event_depevt depevt;
|
|
|
|
struct dwc3_event_devt devt;
|
|
|
|
struct dwc3_event_gevt gevt;
|
|
|
|
};
|
|
|
|
|
2014-03-04 23:23:50 +08:00
|
|
|
/**
|
|
|
|
* struct dwc3_gadget_ep_cmd_params - representation of endpoint command
|
|
|
|
* parameters
|
|
|
|
* @param2: third parameter
|
|
|
|
* @param1: second parameter
|
|
|
|
* @param0: first parameter
|
|
|
|
*/
|
|
|
|
struct dwc3_gadget_ep_cmd_params {
|
|
|
|
u32 param2;
|
|
|
|
u32 param1;
|
|
|
|
u32 param0;
|
|
|
|
};
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/*
|
|
|
|
* DWC3 Features to be used as Driver Data
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define DWC3_HAS_PERIPHERAL BIT(0)
|
|
|
|
#define DWC3_HAS_XHCI BIT(1)
|
|
|
|
#define DWC3_HAS_OTG BIT(3)
|
|
|
|
|
2011-10-12 19:08:26 +08:00
|
|
|
/* prototypes */
|
2018-02-27 19:30:19 +08:00
|
|
|
void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
|
2011-11-01 05:25:40 +08:00
|
|
|
void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
|
2016-04-14 20:03:39 +08:00
|
|
|
u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
|
2011-11-01 05:25:40 +08:00
|
|
|
|
2016-11-11 09:08:48 +08:00
|
|
|
/* check whether we are on the DWC_usb3 core */
|
|
|
|
static inline bool dwc3_is_usb3(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
return !(dwc->revision & DWC3_REVISION_IS_DWC31);
|
|
|
|
}
|
|
|
|
|
2016-02-06 09:08:18 +08:00
|
|
|
/* check whether we are on the DWC_usb31 core */
|
|
|
|
static inline bool dwc3_is_usb31(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
|
|
|
|
}
|
|
|
|
|
2016-11-15 04:32:43 +08:00
|
|
|
bool dwc3_has_imod(struct dwc3 *dwc);
|
|
|
|
|
2018-02-27 19:30:19 +08:00
|
|
|
int dwc3_event_buffers_setup(struct dwc3 *dwc);
|
|
|
|
void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
|
|
|
|
|
2013-01-15 18:39:21 +08:00
|
|
|
#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
|
2011-10-12 19:08:26 +08:00
|
|
|
int dwc3_host_init(struct dwc3 *dwc);
|
|
|
|
void dwc3_host_exit(struct dwc3 *dwc);
|
2013-01-15 18:39:21 +08:00
|
|
|
#else
|
|
|
|
static inline int dwc3_host_init(struct dwc3 *dwc)
|
|
|
|
{ return 0; }
|
|
|
|
static inline void dwc3_host_exit(struct dwc3 *dwc)
|
|
|
|
{ }
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
|
2011-10-12 19:15:49 +08:00
|
|
|
int dwc3_gadget_init(struct dwc3 *dwc);
|
|
|
|
void dwc3_gadget_exit(struct dwc3 *dwc);
|
2014-03-04 23:23:50 +08:00
|
|
|
int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
|
|
|
|
int dwc3_gadget_get_link_state(struct dwc3 *dwc);
|
|
|
|
int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
|
2016-04-12 21:42:43 +08:00
|
|
|
int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
|
|
|
|
struct dwc3_gadget_ep_cmd_params *params);
|
2014-09-05 22:47:44 +08:00
|
|
|
int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
|
2013-01-15 18:39:21 +08:00
|
|
|
#else
|
|
|
|
static inline int dwc3_gadget_init(struct dwc3 *dwc)
|
|
|
|
{ return 0; }
|
|
|
|
static inline void dwc3_gadget_exit(struct dwc3 *dwc)
|
|
|
|
{ }
|
2014-03-04 23:23:50 +08:00
|
|
|
static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
|
|
|
|
{ return 0; }
|
|
|
|
static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
|
|
|
|
{ return 0; }
|
|
|
|
static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
|
|
|
|
enum dwc3_link_state state)
|
|
|
|
{ return 0; }
|
|
|
|
|
2016-04-12 21:42:43 +08:00
|
|
|
static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
|
|
|
|
struct dwc3_gadget_ep_cmd_params *params)
|
2014-03-04 23:23:50 +08:00
|
|
|
{ return 0; }
|
|
|
|
static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
|
|
|
|
int cmd, u32 param)
|
|
|
|
{ return 0; }
|
2013-01-15 18:39:21 +08:00
|
|
|
#endif
|
2011-10-12 19:15:49 +08:00
|
|
|
|
2017-04-05 18:39:31 +08:00
|
|
|
#if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
|
|
|
|
int dwc3_drd_init(struct dwc3 *dwc);
|
|
|
|
void dwc3_drd_exit(struct dwc3 *dwc);
|
2018-02-27 19:30:19 +08:00
|
|
|
void dwc3_otg_init(struct dwc3 *dwc);
|
|
|
|
void dwc3_otg_exit(struct dwc3 *dwc);
|
|
|
|
void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
|
|
|
|
void dwc3_otg_host_init(struct dwc3 *dwc);
|
2017-04-05 18:39:31 +08:00
|
|
|
#else
|
|
|
|
static inline int dwc3_drd_init(struct dwc3 *dwc)
|
|
|
|
{ return 0; }
|
|
|
|
static inline void dwc3_drd_exit(struct dwc3 *dwc)
|
|
|
|
{ }
|
2018-02-27 19:30:19 +08:00
|
|
|
static inline void dwc3_otg_init(struct dwc3 *dwc)
|
|
|
|
{ }
|
|
|
|
static inline void dwc3_otg_exit(struct dwc3 *dwc)
|
|
|
|
{ }
|
|
|
|
static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
|
|
|
|
{ }
|
|
|
|
static inline void dwc3_otg_host_init(struct dwc3 *dwc)
|
|
|
|
{ }
|
2017-04-05 18:39:31 +08:00
|
|
|
#endif
|
|
|
|
|
2012-04-30 19:56:33 +08:00
|
|
|
/* power management interface */
|
|
|
|
#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
|
|
|
|
int dwc3_gadget_suspend(struct dwc3 *dwc);
|
|
|
|
int dwc3_gadget_resume(struct dwc3 *dwc);
|
2016-05-16 18:14:48 +08:00
|
|
|
void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
|
2012-04-30 19:56:33 +08:00
|
|
|
#else
|
|
|
|
static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int dwc3_gadget_resume(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2016-05-16 18:14:48 +08:00
|
|
|
|
|
|
|
static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
}
|
2012-04-30 19:56:33 +08:00
|
|
|
#endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
|
|
|
|
|
2015-05-13 20:26:51 +08:00
|
|
|
#if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
|
|
|
|
int dwc3_ulpi_init(struct dwc3 *dwc);
|
|
|
|
void dwc3_ulpi_exit(struct dwc3 *dwc);
|
|
|
|
#else
|
|
|
|
static inline int dwc3_ulpi_init(struct dwc3 *dwc)
|
|
|
|
{ return 0; }
|
|
|
|
static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
|
|
|
|
{ }
|
|
|
|
#endif
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#endif /* __DRIVERS_USB_DWC3_CORE_H */
|