2007-09-12 10:13:17 +08:00
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/*
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* linux/arch/arm/mach-pxa/pxa3xx.c
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*
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* code specific to pxa3xx aka Monahans
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*
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* Copyright (C) 2006 Marvell International Ltd.
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*
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2007-10-30 15:01:38 +08:00
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* 2007-09-02: eric miao <eric.miao@marvell.com>
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2007-09-12 10:13:17 +08:00
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* initial version
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pm.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <asm/hardware.h>
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#include <asm/arch/pxa3xx-regs.h>
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#include <asm/arch/ohci.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/ssp.h>
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#include "generic.h"
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#include "devices.h"
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#include "clock.h"
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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/* Ring Oscillator Clock: 60MHz */
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#define RO_CLK 60000000
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#define ACCR_D0CS (1 << 26)
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/* crystal frequency to static memory controller multiplier (SMCFS) */
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static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
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/* crystal frequency to HSIO bus frequency multiplier (HSS) */
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static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa3xx_get_clk_frequency_khz(int info)
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{
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unsigned long acsr, xclkcfg;
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unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
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/* Read XCLKCFG register turbo bit */
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__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
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t = xclkcfg & 0x1;
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acsr = ACSR;
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xl = acsr & 0x1f;
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xn = (acsr >> 8) & 0x7;
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hss = (acsr >> 14) & 0x3;
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XL = xl * BASE_CLK;
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XN = xn * XL;
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ro = acsr & ACCR_D0CS;
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CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
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HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
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if (info) {
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pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
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RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
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(ro) ? "" : "in");
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pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
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XL / 1000000, (XL % 1000000) / 10000, xl);
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pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
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XN / 1000000, (XN % 1000000) / 10000, xn,
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(t) ? "" : "in");
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pr_info("HSIO bus clock: %d.%02dMHz\n",
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HSS / 1000000, (HSS % 1000000) / 10000);
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}
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return CLK;
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}
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/*
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* Return the current static memory controller clock frequency
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* in units of 10kHz
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*/
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unsigned int pxa3xx_get_memclk_frequency_10khz(void)
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{
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unsigned long acsr;
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unsigned int smcfs, clk = 0;
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acsr = ACSR;
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smcfs = (acsr >> 23) & 0x7;
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clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
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return (clk / 10000);
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}
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/*
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* Return the current HSIO bus clock frequency
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*/
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static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
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{
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unsigned long acsr;
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unsigned int hss, hsio_clk;
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acsr = ACSR;
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hss = (acsr >> 14) & 0x3;
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hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
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return hsio_clk;
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}
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static void clk_pxa3xx_cken_enable(struct clk *clk)
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{
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unsigned long mask = 1ul << (clk->cken & 0x1f);
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local_irq_disable();
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if (clk->cken < 32)
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CKENA |= mask;
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else
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CKENB |= mask;
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local_irq_enable();
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}
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static void clk_pxa3xx_cken_disable(struct clk *clk)
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{
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unsigned long mask = 1ul << (clk->cken & 0x1f);
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local_irq_disable();
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if (clk->cken < 32)
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CKENA &= ~mask;
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else
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CKENB &= ~mask;
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local_irq_enable();
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}
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2007-10-30 15:10:18 +08:00
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static const struct clkops clk_pxa3xx_cken_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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};
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2007-09-12 10:13:17 +08:00
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static const struct clkops clk_pxa3xx_hsio_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_hsio_getrate,
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};
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2007-10-30 15:10:18 +08:00
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#define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \
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{ \
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.name = _name, \
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.dev = _dev, \
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.ops = &clk_pxa3xx_cken_ops, \
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.rate = _rate, \
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.cken = CKEN_##_cken, \
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.delay = _delay, \
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}
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#define PXA3xx_CK(_name, _cken, _ops, _dev) \
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{ \
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.name = _name, \
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.dev = _dev, \
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.ops = _ops, \
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.cken = CKEN_##_cken, \
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}
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2007-09-12 10:13:17 +08:00
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static struct clk pxa3xx_clks[] = {
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2007-10-30 15:10:18 +08:00
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PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
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PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
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2007-09-12 10:13:17 +08:00
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2007-10-30 15:10:18 +08:00
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PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
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PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
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PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
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2007-09-12 10:13:17 +08:00
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2007-10-30 15:10:18 +08:00
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PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
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PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
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2007-09-12 10:13:17 +08:00
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};
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void __init pxa3xx_init_irq(void)
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{
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/* enable CP6 access */
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u32 value;
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__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
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value |= (1 << 6);
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__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
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pxa_init_irq_low();
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pxa_init_irq_high();
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pxa_init_irq_gpio(128);
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}
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/*
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* device registration specific to PXA3xx.
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*/
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static struct platform_device *devices[] __initdata = {
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&pxa_device_mci,
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&pxa_device_udc,
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&pxa_device_fb,
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&pxa_device_ffuart,
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&pxa_device_btuart,
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&pxa_device_stuart,
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&pxa_device_i2c,
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&pxa_device_i2s,
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&pxa_device_ficp,
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&pxa_device_rtc,
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};
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static int __init pxa3xx_init(void)
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{
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int ret = 0;
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if (cpu_is_pxa3xx()) {
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clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
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if ((ret = pxa_init_dma(32)))
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return ret;
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return platform_add_devices(devices, ARRAY_SIZE(devices));
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}
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return 0;
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}
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subsys_initcall(pxa3xx_init);
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