2009-06-11 12:54:01 +08:00
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/*
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* Performance counter support for POWER7 processors.
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*
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* Copyright 2009 Paul Mackerras, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 18:02:48 +08:00
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#include <linux/perf_event.h>
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2009-06-17 19:52:09 +08:00
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#include <linux/string.h>
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2009-06-11 12:54:01 +08:00
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#include <asm/reg.h>
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2009-06-17 19:52:09 +08:00
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#include <asm/cputable.h>
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2009-06-11 12:54:01 +08:00
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/*
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* Bits in event code for POWER7
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*/
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#define PM_PMC_SH 16 /* PMC number (1-based) for direct events */
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#define PM_PMC_MSK 0xf
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#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
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#define PM_UNIT_SH 12 /* TTMMUX number and setting - unit select */
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#define PM_UNIT_MSK 0xf
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#define PM_COMBINE_SH 11 /* Combined event bit */
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#define PM_COMBINE_MSK 1
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#define PM_COMBINE_MSKS 0x800
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#define PM_L2SEL_SH 8 /* L2 event select */
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#define PM_L2SEL_MSK 7
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#define PM_PMCSEL_MSK 0xff
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/*
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* Bits in MMCR1 for POWER7
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*/
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#define MMCR1_TTM0SEL_SH 60
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#define MMCR1_TTM1SEL_SH 56
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#define MMCR1_TTM2SEL_SH 52
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#define MMCR1_TTM3SEL_SH 48
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#define MMCR1_TTMSEL_MSK 0xf
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#define MMCR1_L2SEL_SH 45
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#define MMCR1_L2SEL_MSK 7
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#define MMCR1_PMC1_COMBINE_SH 35
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#define MMCR1_PMC2_COMBINE_SH 34
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#define MMCR1_PMC3_COMBINE_SH 33
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#define MMCR1_PMC4_COMBINE_SH 32
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#define MMCR1_PMC1SEL_SH 24
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#define MMCR1_PMC2SEL_SH 16
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#define MMCR1_PMC3SEL_SH 8
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#define MMCR1_PMC4SEL_SH 0
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#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
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#define MMCR1_PMCSEL_MSK 0xff
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2013-01-23 14:23:53 +08:00
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/*
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* Power7 event codes.
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*/
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#define PME_PM_CYC 0x1e
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#define PME_PM_GCT_NOSLOT_CYC 0x100f8
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#define PME_PM_CMPLU_STALL 0x4000a
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#define PME_PM_INST_CMPL 0x2
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#define PME_PM_LD_REF_L1 0xc880
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#define PME_PM_LD_MISS_L1 0x400f0
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#define PME_PM_BRU_FIN 0x10068
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#define PME_PM_BRU_MPRED 0x400f6
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2013-04-06 23:48:26 +08:00
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#define PME_PM_CMPLU_STALL_FXU 0x20014
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#define PME_PM_CMPLU_STALL_DIV 0x40014
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#define PME_PM_CMPLU_STALL_SCALAR 0x40012
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#define PME_PM_CMPLU_STALL_SCALAR_LONG 0x20018
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#define PME_PM_CMPLU_STALL_VECTOR 0x2001c
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#define PME_PM_CMPLU_STALL_VECTOR_LONG 0x4004a
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#define PME_PM_CMPLU_STALL_LSU 0x20012
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#define PME_PM_CMPLU_STALL_REJECT 0x40016
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#define PME_PM_CMPLU_STALL_ERAT_MISS 0x40018
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#define PME_PM_CMPLU_STALL_DCACHE_MISS 0x20016
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#define PME_PM_CMPLU_STALL_STORE 0x2004a
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#define PME_PM_CMPLU_STALL_THRD 0x1001c
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#define PME_PM_CMPLU_STALL_IFU 0x4004c
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#define PME_PM_CMPLU_STALL_BRU 0x4004e
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#define PME_PM_GCT_NOSLOT_IC_MISS 0x2001a
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#define PME_PM_GCT_NOSLOT_BR_MPRED 0x4001a
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#define PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS 0x4001c
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#define PME_PM_GRP_CMPL 0x30004
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#define PME_PM_1PLUS_PPC_CMPL 0x100f2
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#define PME_PM_CMPLU_STALL_DFU 0x2003c
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#define PME_PM_RUN_CYC 0x200f4
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#define PME_PM_RUN_INST_CMPL 0x400fa
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2009-06-11 12:54:01 +08:00
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/*
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* Layout of constraint bits:
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* 6666555555555544444444443333333333222222222211111111110000000000
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* 3210987654321098765432109876543210987654321098765432109876543210
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2012-10-31 00:09:56 +08:00
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* < >< ><><><><><><>
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* L2 NC P6P5P4P3P2P1
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*
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* L2 - 16-18 - Required L2SEL value (select field)
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2009-06-11 12:54:01 +08:00
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*
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* NC - number of counters
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* 15: NC error 0x8000
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* 12-14: number of events needing PMC1-4 0x7000
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*
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* P6
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* 11: P6 error 0x800
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* 10-11: Count of events needing PMC6
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*
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* P1..P5
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* 0-9: Count of events needing PMC1..PMC5
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*/
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2009-06-17 19:51:13 +08:00
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static int power7_get_constraint(u64 event, unsigned long *maskp,
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unsigned long *valp)
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2009-06-11 12:54:01 +08:00
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{
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2012-10-31 00:09:56 +08:00
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int pmc, sh, unit;
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2009-06-17 19:51:13 +08:00
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unsigned long mask = 0, value = 0;
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2009-06-11 12:54:01 +08:00
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc > 6)
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return -1;
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sh = (pmc - 1) * 2;
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mask |= 2 << sh;
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value |= 1 << sh;
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if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4))
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return -1;
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}
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if (pmc < 5) {
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/* need a counter from PMC1-4 set */
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mask |= 0x8000;
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value |= 0x1000;
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}
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2012-10-31 00:09:56 +08:00
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unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
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if (unit == 6) {
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/* L2SEL must be identical across events */
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int l2sel = (event >> PM_L2SEL_SH) & PM_L2SEL_MSK;
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mask |= 0x7 << 16;
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value |= l2sel << 16;
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}
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2009-06-11 12:54:01 +08:00
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*maskp = mask;
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*valp = value;
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return 0;
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}
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#define MAX_ALT 2 /* at most 2 alternatives for any event */
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static const unsigned int event_alternatives[][MAX_ALT] = {
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{ 0x200f2, 0x300f2 }, /* PM_INST_DISP */
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{ 0x200f4, 0x600f4 }, /* PM_RUN_CYC */
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{ 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */
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};
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/*
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* Scan the alternatives table for a match and return the
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* index into the alternatives table if found, else -1.
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*/
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static int find_alternative(u64 event)
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{
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int i, j;
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for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
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if (event < event_alternatives[i][0])
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break;
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for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
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if (event == event_alternatives[i][j])
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return i;
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}
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return -1;
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}
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static s64 find_alternative_decode(u64 event)
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{
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int pmc, psel;
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/* this only handles the 4x decode events */
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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psel = event & PM_PMCSEL_MSK;
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if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40)
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return event - (1 << PM_PMC_SH) + 8;
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if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48)
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return event + (1 << PM_PMC_SH) - 8;
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return -1;
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}
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static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
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{
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int i, j, nalt = 1;
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s64 ae;
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alt[0] = event;
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nalt = 1;
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i = find_alternative(event);
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if (i >= 0) {
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for (j = 0; j < MAX_ALT; ++j) {
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ae = event_alternatives[i][j];
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if (ae && ae != event)
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alt[nalt++] = ae;
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}
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} else {
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ae = find_alternative_decode(event);
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if (ae > 0)
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alt[nalt++] = ae;
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}
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if (flags & PPMU_ONLY_COUNT_RUN) {
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/*
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* We're only counting in RUN state,
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* so PM_CYC is equivalent to PM_RUN_CYC
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* and PM_INST_CMPL === PM_RUN_INST_CMPL.
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* This doesn't include alternatives that don't provide
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* any extra flexibility in assigning PMCs.
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*/
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j = nalt;
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for (i = 0; i < nalt; ++i) {
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switch (alt[i]) {
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case 0x1e: /* PM_CYC */
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alt[j++] = 0x600f4; /* PM_RUN_CYC */
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break;
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case 0x600f4: /* PM_RUN_CYC */
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alt[j++] = 0x1e;
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break;
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case 0x2: /* PM_PPC_CMPL */
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alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
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break;
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case 0x500fa: /* PM_RUN_INST_CMPL */
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alt[j++] = 0x2; /* PM_PPC_CMPL */
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break;
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}
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}
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nalt = j;
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}
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return nalt;
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}
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/*
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* Returns 1 if event counts things relating to marked instructions
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* and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
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*/
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static int power7_marked_instr_event(u64 event)
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{
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int pmc, psel;
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int unit;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
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psel = event & PM_PMCSEL_MSK & ~1; /* trim off edge/level bit */
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if (pmc >= 5)
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return 0;
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switch (psel >> 4) {
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case 2:
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return pmc == 2 || pmc == 4;
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|
|
|
|
case 3:
|
|
|
|
|
if (psel == 0x3c)
|
|
|
|
|
return pmc == 1;
|
|
|
|
|
if (psel == 0x3e)
|
|
|
|
|
return pmc != 2;
|
|
|
|
|
return 1;
|
|
|
|
|
case 4:
|
|
|
|
|
case 5:
|
|
|
|
|
return unit == 0xd;
|
|
|
|
|
case 6:
|
|
|
|
|
if (psel == 0x64)
|
|
|
|
|
return pmc >= 3;
|
|
|
|
|
case 8:
|
|
|
|
|
return unit == 0xd;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int power7_compute_mmcr(u64 event[], int n_ev,
|
2009-06-17 19:51:13 +08:00
|
|
|
unsigned int hwc[], unsigned long mmcr[])
|
2009-06-11 12:54:01 +08:00
|
|
|
{
|
2009-06-17 19:51:13 +08:00
|
|
|
unsigned long mmcr1 = 0;
|
2009-10-28 02:31:29 +08:00
|
|
|
unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
|
2009-06-11 12:54:01 +08:00
|
|
|
unsigned int pmc, unit, combine, l2sel, psel;
|
|
|
|
|
unsigned int pmc_inuse = 0;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
/* First pass to count resource use */
|
|
|
|
|
for (i = 0; i < n_ev; ++i) {
|
|
|
|
|
pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
|
|
|
|
|
if (pmc) {
|
|
|
|
|
if (pmc > 6)
|
|
|
|
|
return -1;
|
|
|
|
|
if (pmc_inuse & (1 << (pmc - 1)))
|
|
|
|
|
return -1;
|
|
|
|
|
pmc_inuse |= 1 << (pmc - 1);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Second pass: assign PMCs, set all MMCR1 fields */
|
|
|
|
|
for (i = 0; i < n_ev; ++i) {
|
|
|
|
|
pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
|
|
|
|
|
unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
|
|
|
|
|
combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK;
|
|
|
|
|
l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK;
|
|
|
|
|
psel = event[i] & PM_PMCSEL_MSK;
|
|
|
|
|
if (!pmc) {
|
|
|
|
|
/* Bus event or any-PMC direct event */
|
|
|
|
|
for (pmc = 0; pmc < 4; ++pmc) {
|
|
|
|
|
if (!(pmc_inuse & (1 << pmc)))
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
if (pmc >= 4)
|
|
|
|
|
return -1;
|
|
|
|
|
pmc_inuse |= 1 << pmc;
|
|
|
|
|
} else {
|
|
|
|
|
/* Direct or decoded event */
|
|
|
|
|
--pmc;
|
|
|
|
|
}
|
|
|
|
|
if (pmc <= 3) {
|
2009-06-17 19:51:13 +08:00
|
|
|
mmcr1 |= (unsigned long) unit
|
|
|
|
|
<< (MMCR1_TTM0SEL_SH - 4 * pmc);
|
|
|
|
|
mmcr1 |= (unsigned long) combine
|
|
|
|
|
<< (MMCR1_PMC1_COMBINE_SH - pmc);
|
2009-06-11 12:54:01 +08:00
|
|
|
mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
|
|
|
|
|
if (unit == 6) /* L2 events */
|
2009-06-17 19:51:13 +08:00
|
|
|
mmcr1 |= (unsigned long) l2sel
|
|
|
|
|
<< MMCR1_L2SEL_SH;
|
2009-06-11 12:54:01 +08:00
|
|
|
}
|
|
|
|
|
if (power7_marked_instr_event(event[i]))
|
|
|
|
|
mmcra |= MMCRA_SAMPLE_ENABLE;
|
|
|
|
|
hwc[i] = pmc;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return MMCRx values */
|
|
|
|
|
mmcr[0] = 0;
|
|
|
|
|
if (pmc_inuse & 1)
|
|
|
|
|
mmcr[0] = MMCR0_PMC1CE;
|
|
|
|
|
if (pmc_inuse & 0x3e)
|
|
|
|
|
mmcr[0] |= MMCR0_PMCjCE;
|
|
|
|
|
mmcr[1] = mmcr1;
|
|
|
|
|
mmcr[2] = mmcra;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2009-06-17 19:51:13 +08:00
|
|
|
static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
|
2009-06-11 12:54:01 +08:00
|
|
|
{
|
|
|
|
|
if (pmc <= 3)
|
2009-06-17 19:51:13 +08:00
|
|
|
mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
|
2009-06-11 12:54:01 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int power7_generic_events[] = {
|
2013-01-23 14:23:53 +08:00
|
|
|
[PERF_COUNT_HW_CPU_CYCLES] = PME_PM_CYC,
|
|
|
|
|
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PME_PM_GCT_NOSLOT_CYC,
|
|
|
|
|
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PME_PM_CMPLU_STALL,
|
|
|
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = PME_PM_INST_CMPL,
|
|
|
|
|
[PERF_COUNT_HW_CACHE_REFERENCES] = PME_PM_LD_REF_L1,
|
|
|
|
|
[PERF_COUNT_HW_CACHE_MISSES] = PME_PM_LD_MISS_L1,
|
|
|
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PME_PM_BRU_FIN,
|
|
|
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = PME_PM_BRU_MPRED,
|
2009-06-11 12:54:01 +08:00
|
|
|
};
|
|
|
|
|
|
2009-06-11 12:55:42 +08:00
|
|
|
#define C(x) PERF_COUNT_HW_CACHE_##x
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Table of generalized cache-related events.
|
|
|
|
|
* 0 means not supported, -1 means nonsensical, other values
|
|
|
|
|
* are event codes.
|
|
|
|
|
*/
|
|
|
|
|
static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
|
|
|
|
|
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
|
2009-09-03 09:52:02 +08:00
|
|
|
[C(OP_READ)] = { 0xc880, 0x400f0 },
|
2009-06-11 12:55:42 +08:00
|
|
|
[C(OP_WRITE)] = { 0, 0x300f0 },
|
|
|
|
|
[C(OP_PREFETCH)] = { 0xd8b8, 0 },
|
|
|
|
|
},
|
|
|
|
|
[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
|
|
|
[C(OP_READ)] = { 0, 0x200fc },
|
|
|
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
|
|
|
[C(OP_PREFETCH)] = { 0x408a, 0 },
|
|
|
|
|
},
|
2009-06-11 20:19:11 +08:00
|
|
|
[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
|
2009-09-03 09:52:02 +08:00
|
|
|
[C(OP_READ)] = { 0x16080, 0x26080 },
|
|
|
|
|
[C(OP_WRITE)] = { 0x16082, 0x26082 },
|
2009-06-11 12:55:42 +08:00
|
|
|
[C(OP_PREFETCH)] = { 0, 0 },
|
|
|
|
|
},
|
|
|
|
|
[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
|
|
|
[C(OP_READ)] = { 0, 0x300fc },
|
|
|
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
|
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
|
|
|
|
},
|
|
|
|
|
[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
|
|
|
[C(OP_READ)] = { 0, 0x400fc },
|
|
|
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
|
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
|
|
|
|
},
|
|
|
|
|
[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
|
|
|
[C(OP_READ)] = { 0x10068, 0x400f6 },
|
|
|
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
|
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
|
|
|
|
},
|
2011-04-23 05:37:06 +08:00
|
|
|
[C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
|
|
|
[C(OP_READ)] = { -1, -1 },
|
|
|
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
|
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
|
|
|
|
},
|
2009-06-11 12:55:42 +08:00
|
|
|
};
|
|
|
|
|
|
2013-01-23 14:24:54 +08:00
|
|
|
|
|
|
|
|
GENERIC_EVENT_ATTR(cpu-cycles, CYC);
|
|
|
|
|
GENERIC_EVENT_ATTR(stalled-cycles-frontend, GCT_NOSLOT_CYC);
|
|
|
|
|
GENERIC_EVENT_ATTR(stalled-cycles-backend, CMPLU_STALL);
|
|
|
|
|
GENERIC_EVENT_ATTR(instructions, INST_CMPL);
|
|
|
|
|
GENERIC_EVENT_ATTR(cache-references, LD_REF_L1);
|
|
|
|
|
GENERIC_EVENT_ATTR(cache-misses, LD_MISS_L1);
|
|
|
|
|
GENERIC_EVENT_ATTR(branch-instructions, BRU_FIN);
|
|
|
|
|
GENERIC_EVENT_ATTR(branch-misses, BRU_MPRED);
|
|
|
|
|
|
2013-01-23 14:25:29 +08:00
|
|
|
POWER_EVENT_ATTR(CYC, CYC);
|
|
|
|
|
POWER_EVENT_ATTR(GCT_NOSLOT_CYC, GCT_NOSLOT_CYC);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL, CMPLU_STALL);
|
|
|
|
|
POWER_EVENT_ATTR(INST_CMPL, INST_CMPL);
|
|
|
|
|
POWER_EVENT_ATTR(LD_REF_L1, LD_REF_L1);
|
|
|
|
|
POWER_EVENT_ATTR(LD_MISS_L1, LD_MISS_L1);
|
|
|
|
|
POWER_EVENT_ATTR(BRU_FIN, BRU_FIN)
|
|
|
|
|
POWER_EVENT_ATTR(BRU_MPRED, BRU_MPRED);
|
|
|
|
|
|
2013-04-06 23:48:26 +08:00
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_FXU, CMPLU_STALL_FXU);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_DIV, CMPLU_STALL_DIV);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_SCALAR, CMPLU_STALL_SCALAR);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_SCALAR_LONG, CMPLU_STALL_SCALAR_LONG);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_VECTOR, CMPLU_STALL_VECTOR);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_VECTOR_LONG, CMPLU_STALL_VECTOR_LONG);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_LSU, CMPLU_STALL_LSU);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_REJECT, CMPLU_STALL_REJECT);
|
|
|
|
|
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_ERAT_MISS, CMPLU_STALL_ERAT_MISS);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_DCACHE_MISS, CMPLU_STALL_DCACHE_MISS);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_STORE, CMPLU_STALL_STORE);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_THRD, CMPLU_STALL_THRD);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_IFU, CMPLU_STALL_IFU);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_BRU, CMPLU_STALL_BRU);
|
|
|
|
|
POWER_EVENT_ATTR(GCT_NOSLOT_IC_MISS, GCT_NOSLOT_IC_MISS);
|
|
|
|
|
|
|
|
|
|
POWER_EVENT_ATTR(GCT_NOSLOT_BR_MPRED, GCT_NOSLOT_BR_MPRED);
|
|
|
|
|
POWER_EVENT_ATTR(GCT_NOSLOT_BR_MPRED_IC_MISS, GCT_NOSLOT_BR_MPRED_IC_MISS);
|
|
|
|
|
POWER_EVENT_ATTR(GRP_CMPL, GRP_CMPL);
|
|
|
|
|
POWER_EVENT_ATTR(1PLUS_PPC_CMPL, 1PLUS_PPC_CMPL);
|
|
|
|
|
POWER_EVENT_ATTR(CMPLU_STALL_DFU, CMPLU_STALL_DFU);
|
|
|
|
|
POWER_EVENT_ATTR(RUN_CYC, RUN_CYC);
|
|
|
|
|
POWER_EVENT_ATTR(RUN_INST_CMPL, RUN_INST_CMPL);
|
|
|
|
|
|
2013-01-23 14:24:54 +08:00
|
|
|
static struct attribute *power7_events_attr[] = {
|
|
|
|
|
GENERIC_EVENT_PTR(CYC),
|
|
|
|
|
GENERIC_EVENT_PTR(GCT_NOSLOT_CYC),
|
|
|
|
|
GENERIC_EVENT_PTR(CMPLU_STALL),
|
|
|
|
|
GENERIC_EVENT_PTR(INST_CMPL),
|
|
|
|
|
GENERIC_EVENT_PTR(LD_REF_L1),
|
|
|
|
|
GENERIC_EVENT_PTR(LD_MISS_L1),
|
|
|
|
|
GENERIC_EVENT_PTR(BRU_FIN),
|
|
|
|
|
GENERIC_EVENT_PTR(BRU_MPRED),
|
2013-01-23 14:25:29 +08:00
|
|
|
|
|
|
|
|
POWER_EVENT_PTR(CYC),
|
|
|
|
|
POWER_EVENT_PTR(GCT_NOSLOT_CYC),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL),
|
|
|
|
|
POWER_EVENT_PTR(INST_CMPL),
|
|
|
|
|
POWER_EVENT_PTR(LD_REF_L1),
|
|
|
|
|
POWER_EVENT_PTR(LD_MISS_L1),
|
|
|
|
|
POWER_EVENT_PTR(BRU_FIN),
|
|
|
|
|
POWER_EVENT_PTR(BRU_MPRED),
|
2013-04-06 23:48:26 +08:00
|
|
|
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_FXU),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_DIV),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_SCALAR),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_SCALAR_LONG),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_VECTOR),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_VECTOR_LONG),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_LSU),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_REJECT),
|
|
|
|
|
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_ERAT_MISS),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_DCACHE_MISS),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_STORE),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_THRD),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_IFU),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_BRU),
|
|
|
|
|
POWER_EVENT_PTR(GCT_NOSLOT_IC_MISS),
|
|
|
|
|
POWER_EVENT_PTR(GCT_NOSLOT_BR_MPRED),
|
|
|
|
|
|
|
|
|
|
POWER_EVENT_PTR(GCT_NOSLOT_BR_MPRED_IC_MISS),
|
|
|
|
|
POWER_EVENT_PTR(GRP_CMPL),
|
|
|
|
|
POWER_EVENT_PTR(1PLUS_PPC_CMPL),
|
|
|
|
|
POWER_EVENT_PTR(CMPLU_STALL_DFU),
|
|
|
|
|
POWER_EVENT_PTR(RUN_CYC),
|
|
|
|
|
POWER_EVENT_PTR(RUN_INST_CMPL),
|
2013-01-23 14:24:54 +08:00
|
|
|
NULL
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static struct attribute_group power7_pmu_events_group = {
|
|
|
|
|
.name = "events",
|
|
|
|
|
.attrs = power7_events_attr,
|
|
|
|
|
};
|
|
|
|
|
|
2013-03-06 13:48:26 +08:00
|
|
|
PMU_FORMAT_ATTR(event, "config:0-19");
|
|
|
|
|
|
|
|
|
|
static struct attribute *power7_pmu_format_attr[] = {
|
|
|
|
|
&format_attr_event.attr,
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct attribute_group power7_pmu_format_group = {
|
|
|
|
|
.name = "format",
|
|
|
|
|
.attrs = power7_pmu_format_attr,
|
|
|
|
|
};
|
|
|
|
|
|
2013-01-23 14:24:54 +08:00
|
|
|
static const struct attribute_group *power7_pmu_attr_groups[] = {
|
2013-03-06 13:48:26 +08:00
|
|
|
&power7_pmu_format_group,
|
2013-01-23 14:24:54 +08:00
|
|
|
&power7_pmu_events_group,
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
2009-06-17 19:52:09 +08:00
|
|
|
static struct power_pmu power7_pmu = {
|
|
|
|
|
.name = "POWER7",
|
2009-06-17 19:51:13 +08:00
|
|
|
.n_counter = 6,
|
|
|
|
|
.max_alternatives = MAX_ALT + 1,
|
|
|
|
|
.add_fields = 0x1555ul,
|
|
|
|
|
.test_adder = 0x3000ul,
|
|
|
|
|
.compute_mmcr = power7_compute_mmcr,
|
|
|
|
|
.get_constraint = power7_get_constraint,
|
|
|
|
|
.get_alternatives = power7_get_alternatives,
|
|
|
|
|
.disable_pmc = power7_disable_pmc,
|
2009-07-01 11:07:01 +08:00
|
|
|
.flags = PPMU_ALT_SIPR,
|
2013-01-23 14:24:54 +08:00
|
|
|
.attr_groups = power7_pmu_attr_groups,
|
2009-06-17 19:51:13 +08:00
|
|
|
.n_generic = ARRAY_SIZE(power7_generic_events),
|
|
|
|
|
.generic_events = power7_generic_events,
|
|
|
|
|
.cache_events = &power7_cache_events,
|
2009-06-11 12:54:01 +08:00
|
|
|
};
|
2009-06-17 19:52:09 +08:00
|
|
|
|
2011-06-29 12:54:00 +08:00
|
|
|
static int __init init_power7_pmu(void)
|
2009-06-17 19:52:09 +08:00
|
|
|
{
|
2009-08-06 19:16:44 +08:00
|
|
|
if (!cur_cpu_spec->oprofile_cpu_type ||
|
|
|
|
|
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
|
2009-06-17 19:52:09 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
2012-09-19 04:56:11 +08:00
|
|
|
if (pvr_version_is(PVR_POWER7p))
|
|
|
|
|
power7_pmu.flags |= PPMU_SIAR_VALID;
|
|
|
|
|
|
2009-06-17 19:52:09 +08:00
|
|
|
return register_power_pmu(&power7_pmu);
|
|
|
|
|
}
|
|
|
|
|
|
2010-11-26 01:38:29 +08:00
|
|
|
early_initcall(init_power7_pmu);
|
