2020-07-03 16:49:42 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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/*
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* Each of the CPU clusters (Power and Perf) on msm8996 are
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* clocked via 2 PLLs, a primary and alternate. There are also
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* 2 Mux'es, a primary and secondary all connected together
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* as shown below
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*
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* +-------+
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* XO | |
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* +------------------>0 |
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2023-01-13 20:05:35 +08:00
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* SYS_APCS_AUX | |
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* +------------------>3 |
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2020-07-03 16:49:42 +08:00
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* | |
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* PLL/2 | SMUX +----+
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* +------->1 | |
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* | | | |
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* | +-------+ | +-------+
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* | +---->0 |
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* | | |
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* +---------------+ | +----------->1 | CPU clk
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* |Primary PLL +----+ PLL_EARLY | | +------>
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* | +------+-----------+ +------>2 PMUX |
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* +---------------+ | | | |
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* | +------+ | +-->3 |
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* +--^+ ACD +-----+ | +-------+
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* +---------------+ +------+ |
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* |Alt PLL | |
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* | +---------------------------+
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* +---------------+ PLL_EARLY
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*
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* The primary PLL is what drives the CPU clk, except for times
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* when we are reprogramming the PLL itself (for rate changes) when
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* we temporarily switch to an alternate PLL.
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*
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* The primary PLL operates on a single VCO range, between 600MHz
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* and 3GHz. However the CPUs do support OPPs with frequencies
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* between 300MHz and 600MHz. In order to support running the CPUs
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* at those frequencies we end up having to lock the PLL at twice
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* the rate and drive the CPU clk via the PLL/2 output and SMUX.
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*
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* So for frequencies above 600MHz we follow the following path
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* Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
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* and for frequencies between 300MHz and 600MHz we follow
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* Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
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*
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* ACD stands for Adaptive Clock Distribution and is used to
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* detect voltage droops.
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*/
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2022-07-14 18:03:51 +08:00
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#include <linux/bitfield.h>
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2020-07-03 16:49:42 +08:00
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <soc/qcom/kryo-l2-accessors.h>
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2023-01-24 04:18:10 +08:00
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#include <asm/cputype.h>
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2020-07-03 16:49:42 +08:00
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#include "clk-alpha-pll.h"
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#include "clk-regmap.h"
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2022-06-22 00:06:19 +08:00
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#include "clk-regmap-mux.h"
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2020-07-03 16:49:42 +08:00
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enum _pmux_input {
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2022-06-22 00:06:16 +08:00
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SMUX_INDEX = 0,
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2020-07-03 16:49:42 +08:00
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PLL_INDEX,
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ACD_INDEX,
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ALT_INDEX,
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NUM_OF_PMUX_INPUTS
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};
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#define DIV_2_THRESHOLD 600000000
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#define PWRCL_REG_OFFSET 0x0
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#define PERFCL_REG_OFFSET 0x80000
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#define MUX_OFFSET 0x40
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#define CLK_CTL_OFFSET 0x44
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#define CLK_CTL_AUTO_CLK_SEL BIT(8)
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#define ALT_PLL_OFFSET 0x100
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#define SSSCTL_OFFSET 0x160
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#define PSCTL_OFFSET 0x164
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2022-07-14 18:03:51 +08:00
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#define PMUX_MASK 0x3
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#define MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK GENMASK(5, 4)
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#define MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL \
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FIELD_PREP(MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, 0x03)
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2022-07-14 18:03:51 +08:00
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2020-07-03 16:49:42 +08:00
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static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_USER_CTL] = 0x10,
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[PLL_OFF_CONFIG_CTL] = 0x18,
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[PLL_OFF_CONFIG_CTL_U] = 0x1c,
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[PLL_OFF_TEST_CTL] = 0x20,
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[PLL_OFF_TEST_CTL_U] = 0x24,
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[PLL_OFF_STATUS] = 0x28,
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};
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static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_USER_CTL] = 0x10,
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[PLL_OFF_CONFIG_CTL] = 0x18,
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[PLL_OFF_TEST_CTL] = 0x20,
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[PLL_OFF_STATUS] = 0x28,
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};
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/* PLLs */
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static const struct alpha_pll_config hfpll_config = {
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2023-01-13 20:05:34 +08:00
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.l = 54,
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2023-01-13 20:05:33 +08:00
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.config_ctl_val = 0x200d4828,
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2020-07-03 16:49:42 +08:00
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.config_ctl_hi_val = 0x006,
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2023-01-13 20:05:33 +08:00
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.test_ctl_val = 0x1c000000,
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.test_ctl_hi_val = 0x00004000,
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2020-07-03 16:49:42 +08:00
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.pre_div_mask = BIT(12),
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.post_div_mask = 0x3 << 8,
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.post_div_val = 0x1 << 8,
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.main_output_mask = BIT(0),
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.early_output_mask = BIT(3),
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};
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2022-07-14 18:03:46 +08:00
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static const struct clk_parent_data pll_parent[] = {
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{ .fw_name = "xo" },
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};
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2022-06-22 00:06:18 +08:00
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static struct clk_alpha_pll pwrcl_pll = {
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.offset = PWRCL_REG_OFFSET,
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2020-07-03 16:49:42 +08:00
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.regs = prim_pll_regs,
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.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data){
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2022-06-22 00:06:18 +08:00
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.name = "pwrcl_pll",
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.parent_data = pll_parent,
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.num_parents = ARRAY_SIZE(pll_parent),
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2023-01-13 20:05:42 +08:00
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.ops = &clk_alpha_pll_hwfsm_ops,
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2020-07-03 16:49:42 +08:00
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},
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};
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2022-06-22 00:06:18 +08:00
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static struct clk_alpha_pll perfcl_pll = {
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.offset = PERFCL_REG_OFFSET,
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2020-07-03 16:49:42 +08:00
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.regs = prim_pll_regs,
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.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data){
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2022-06-22 00:06:18 +08:00
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.name = "perfcl_pll",
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2022-07-14 18:03:46 +08:00
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.parent_data = pll_parent,
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.num_parents = ARRAY_SIZE(pll_parent),
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.ops = &clk_alpha_pll_hwfsm_ops,
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2020-07-03 16:49:42 +08:00
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},
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};
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2022-06-22 00:06:17 +08:00
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static struct clk_fixed_factor pwrcl_pll_postdiv = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data){
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.name = "pwrcl_pll_postdiv",
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.parent_data = &(const struct clk_parent_data){
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.hw = &pwrcl_pll.clkr.hw
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},
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_fixed_factor perfcl_pll_postdiv = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data){
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.name = "perfcl_pll_postdiv",
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.parent_data = &(const struct clk_parent_data){
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.hw = &perfcl_pll.clkr.hw
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},
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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2022-07-14 18:03:48 +08:00
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static struct clk_fixed_factor perfcl_pll_acd = {
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.mult = 1,
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.div = 1,
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.hw.init = &(struct clk_init_data){
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.name = "perfcl_pll_acd",
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.parent_data = &(const struct clk_parent_data){
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.hw = &perfcl_pll.clkr.hw
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},
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_fixed_factor pwrcl_pll_acd = {
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.mult = 1,
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.div = 1,
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.hw.init = &(struct clk_init_data){
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.name = "pwrcl_pll_acd",
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.parent_data = &(const struct clk_parent_data){
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.hw = &pwrcl_pll.clkr.hw
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},
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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2020-07-03 16:49:42 +08:00
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static const struct pll_vco alt_pll_vco_modes[] = {
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VCO(3, 250000000, 500000000),
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VCO(2, 500000000, 750000000),
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VCO(1, 750000000, 1000000000),
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VCO(0, 1000000000, 2150400000),
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};
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static const struct alpha_pll_config altpll_config = {
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.l = 16,
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.vco_val = 0x3 << 20,
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.vco_mask = 0x3 << 20,
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.config_ctl_val = 0x4001051b,
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.post_div_mask = 0x3 << 8,
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.post_div_val = 0x1 << 8,
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.main_output_mask = BIT(0),
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.early_output_mask = BIT(3),
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};
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2022-06-22 00:06:18 +08:00
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static struct clk_alpha_pll pwrcl_alt_pll = {
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.offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET,
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2020-07-03 16:49:42 +08:00
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.regs = alt_pll_regs,
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.vco_table = alt_pll_vco_modes,
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.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
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.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data) {
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2022-06-22 00:06:18 +08:00
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.name = "pwrcl_alt_pll",
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2022-07-14 18:03:46 +08:00
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.parent_data = pll_parent,
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.num_parents = ARRAY_SIZE(pll_parent),
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2020-07-03 16:49:42 +08:00
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.ops = &clk_alpha_pll_hwfsm_ops,
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},
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};
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2022-06-22 00:06:18 +08:00
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static struct clk_alpha_pll perfcl_alt_pll = {
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.offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET,
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2020-07-03 16:49:42 +08:00
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.regs = alt_pll_regs,
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.vco_table = alt_pll_vco_modes,
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.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
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.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data) {
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2022-06-22 00:06:18 +08:00
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.name = "perfcl_alt_pll",
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2022-07-14 18:03:46 +08:00
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.parent_data = pll_parent,
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.num_parents = ARRAY_SIZE(pll_parent),
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2020-07-03 16:49:42 +08:00
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.ops = &clk_alpha_pll_hwfsm_ops,
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},
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};
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2022-06-22 00:06:19 +08:00
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struct clk_cpu_8996_pmux {
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2020-07-03 16:49:42 +08:00
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u32 reg;
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struct notifier_block nb;
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struct clk_regmap clkr;
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};
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static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
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void *data);
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2022-06-22 00:06:19 +08:00
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#define to_clk_cpu_8996_pmux_nb(_nb) \
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container_of(_nb, struct clk_cpu_8996_pmux, nb)
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2020-07-03 16:49:42 +08:00
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2022-06-22 00:06:19 +08:00
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static inline struct clk_cpu_8996_pmux *to_clk_cpu_8996_pmux_hw(struct clk_hw *hw)
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2020-07-03 16:49:42 +08:00
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{
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2022-06-22 00:06:19 +08:00
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return container_of(to_clk_regmap(hw), struct clk_cpu_8996_pmux, clkr);
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2020-07-03 16:49:42 +08:00
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}
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2022-06-22 00:06:19 +08:00
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static u8 clk_cpu_8996_pmux_get_parent(struct clk_hw *hw)
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2020-07-03 16:49:42 +08:00
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{
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struct clk_regmap *clkr = to_clk_regmap(hw);
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2022-06-22 00:06:19 +08:00
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struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw);
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2020-07-03 16:49:42 +08:00
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u32 val;
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regmap_read(clkr->regmap, cpuclk->reg, &val);
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2022-07-14 18:03:51 +08:00
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return FIELD_GET(PMUX_MASK, val);
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2020-07-03 16:49:42 +08:00
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}
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2022-06-22 00:06:19 +08:00
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static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index)
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2020-07-03 16:49:42 +08:00
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{
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struct clk_regmap *clkr = to_clk_regmap(hw);
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2022-06-22 00:06:19 +08:00
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struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw);
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2020-07-03 16:49:42 +08:00
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u32 val;
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2022-07-14 18:03:51 +08:00
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val = FIELD_PREP(PMUX_MASK, index);
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2020-07-03 16:49:42 +08:00
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2022-07-14 18:03:51 +08:00
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return regmap_update_bits(clkr->regmap, cpuclk->reg, PMUX_MASK, val);
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2020-07-03 16:49:42 +08:00
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}
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2022-06-22 00:06:19 +08:00
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static int clk_cpu_8996_pmux_determine_rate(struct clk_hw *hw,
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2020-07-03 16:49:42 +08:00
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|
|
struct clk_rate_request *req)
|
|
|
|
{
|
2022-07-14 18:03:50 +08:00
|
|
|
struct clk_hw *parent;
|
2020-07-03 16:49:42 +08:00
|
|
|
|
2022-07-14 18:03:50 +08:00
|
|
|
if (req->rate < (DIV_2_THRESHOLD / 2))
|
|
|
|
return -EINVAL;
|
2020-07-03 16:49:42 +08:00
|
|
|
|
2022-07-14 18:03:50 +08:00
|
|
|
if (req->rate < DIV_2_THRESHOLD)
|
|
|
|
parent = clk_hw_get_parent_by_index(hw, SMUX_INDEX);
|
|
|
|
else
|
|
|
|
parent = clk_hw_get_parent_by_index(hw, ACD_INDEX);
|
|
|
|
if (!parent)
|
|
|
|
return -EINVAL;
|
2020-07-03 16:49:42 +08:00
|
|
|
|
|
|
|
req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
|
|
|
|
req->best_parent_hw = parent;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-06-22 00:06:19 +08:00
|
|
|
static const struct clk_ops clk_cpu_8996_pmux_ops = {
|
|
|
|
.set_parent = clk_cpu_8996_pmux_set_parent,
|
|
|
|
.get_parent = clk_cpu_8996_pmux_get_parent,
|
|
|
|
.determine_rate = clk_cpu_8996_pmux_determine_rate,
|
2020-07-03 16:49:42 +08:00
|
|
|
};
|
|
|
|
|
2023-01-13 20:05:35 +08:00
|
|
|
static const struct parent_map smux_parent_map[] = {
|
|
|
|
{ .cfg = 0, }, /* xo */
|
|
|
|
{ .cfg = 1, }, /* pll */
|
|
|
|
{ .cfg = 3, }, /* sys_apcs_aux */
|
|
|
|
};
|
|
|
|
|
2022-07-14 18:03:46 +08:00
|
|
|
static const struct clk_parent_data pwrcl_smux_parents[] = {
|
|
|
|
{ .fw_name = "xo" },
|
|
|
|
{ .hw = &pwrcl_pll_postdiv.hw },
|
2023-01-13 20:05:35 +08:00
|
|
|
{ .fw_name = "sys_apcs_aux" },
|
2022-07-14 18:03:46 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clk_parent_data perfcl_smux_parents[] = {
|
|
|
|
{ .fw_name = "xo" },
|
|
|
|
{ .hw = &perfcl_pll_postdiv.hw },
|
2023-01-13 20:05:35 +08:00
|
|
|
{ .fw_name = "sys_apcs_aux" },
|
2022-07-14 18:03:46 +08:00
|
|
|
};
|
|
|
|
|
2022-06-22 00:06:19 +08:00
|
|
|
static struct clk_regmap_mux pwrcl_smux = {
|
2020-07-03 16:49:42 +08:00
|
|
|
.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
|
|
|
|
.shift = 2,
|
|
|
|
.width = 2,
|
2023-01-13 20:05:35 +08:00
|
|
|
.parent_map = smux_parent_map,
|
2020-07-03 16:49:42 +08:00
|
|
|
.clkr.hw.init = &(struct clk_init_data) {
|
|
|
|
.name = "pwrcl_smux",
|
2022-07-14 18:03:46 +08:00
|
|
|
.parent_data = pwrcl_smux_parents,
|
|
|
|
.num_parents = ARRAY_SIZE(pwrcl_smux_parents),
|
2022-06-22 00:06:19 +08:00
|
|
|
.ops = &clk_regmap_mux_closest_ops,
|
2020-07-03 16:49:42 +08:00
|
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2022-06-22 00:06:19 +08:00
|
|
|
static struct clk_regmap_mux perfcl_smux = {
|
2020-07-03 16:49:42 +08:00
|
|
|
.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
|
|
|
|
.shift = 2,
|
|
|
|
.width = 2,
|
2023-01-13 20:05:35 +08:00
|
|
|
.parent_map = smux_parent_map,
|
2020-07-03 16:49:42 +08:00
|
|
|
.clkr.hw.init = &(struct clk_init_data) {
|
|
|
|
.name = "perfcl_smux",
|
2022-07-14 18:03:46 +08:00
|
|
|
.parent_data = perfcl_smux_parents,
|
|
|
|
.num_parents = ARRAY_SIZE(perfcl_smux_parents),
|
2022-06-22 00:06:19 +08:00
|
|
|
.ops = &clk_regmap_mux_closest_ops,
|
2020-07-03 16:49:42 +08:00
|
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2022-07-14 18:03:46 +08:00
|
|
|
static const struct clk_hw *pwrcl_pmux_parents[] = {
|
|
|
|
[SMUX_INDEX] = &pwrcl_smux.clkr.hw,
|
|
|
|
[PLL_INDEX] = &pwrcl_pll.clkr.hw,
|
2022-07-14 18:03:48 +08:00
|
|
|
[ACD_INDEX] = &pwrcl_pll_acd.hw,
|
2022-07-14 18:03:46 +08:00
|
|
|
[ALT_INDEX] = &pwrcl_alt_pll.clkr.hw,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clk_hw *perfcl_pmux_parents[] = {
|
|
|
|
[SMUX_INDEX] = &perfcl_smux.clkr.hw,
|
|
|
|
[PLL_INDEX] = &perfcl_pll.clkr.hw,
|
2022-07-14 18:03:48 +08:00
|
|
|
[ACD_INDEX] = &perfcl_pll_acd.hw,
|
2022-07-14 18:03:46 +08:00
|
|
|
[ALT_INDEX] = &perfcl_alt_pll.clkr.hw,
|
|
|
|
};
|
|
|
|
|
2022-06-22 00:06:19 +08:00
|
|
|
static struct clk_cpu_8996_pmux pwrcl_pmux = {
|
2020-07-03 16:49:42 +08:00
|
|
|
.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
|
|
|
|
.nb.notifier_call = cpu_clk_notifier_cb,
|
|
|
|
.clkr.hw.init = &(struct clk_init_data) {
|
|
|
|
.name = "pwrcl_pmux",
|
2022-07-14 18:03:46 +08:00
|
|
|
.parent_hws = pwrcl_pmux_parents,
|
|
|
|
.num_parents = ARRAY_SIZE(pwrcl_pmux_parents),
|
2022-06-22 00:06:19 +08:00
|
|
|
.ops = &clk_cpu_8996_pmux_ops,
|
2020-07-03 16:49:42 +08:00
|
|
|
/* CPU clock is critical and should never be gated */
|
|
|
|
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2022-06-22 00:06:19 +08:00
|
|
|
static struct clk_cpu_8996_pmux perfcl_pmux = {
|
2020-07-03 16:49:42 +08:00
|
|
|
.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
|
|
|
|
.nb.notifier_call = cpu_clk_notifier_cb,
|
|
|
|
.clkr.hw.init = &(struct clk_init_data) {
|
|
|
|
.name = "perfcl_pmux",
|
2022-07-14 18:03:46 +08:00
|
|
|
.parent_hws = perfcl_pmux_parents,
|
|
|
|
.num_parents = ARRAY_SIZE(perfcl_pmux_parents),
|
2022-06-22 00:06:19 +08:00
|
|
|
.ops = &clk_cpu_8996_pmux_ops,
|
2020-07-03 16:49:42 +08:00
|
|
|
/* CPU clock is critical and should never be gated */
|
|
|
|
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct regmap_config cpu_msm8996_regmap_config = {
|
|
|
|
.reg_bits = 32,
|
|
|
|
.reg_stride = 4,
|
|
|
|
.val_bits = 32,
|
|
|
|
.max_register = 0x80210,
|
|
|
|
.fast_io = true,
|
|
|
|
.val_format_endian = REGMAP_ENDIAN_LITTLE,
|
|
|
|
};
|
|
|
|
|
2022-07-14 18:03:48 +08:00
|
|
|
static struct clk_hw *cpu_msm8996_hw_clks[] = {
|
|
|
|
&pwrcl_pll_postdiv.hw,
|
|
|
|
&perfcl_pll_postdiv.hw,
|
|
|
|
&pwrcl_pll_acd.hw,
|
|
|
|
&perfcl_pll_acd.hw,
|
|
|
|
};
|
|
|
|
|
2020-07-14 22:21:55 +08:00
|
|
|
static struct clk_regmap *cpu_msm8996_clks[] = {
|
2020-07-03 16:49:42 +08:00
|
|
|
&pwrcl_pll.clkr,
|
2022-06-22 00:06:18 +08:00
|
|
|
&perfcl_pll.clkr,
|
2020-07-03 16:49:42 +08:00
|
|
|
&pwrcl_alt_pll.clkr,
|
2022-06-22 00:06:18 +08:00
|
|
|
&perfcl_alt_pll.clkr,
|
2020-07-03 16:49:42 +08:00
|
|
|
&pwrcl_smux.clkr,
|
2022-06-22 00:06:18 +08:00
|
|
|
&perfcl_smux.clkr,
|
2020-07-03 16:49:42 +08:00
|
|
|
&pwrcl_pmux.clkr,
|
2022-06-22 00:06:18 +08:00
|
|
|
&perfcl_pmux.clkr,
|
2020-07-03 16:49:42 +08:00
|
|
|
};
|
|
|
|
|
2023-01-13 20:05:39 +08:00
|
|
|
static void qcom_cpu_clk_msm8996_acd_init(struct regmap *regmap);
|
|
|
|
|
2020-07-03 16:49:42 +08:00
|
|
|
static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
|
|
|
|
struct regmap *regmap)
|
|
|
|
{
|
|
|
|
int i, ret;
|
|
|
|
|
2023-01-13 20:05:40 +08:00
|
|
|
/* Select GPLL0 for 300MHz for both clusters */
|
|
|
|
regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0xc);
|
|
|
|
regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0xc);
|
|
|
|
|
|
|
|
/* Ensure write goes through before PLLs are reconfigured */
|
|
|
|
udelay(5);
|
|
|
|
|
2023-01-13 20:05:43 +08:00
|
|
|
/* Set the auto clock sel always-on source to GPLL0/2 (300MHz) */
|
|
|
|
regmap_update_bits(regmap, PWRCL_REG_OFFSET + MUX_OFFSET,
|
|
|
|
MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK,
|
|
|
|
MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL);
|
|
|
|
regmap_update_bits(regmap, PERFCL_REG_OFFSET + MUX_OFFSET,
|
|
|
|
MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK,
|
|
|
|
MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL);
|
|
|
|
|
2023-01-13 20:05:38 +08:00
|
|
|
clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
|
|
|
|
clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
|
|
|
|
clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
|
|
|
|
clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
|
|
|
|
|
2023-01-13 20:05:40 +08:00
|
|
|
/* Wait for PLL(s) to lock */
|
|
|
|
udelay(50);
|
|
|
|
|
2023-01-13 20:05:43 +08:00
|
|
|
/* Enable auto clock selection for both clusters */
|
|
|
|
regmap_update_bits(regmap, PWRCL_REG_OFFSET + CLK_CTL_OFFSET,
|
|
|
|
CLK_CTL_AUTO_CLK_SEL, CLK_CTL_AUTO_CLK_SEL);
|
|
|
|
regmap_update_bits(regmap, PERFCL_REG_OFFSET + CLK_CTL_OFFSET,
|
|
|
|
CLK_CTL_AUTO_CLK_SEL, CLK_CTL_AUTO_CLK_SEL);
|
|
|
|
|
|
|
|
/* Ensure write goes through before muxes are switched */
|
|
|
|
udelay(5);
|
|
|
|
|
2023-01-13 20:05:39 +08:00
|
|
|
qcom_cpu_clk_msm8996_acd_init(regmap);
|
|
|
|
|
2023-01-13 20:05:43 +08:00
|
|
|
/* Pulse swallower and soft-start settings */
|
|
|
|
regmap_write(regmap, PWRCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005);
|
|
|
|
regmap_write(regmap, PERFCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005);
|
|
|
|
|
2023-01-13 20:05:40 +08:00
|
|
|
/* Switch clusters to use the ACD leg */
|
2023-01-13 20:05:43 +08:00
|
|
|
regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x32);
|
|
|
|
regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x32);
|
2023-01-13 20:05:40 +08:00
|
|
|
|
2022-07-14 18:03:48 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) {
|
|
|
|
ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2020-07-03 16:49:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) {
|
|
|
|
ret = devm_clk_register_regmap(dev, cpu_msm8996_clks[i]);
|
2022-06-22 00:06:17 +08:00
|
|
|
if (ret)
|
2020-07-03 16:49:42 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable alt PLLs */
|
|
|
|
clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk);
|
|
|
|
clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk);
|
|
|
|
|
2022-07-14 18:03:47 +08:00
|
|
|
devm_clk_notifier_register(dev, pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
|
|
|
|
devm_clk_notifier_register(dev, perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
|
2020-07-03 16:49:42 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2023-01-13 20:05:41 +08:00
|
|
|
#define CPU_CLUSTER_AFFINITY_MASK 0xf00
|
|
|
|
#define PWRCL_AFFINITY_MASK 0x000
|
|
|
|
#define PERFCL_AFFINITY_MASK 0x100
|
2020-07-03 16:49:42 +08:00
|
|
|
|
|
|
|
#define L2ACDCR_REG 0x580ULL
|
|
|
|
#define L2ACDTD_REG 0x581ULL
|
|
|
|
#define L2ACDDVMRC_REG 0x584ULL
|
|
|
|
#define L2ACDSSCR_REG 0x589ULL
|
|
|
|
|
|
|
|
static DEFINE_SPINLOCK(qcom_clk_acd_lock);
|
|
|
|
|
2023-01-13 20:05:39 +08:00
|
|
|
static void qcom_cpu_clk_msm8996_acd_init(struct regmap *regmap)
|
2020-07-03 16:49:42 +08:00
|
|
|
{
|
|
|
|
u64 hwid;
|
2023-01-13 20:05:36 +08:00
|
|
|
u32 val;
|
2020-07-03 16:49:42 +08:00
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&qcom_clk_acd_lock, flags);
|
|
|
|
|
2023-01-13 20:05:36 +08:00
|
|
|
val = kryo_l2_get_indirect_reg(L2ACDTD_REG);
|
|
|
|
if (val == 0x00006a11)
|
|
|
|
goto out;
|
|
|
|
|
2020-07-03 16:49:42 +08:00
|
|
|
kryo_l2_set_indirect_reg(L2ACDTD_REG, 0x00006a11);
|
|
|
|
kryo_l2_set_indirect_reg(L2ACDDVMRC_REG, 0x000e0f0f);
|
|
|
|
kryo_l2_set_indirect_reg(L2ACDSSCR_REG, 0x00000601);
|
|
|
|
|
2023-01-13 20:05:41 +08:00
|
|
|
kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd);
|
2020-07-03 16:49:42 +08:00
|
|
|
|
2023-01-13 20:05:41 +08:00
|
|
|
hwid = read_cpuid_mpidr();
|
|
|
|
if ((hwid & CPU_CLUSTER_AFFINITY_MASK) == PWRCL_AFFINITY_MASK)
|
|
|
|
regmap_write(regmap, PWRCL_REG_OFFSET + SSSCTL_OFFSET, 0xf);
|
|
|
|
else
|
2023-01-13 20:05:39 +08:00
|
|
|
regmap_write(regmap, PERFCL_REG_OFFSET + SSSCTL_OFFSET, 0xf);
|
2020-07-03 16:49:42 +08:00
|
|
|
|
2023-01-13 20:05:36 +08:00
|
|
|
out:
|
2020-07-03 16:49:42 +08:00
|
|
|
spin_unlock_irqrestore(&qcom_clk_acd_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
|
|
|
|
void *data)
|
|
|
|
{
|
2022-06-22 00:06:19 +08:00
|
|
|
struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_nb(nb);
|
2020-07-03 16:49:42 +08:00
|
|
|
struct clk_notifier_data *cnd = data;
|
|
|
|
|
|
|
|
switch (event) {
|
|
|
|
case PRE_RATE_CHANGE:
|
2023-01-13 20:05:39 +08:00
|
|
|
qcom_cpu_clk_msm8996_acd_init(cpuclk->clkr.regmap);
|
2023-01-13 20:05:37 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Avoid overvolting. clk_core_set_rate_nolock() walks from top
|
|
|
|
* to bottom, so it will change the rate of the PLL before
|
|
|
|
* chaging the parent of PMUX. This can result in pmux getting
|
|
|
|
* clocked twice the expected rate.
|
|
|
|
*
|
|
|
|
* Manually switch to PLL/2 here.
|
|
|
|
*/
|
|
|
|
if (cnd->new_rate < DIV_2_THRESHOLD &&
|
|
|
|
cnd->old_rate > DIV_2_THRESHOLD)
|
|
|
|
clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, SMUX_INDEX);
|
|
|
|
|
2020-07-03 16:49:42 +08:00
|
|
|
break;
|
2023-01-13 20:05:37 +08:00
|
|
|
case ABORT_RATE_CHANGE:
|
|
|
|
/* Revert manual change */
|
|
|
|
if (cnd->new_rate < DIV_2_THRESHOLD &&
|
|
|
|
cnd->old_rate > DIV_2_THRESHOLD)
|
|
|
|
clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ACD_INDEX);
|
2020-07-03 16:49:42 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2023-01-13 20:05:37 +08:00
|
|
|
return NOTIFY_OK;
|
2020-07-03 16:49:42 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
|
|
|
|
{
|
2023-01-13 20:05:39 +08:00
|
|
|
static void __iomem *base;
|
2020-07-03 16:49:42 +08:00
|
|
|
struct regmap *regmap;
|
|
|
|
struct clk_hw_onecell_data *data;
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
data = devm_kzalloc(dev, struct_size(data, hws, 2), GFP_KERNEL);
|
|
|
|
if (!data)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
|
|
if (IS_ERR(base))
|
|
|
|
return PTR_ERR(base);
|
|
|
|
|
|
|
|
regmap = devm_regmap_init_mmio(dev, base, &cpu_msm8996_regmap_config);
|
|
|
|
if (IS_ERR(regmap))
|
|
|
|
return PTR_ERR(regmap);
|
|
|
|
|
|
|
|
ret = qcom_cpu_clk_msm8996_register_clks(dev, regmap);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
data->hws[0] = &pwrcl_pmux.clkr.hw;
|
|
|
|
data->hws[1] = &perfcl_pmux.clkr.hw;
|
|
|
|
data->num = 2;
|
|
|
|
|
|
|
|
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = {
|
|
|
|
{ .compatible = "qcom,msm8996-apcc" },
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, qcom_cpu_clk_msm8996_match_table);
|
|
|
|
|
|
|
|
static struct platform_driver qcom_cpu_clk_msm8996_driver = {
|
|
|
|
.probe = qcom_cpu_clk_msm8996_driver_probe,
|
|
|
|
.driver = {
|
|
|
|
.name = "qcom-msm8996-apcc",
|
|
|
|
.of_match_table = qcom_cpu_clk_msm8996_match_table,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(qcom_cpu_clk_msm8996_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|