2019-05-31 16:09:37 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2012-04-17 22:01:25 +08:00
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/*
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* Copyright 2010 Matt Turner.
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* Copyright 2012 Red Hat
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*
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* Authors: Matthew Garrett
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* Matt Turner
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* Dave Airlie
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*/
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#include <linux/delay.h>
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2019-12-03 18:04:00 +08:00
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#include <linux/pci.h>
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2012-04-17 22:01:25 +08:00
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2012-10-03 01:01:07 +08:00
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#include <drm/drm_crtc_helper.h>
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2019-06-23 18:35:42 +08:00
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#include <drm/drm_fourcc.h>
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2020-05-07 17:03:13 +08:00
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#include <drm/drm_gem_framebuffer_helper.h>
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2014-10-29 17:03:57 +08:00
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#include <drm/drm_plane_helper.h>
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2019-01-18 05:03:34 +08:00
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#include <drm/drm_probe_helper.h>
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2020-02-28 16:18:27 +08:00
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#include <drm/drm_simple_kms_helper.h>
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2012-04-17 22:01:25 +08:00
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#include "mgag200_drv.h"
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#define MGAG200_LUT_SIZE 256
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/*
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* This file contains setup code for the CRTC.
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*/
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static void mga_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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2020-05-07 17:03:10 +08:00
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struct mga_device *mdev = to_mga_device(dev);
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2014-04-02 06:22:40 +08:00
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struct drm_framebuffer *fb = crtc->primary->fb;
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2017-07-14 00:25:34 +08:00
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u16 *r_ptr, *g_ptr, *b_ptr;
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2012-04-17 22:01:25 +08:00
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int i;
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if (!crtc->enabled)
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return;
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2017-07-14 00:25:34 +08:00
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r_ptr = crtc->gamma_store;
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g_ptr = r_ptr + crtc->gamma_size;
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b_ptr = g_ptr + crtc->gamma_size;
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2012-04-17 22:01:25 +08:00
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WREG8(DAC_INDEX + MGA1064_INDEX, 0);
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2016-12-15 05:32:20 +08:00
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if (fb && fb->format->cpp[0] * 8 == 16) {
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2016-12-15 05:31:35 +08:00
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int inc = (fb->format->depth == 15) ? 8 : 4;
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2013-07-17 21:07:27 +08:00
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u8 r, b;
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for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
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2016-12-15 05:31:35 +08:00
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if (fb->format->depth == 16) {
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2013-07-17 21:07:27 +08:00
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if (i > (MGAG200_LUT_SIZE >> 1)) {
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r = b = 0;
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} else {
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2017-07-14 00:25:34 +08:00
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r = *r_ptr++ >> 8;
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b = *b_ptr++ >> 8;
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r_ptr++;
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b_ptr++;
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2013-07-17 21:07:27 +08:00
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}
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} else {
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2017-07-14 00:25:34 +08:00
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r = *r_ptr++ >> 8;
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b = *b_ptr++ >> 8;
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2013-07-17 21:07:27 +08:00
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}
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/* VGA registers */
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WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
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2017-07-14 00:25:34 +08:00
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WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
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2013-07-17 21:07:27 +08:00
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WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
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}
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return;
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}
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2012-04-17 22:01:25 +08:00
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for (i = 0; i < MGAG200_LUT_SIZE; i++) {
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/* VGA registers */
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2017-07-14 00:25:34 +08:00
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WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8);
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2012-04-17 22:01:25 +08:00
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}
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}
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static inline void mga_wait_vsync(struct mga_device *mdev)
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{
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2013-05-06 23:56:17 +08:00
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unsigned long timeout = jiffies + HZ/10;
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2012-04-17 22:01:25 +08:00
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unsigned int status = 0;
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do {
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status = RREG32(MGAREG_Status);
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2013-05-06 23:56:17 +08:00
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} while ((status & 0x08) && time_before(jiffies, timeout));
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timeout = jiffies + HZ/10;
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2012-04-17 22:01:25 +08:00
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status = 0;
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do {
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status = RREG32(MGAREG_Status);
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2013-05-06 23:56:17 +08:00
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} while (!(status & 0x08) && time_before(jiffies, timeout));
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2012-04-17 22:01:25 +08:00
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}
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static inline void mga_wait_busy(struct mga_device *mdev)
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{
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2013-05-06 23:56:17 +08:00
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unsigned long timeout = jiffies + HZ;
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2012-04-17 22:01:25 +08:00
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unsigned int status = 0;
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do {
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status = RREG8(MGAREG_Status + 2);
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2013-05-06 23:56:17 +08:00
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} while ((status & 0x01) && time_before(jiffies, timeout));
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2012-04-17 22:01:25 +08:00
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}
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2015-08-21 21:24:13 +08:00
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#define P_ARRAY_SIZE 9
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2012-04-17 22:01:25 +08:00
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static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
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{
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unsigned int vcomax, vcomin, pllreffreq;
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unsigned int delta, tmpdelta, permitteddelta;
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unsigned int testp, testm, testn;
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unsigned int p, m, n;
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unsigned int computed;
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2015-08-21 21:24:13 +08:00
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unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
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unsigned int fvv;
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unsigned int i;
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2012-04-17 22:01:25 +08:00
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2015-08-21 21:24:13 +08:00
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if (mdev->unique_rev_id <= 0x03) {
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2012-04-17 22:01:25 +08:00
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2015-08-21 21:24:13 +08:00
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m = n = p = 0;
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vcomax = 320000;
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vcomin = 160000;
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pllreffreq = 25000;
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2012-04-17 22:01:25 +08:00
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2015-08-21 21:24:13 +08:00
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delta = 0xffffffff;
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permitteddelta = clock * 5 / 1000;
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2012-04-17 22:01:25 +08:00
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2015-08-21 21:24:13 +08:00
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for (testp = 8; testp > 0; testp /= 2) {
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if (clock * testp > vcomax)
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continue;
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if (clock * testp < vcomin)
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continue;
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for (testn = 17; testn < 256; testn++) {
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for (testm = 1; testm < 32; testm++) {
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computed = (pllreffreq * testn) /
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(testm * testp);
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if (computed > clock)
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tmpdelta = computed - clock;
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else
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tmpdelta = clock - computed;
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if (tmpdelta < delta) {
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delta = tmpdelta;
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m = testm - 1;
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n = testn - 1;
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p = testp - 1;
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}
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}
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}
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}
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} else {
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m = n = p = 0;
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vcomax = 1600000;
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vcomin = 800000;
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pllreffreq = 25000;
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if (clock < 25000)
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clock = 25000;
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clock = clock * 2;
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delta = 0xFFFFFFFF;
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/* Permited delta is 0.5% as VESA Specification */
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permitteddelta = clock * 5 / 1000;
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for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
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testp = pvalues_e4[i];
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if ((clock * testp) > vcomax)
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continue;
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if ((clock * testp) < vcomin)
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continue;
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for (testn = 50; testn <= 256; testn++) {
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for (testm = 1; testm <= 32; testm++) {
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computed = (pllreffreq * testn) /
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(testm * testp);
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if (computed > clock)
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tmpdelta = computed - clock;
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else
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tmpdelta = clock - computed;
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if (tmpdelta < delta) {
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delta = tmpdelta;
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m = testm - 1;
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n = testn - 1;
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p = testp - 1;
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}
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2012-04-17 22:01:25 +08:00
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}
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}
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}
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2015-08-21 21:24:13 +08:00
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2016-05-28 03:12:50 +08:00
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fvv = pllreffreq * (n + 1) / (m + 1);
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2015-08-21 21:24:13 +08:00
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fvv = (fvv - 800000) / 50000;
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if (fvv > 15)
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fvv = 15;
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p |= (fvv << 4);
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m |= 0x80;
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clock = clock / 2;
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2012-04-17 22:01:25 +08:00
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}
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if (delta > permitteddelta) {
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2017-02-28 20:55:54 +08:00
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pr_warn("PLL delta too large\n");
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2012-04-17 22:01:25 +08:00
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return 1;
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}
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WREG_DAC(MGA1064_PIX_PLLC_M, m);
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WREG_DAC(MGA1064_PIX_PLLC_N, n);
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WREG_DAC(MGA1064_PIX_PLLC_P, p);
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2016-05-28 03:12:50 +08:00
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if (mdev->unique_rev_id >= 0x04) {
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WREG_DAC(0x1a, 0x09);
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msleep(20);
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WREG_DAC(0x1a, 0x01);
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}
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2012-04-17 22:01:25 +08:00
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return 0;
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}
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static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
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{
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unsigned int vcomax, vcomin, pllreffreq;
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2015-07-01 19:42:45 +08:00
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unsigned int delta, tmpdelta;
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2015-08-21 21:24:05 +08:00
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unsigned int testp, testm, testn, testp2;
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2012-04-17 22:01:25 +08:00
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unsigned int p, m, n;
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unsigned int computed;
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int i, j, tmpcount, vcount;
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bool pll_locked = false;
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u8 tmp;
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m = n = p = 0;
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delta = 0xffffffff;
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2015-08-21 21:24:05 +08:00
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if (mdev->type == G200_EW3) {
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vcomax = 800000;
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vcomin = 400000;
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pllreffreq = 25000;
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for (testp = 1; testp < 8; testp++) {
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for (testp2 = 1; testp2 < 8; testp2++) {
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if (testp < testp2)
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continue;
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if ((clock * testp * testp2) > vcomax)
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continue;
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if ((clock * testp * testp2) < vcomin)
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continue;
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for (testm = 1; testm < 26; testm++) {
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for (testn = 32; testn < 2048 ; testn++) {
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computed = (pllreffreq * testn) /
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(testm * testp * testp2);
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if (computed > clock)
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tmpdelta = computed - clock;
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else
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tmpdelta = clock - computed;
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if (tmpdelta < delta) {
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delta = tmpdelta;
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m = ((testn & 0x100) >> 1) |
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(testm);
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n = (testn & 0xFF);
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p = ((testn & 0x600) >> 3) |
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(testp2 << 3) |
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(testp);
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}
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}
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}
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}
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}
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} else {
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2012-04-17 22:01:25 +08:00
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2015-08-21 21:24:05 +08:00
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vcomax = 550000;
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vcomin = 150000;
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pllreffreq = 48000;
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for (testp = 1; testp < 9; testp++) {
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if (clock * testp > vcomax)
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continue;
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if (clock * testp < vcomin)
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continue;
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for (testm = 1; testm < 17; testm++) {
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for (testn = 1; testn < 151; testn++) {
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computed = (pllreffreq * testn) /
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(testm * testp);
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if (computed > clock)
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tmpdelta = computed - clock;
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else
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tmpdelta = clock - computed;
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if (tmpdelta < delta) {
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delta = tmpdelta;
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n = testn - 1;
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m = (testm - 1) |
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((n >> 1) & 0x80);
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p = testp - 1;
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}
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2012-04-17 22:01:25 +08:00
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}
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}
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}
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}
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for (i = 0; i <= 32 && pll_locked == false; i++) {
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if (i > 0) {
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WREG8(MGAREG_CRTC_INDEX, 0x1e);
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tmp = RREG8(MGAREG_CRTC_DATA);
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if (tmp < 0xff)
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WREG8(MGAREG_CRTC_DATA, tmp+1);
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}
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/* set pixclkdis to 1 */
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WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
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tmp = RREG8(DAC_DATA);
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tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
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2013-04-13 06:24:05 +08:00
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WREG8(DAC_DATA, tmp);
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2012-04-17 22:01:25 +08:00
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WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
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tmp = RREG8(DAC_DATA);
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tmp |= MGA1064_REMHEADCTL_CLKDIS;
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2013-04-13 06:24:05 +08:00
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WREG8(DAC_DATA, tmp);
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2012-04-17 22:01:25 +08:00
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/* select PLL Set C */
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tmp = RREG8(MGAREG_MEM_MISC_READ);
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tmp |= 0x3 << 2;
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WREG8(MGAREG_MEM_MISC_WRITE, tmp);
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WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
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tmp = RREG8(DAC_DATA);
|
|
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
udelay(500);
|
|
|
|
|
|
|
|
/* reset the PLL */
|
|
|
|
WREG8(DAC_INDEX, MGA1064_VREF_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~0x04;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
udelay(50);
|
|
|
|
|
|
|
|
/* program pixel pll register */
|
|
|
|
WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
|
|
|
|
WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
|
|
|
|
WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
|
|
|
|
|
|
|
|
udelay(50);
|
|
|
|
|
|
|
|
/* turn pll on */
|
|
|
|
WREG8(DAC_INDEX, MGA1064_VREF_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp |= 0x04;
|
|
|
|
WREG_DAC(MGA1064_VREF_CTL, tmp);
|
|
|
|
|
|
|
|
udelay(500);
|
|
|
|
|
|
|
|
/* select the pixel pll */
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
|
|
|
|
tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
|
|
|
|
tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
/* reset dotclock rate bit */
|
|
|
|
WREG8(MGAREG_SEQ_INDEX, 1);
|
|
|
|
tmp = RREG8(MGAREG_SEQ_DATA);
|
|
|
|
tmp &= ~0x8;
|
|
|
|
WREG8(MGAREG_SEQ_DATA, tmp);
|
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
vcount = RREG8(MGAREG_VCOUNT);
|
|
|
|
|
|
|
|
for (j = 0; j < 30 && pll_locked == false; j++) {
|
|
|
|
tmpcount = RREG8(MGAREG_VCOUNT);
|
|
|
|
if (tmpcount < vcount)
|
|
|
|
vcount = 0;
|
|
|
|
if ((tmpcount - vcount) > 2)
|
|
|
|
pll_locked = true;
|
|
|
|
else
|
|
|
|
udelay(5);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
|
|
|
|
WREG_DAC(MGA1064_REMHEADCTL, tmp);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
|
|
|
|
{
|
|
|
|
unsigned int vcomax, vcomin, pllreffreq;
|
2015-07-01 19:42:45 +08:00
|
|
|
unsigned int delta, tmpdelta;
|
2012-04-17 22:01:25 +08:00
|
|
|
unsigned int testp, testm, testn;
|
|
|
|
unsigned int p, m, n;
|
|
|
|
unsigned int computed;
|
|
|
|
u8 tmp;
|
|
|
|
|
|
|
|
m = n = p = 0;
|
|
|
|
vcomax = 550000;
|
|
|
|
vcomin = 150000;
|
|
|
|
pllreffreq = 50000;
|
|
|
|
|
|
|
|
delta = 0xffffffff;
|
|
|
|
|
|
|
|
for (testp = 16; testp > 0; testp--) {
|
|
|
|
if (clock * testp > vcomax)
|
|
|
|
continue;
|
|
|
|
if (clock * testp < vcomin)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
for (testn = 1; testn < 257; testn++) {
|
|
|
|
for (testm = 1; testm < 17; testm++) {
|
|
|
|
computed = (pllreffreq * testn) /
|
|
|
|
(testm * testp);
|
|
|
|
if (computed > clock)
|
|
|
|
tmpdelta = computed - clock;
|
|
|
|
else
|
|
|
|
tmpdelta = clock - computed;
|
|
|
|
if (tmpdelta < delta) {
|
|
|
|
delta = tmpdelta;
|
|
|
|
n = testn - 1;
|
|
|
|
m = testm - 1;
|
|
|
|
p = testp - 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
tmp = RREG8(MGAREG_MEM_MISC_READ);
|
|
|
|
tmp |= 0x3 << 2;
|
|
|
|
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
|
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp & ~0x40);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
|
|
|
|
WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
|
|
|
|
WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
|
|
|
|
|
|
|
|
udelay(50);
|
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
udelay(500);
|
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
|
|
|
|
tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp | 0x40);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
tmp = RREG8(MGAREG_MEM_MISC_READ);
|
|
|
|
tmp |= (0x3 << 2);
|
|
|
|
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
|
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
|
|
|
|
{
|
|
|
|
unsigned int vcomax, vcomin, pllreffreq;
|
2015-07-01 19:42:45 +08:00
|
|
|
unsigned int delta, tmpdelta;
|
2012-04-17 22:01:25 +08:00
|
|
|
unsigned int testp, testm, testn;
|
|
|
|
unsigned int p, m, n;
|
|
|
|
unsigned int computed;
|
|
|
|
int i, j, tmpcount, vcount;
|
|
|
|
u8 tmp;
|
|
|
|
bool pll_locked = false;
|
|
|
|
|
|
|
|
m = n = p = 0;
|
|
|
|
|
2016-10-22 00:47:07 +08:00
|
|
|
if (mdev->type == G200_EH3) {
|
|
|
|
vcomax = 3000000;
|
|
|
|
vcomin = 1500000;
|
|
|
|
pllreffreq = 25000;
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2016-10-22 00:47:07 +08:00
|
|
|
delta = 0xffffffff;
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2016-10-22 00:47:07 +08:00
|
|
|
testp = 0;
|
|
|
|
|
|
|
|
for (testm = 150; testm >= 6; testm--) {
|
|
|
|
if (clock * testm > vcomax)
|
|
|
|
continue;
|
|
|
|
if (clock * testm < vcomin)
|
|
|
|
continue;
|
|
|
|
for (testn = 120; testn >= 60; testn--) {
|
|
|
|
computed = (pllreffreq * testn) / testm;
|
2012-04-17 22:01:25 +08:00
|
|
|
if (computed > clock)
|
|
|
|
tmpdelta = computed - clock;
|
|
|
|
else
|
|
|
|
tmpdelta = clock - computed;
|
|
|
|
if (tmpdelta < delta) {
|
|
|
|
delta = tmpdelta;
|
2016-10-22 00:47:07 +08:00
|
|
|
n = testn;
|
|
|
|
m = testm;
|
|
|
|
p = testp;
|
|
|
|
}
|
|
|
|
if (delta == 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (delta == 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
|
|
|
|
vcomax = 800000;
|
|
|
|
vcomin = 400000;
|
|
|
|
pllreffreq = 33333;
|
|
|
|
|
|
|
|
delta = 0xffffffff;
|
|
|
|
|
|
|
|
for (testp = 16; testp > 0; testp >>= 1) {
|
|
|
|
if (clock * testp > vcomax)
|
|
|
|
continue;
|
|
|
|
if (clock * testp < vcomin)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
for (testm = 1; testm < 33; testm++) {
|
|
|
|
for (testn = 17; testn < 257; testn++) {
|
|
|
|
computed = (pllreffreq * testn) /
|
|
|
|
(testm * testp);
|
|
|
|
if (computed > clock)
|
|
|
|
tmpdelta = computed - clock;
|
|
|
|
else
|
|
|
|
tmpdelta = clock - computed;
|
|
|
|
if (tmpdelta < delta) {
|
|
|
|
delta = tmpdelta;
|
|
|
|
n = testn - 1;
|
|
|
|
m = (testm - 1);
|
|
|
|
p = testp - 1;
|
|
|
|
}
|
|
|
|
if ((clock * testp) >= 600000)
|
|
|
|
p |= 0x80;
|
2012-04-17 22:01:25 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
for (i = 0; i <= 32 && pll_locked == false; i++) {
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
tmp = RREG8(MGAREG_MEM_MISC_READ);
|
|
|
|
tmp |= 0x3 << 2;
|
|
|
|
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
|
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
udelay(500);
|
|
|
|
|
|
|
|
WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
|
|
|
|
WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
|
|
|
|
WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
|
|
|
|
|
|
|
|
udelay(500);
|
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
|
|
|
|
tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
|
|
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
vcount = RREG8(MGAREG_VCOUNT);
|
|
|
|
|
|
|
|
for (j = 0; j < 30 && pll_locked == false; j++) {
|
|
|
|
tmpcount = RREG8(MGAREG_VCOUNT);
|
|
|
|
if (tmpcount < vcount)
|
|
|
|
vcount = 0;
|
|
|
|
if ((tmpcount - vcount) > 2)
|
|
|
|
pll_locked = true;
|
|
|
|
else
|
|
|
|
udelay(5);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
|
|
|
|
{
|
|
|
|
unsigned int vcomax, vcomin, pllreffreq;
|
|
|
|
unsigned int delta, tmpdelta;
|
2012-08-09 13:00:15 +08:00
|
|
|
int testr, testn, testm, testo;
|
2012-04-17 22:01:25 +08:00
|
|
|
unsigned int p, m, n;
|
2012-08-09 13:00:15 +08:00
|
|
|
unsigned int computed, vco;
|
2012-04-17 22:01:25 +08:00
|
|
|
int tmp;
|
2012-08-09 13:00:15 +08:00
|
|
|
const unsigned int m_div_val[] = { 1, 2, 4, 8 };
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
m = n = p = 0;
|
|
|
|
vcomax = 1488000;
|
|
|
|
vcomin = 1056000;
|
|
|
|
pllreffreq = 48000;
|
|
|
|
|
|
|
|
delta = 0xffffffff;
|
|
|
|
|
|
|
|
for (testr = 0; testr < 4; testr++) {
|
|
|
|
if (delta == 0)
|
|
|
|
break;
|
|
|
|
for (testn = 5; testn < 129; testn++) {
|
|
|
|
if (delta == 0)
|
|
|
|
break;
|
|
|
|
for (testm = 3; testm >= 0; testm--) {
|
|
|
|
if (delta == 0)
|
|
|
|
break;
|
|
|
|
for (testo = 5; testo < 33; testo++) {
|
2012-08-09 13:00:15 +08:00
|
|
|
vco = pllreffreq * (testn + 1) /
|
2012-04-17 22:01:25 +08:00
|
|
|
(testr + 1);
|
2012-08-09 13:00:15 +08:00
|
|
|
if (vco < vcomin)
|
2012-04-17 22:01:25 +08:00
|
|
|
continue;
|
2012-08-09 13:00:15 +08:00
|
|
|
if (vco > vcomax)
|
2012-04-17 22:01:25 +08:00
|
|
|
continue;
|
2012-08-09 13:00:15 +08:00
|
|
|
computed = vco / (m_div_val[testm] * (testo + 1));
|
2012-04-17 22:01:25 +08:00
|
|
|
if (computed > clock)
|
|
|
|
tmpdelta = computed - clock;
|
|
|
|
else
|
|
|
|
tmpdelta = clock - computed;
|
|
|
|
if (tmpdelta < delta) {
|
|
|
|
delta = tmpdelta;
|
|
|
|
m = testm | (testo << 3);
|
|
|
|
n = testn;
|
|
|
|
p = testr | (testr << 3);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp |= MGA1064_REMHEADCTL_CLKDIS;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
tmp = RREG8(MGAREG_MEM_MISC_READ);
|
|
|
|
tmp |= (0x3<<2) | 0xc0;
|
|
|
|
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
|
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
|
|
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
|
2013-04-13 06:24:05 +08:00
|
|
|
WREG8(DAC_DATA, tmp);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
udelay(500);
|
|
|
|
|
|
|
|
WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
|
|
|
|
WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
|
|
|
|
WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
|
|
|
|
|
|
|
|
udelay(50);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
|
|
|
|
{
|
2020-05-15 16:32:23 +08:00
|
|
|
u8 misc;
|
|
|
|
|
2012-04-17 22:01:25 +08:00
|
|
|
switch(mdev->type) {
|
|
|
|
case G200_SE_A:
|
|
|
|
case G200_SE_B:
|
|
|
|
return mga_g200se_set_plls(mdev, clock);
|
|
|
|
break;
|
|
|
|
case G200_WB:
|
2015-08-21 21:24:05 +08:00
|
|
|
case G200_EW3:
|
2012-04-17 22:01:25 +08:00
|
|
|
return mga_g200wb_set_plls(mdev, clock);
|
|
|
|
break;
|
|
|
|
case G200_EV:
|
|
|
|
return mga_g200ev_set_plls(mdev, clock);
|
|
|
|
break;
|
|
|
|
case G200_EH:
|
2016-10-22 00:47:07 +08:00
|
|
|
case G200_EH3:
|
2012-04-17 22:01:25 +08:00
|
|
|
return mga_g200eh_set_plls(mdev, clock);
|
|
|
|
break;
|
|
|
|
case G200_ER:
|
|
|
|
return mga_g200er_set_plls(mdev, clock);
|
|
|
|
break;
|
|
|
|
}
|
2020-05-15 16:32:23 +08:00
|
|
|
|
|
|
|
misc = RREG8(MGA_MISC_IN);
|
|
|
|
misc &= ~MGAREG_MISC_CLK_SEL_MASK;
|
|
|
|
misc |= MGAREG_MISC_CLK_SEL_MGA_MSK;
|
|
|
|
WREG8(MGA_MISC_OUT, misc);
|
|
|
|
|
2012-04-17 22:01:25 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mga_g200wb_prepare(struct drm_crtc *crtc)
|
|
|
|
{
|
2020-05-07 17:03:10 +08:00
|
|
|
struct mga_device *mdev = to_mga_device(crtc->dev);
|
2012-04-17 22:01:25 +08:00
|
|
|
u8 tmp;
|
|
|
|
int iter_max;
|
|
|
|
|
|
|
|
/* 1- The first step is to warn the BMC of an upcoming mode change.
|
|
|
|
* We are putting the misc<0> to output.*/
|
|
|
|
|
|
|
|
WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp |= 0x10;
|
|
|
|
WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
|
|
|
|
|
|
|
|
/* we are putting a 1 on the misc<0> line */
|
|
|
|
WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp |= 0x10;
|
|
|
|
WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
|
|
|
|
|
|
|
|
/* 2- Second step to mask and further scan request
|
|
|
|
* This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
|
|
|
|
*/
|
|
|
|
WREG8(DAC_INDEX, MGA1064_SPAREREG);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp |= 0x80;
|
|
|
|
WREG_DAC(MGA1064_SPAREREG, tmp);
|
|
|
|
|
|
|
|
/* 3a- the third step is to verifu if there is an active scan
|
|
|
|
* We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
|
|
|
|
*/
|
|
|
|
iter_max = 300;
|
|
|
|
while (!(tmp & 0x1) && iter_max) {
|
|
|
|
WREG8(DAC_INDEX, MGA1064_SPAREREG);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
udelay(1000);
|
|
|
|
iter_max--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 3b- this step occurs only if the remove is actually scanning
|
|
|
|
* we are waiting for the end of the frame which is a 1 on
|
|
|
|
* remvsyncsts (XSPAREREG<1>)
|
|
|
|
*/
|
|
|
|
if (iter_max) {
|
|
|
|
iter_max = 300;
|
|
|
|
while ((tmp & 0x2) && iter_max) {
|
|
|
|
WREG8(DAC_INDEX, MGA1064_SPAREREG);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
udelay(1000);
|
|
|
|
iter_max--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mga_g200wb_commit(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
u8 tmp;
|
2020-05-07 17:03:10 +08:00
|
|
|
struct mga_device *mdev = to_mga_device(crtc->dev);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
/* 1- The first step is to ensure that the vrsten and hrsten are set */
|
|
|
|
WREG8(MGAREG_CRTCEXT_INDEX, 1);
|
|
|
|
tmp = RREG8(MGAREG_CRTCEXT_DATA);
|
|
|
|
WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
|
|
|
|
|
|
|
|
/* 2- second step is to assert the rstlvl2 */
|
|
|
|
WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp |= 0x8;
|
|
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
|
|
|
|
/* wait 10 us */
|
|
|
|
udelay(10);
|
|
|
|
|
|
|
|
/* 3- deassert rstlvl2 */
|
|
|
|
tmp &= ~0x08;
|
|
|
|
WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
|
|
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
|
|
|
|
/* 4- remove mask of scan request */
|
|
|
|
WREG8(DAC_INDEX, MGA1064_SPAREREG);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~0x80;
|
|
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
|
|
|
|
/* 5- put back a 0 on the misc<0> line */
|
|
|
|
WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
|
|
|
|
tmp = RREG8(DAC_DATA);
|
|
|
|
tmp &= ~0x10;
|
|
|
|
WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
|
|
|
|
}
|
|
|
|
|
2013-05-09 03:10:38 +08:00
|
|
|
/*
|
2020-05-15 16:32:20 +08:00
|
|
|
* This is how the framebuffer base address is stored in g200 cards:
|
|
|
|
* * Assume @offset is the gpu_addr variable of the framebuffer object
|
|
|
|
* * Then addr is the number of _pixels_ (not bytes) from the start of
|
|
|
|
* VRAM to the first pixel we want to display. (divided by 2 for 32bit
|
|
|
|
* framebuffers)
|
|
|
|
* * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
|
|
|
|
* addr<20> -> CRTCEXT0<6>
|
|
|
|
* addr<19-16> -> CRTCEXT0<3-0>
|
|
|
|
* addr<15-8> -> CRTCC<7-0>
|
|
|
|
* addr<7-0> -> CRTCD<7-0>
|
|
|
|
*
|
|
|
|
* CRTCEXT0 has to be programmed last to trigger an update and make the
|
|
|
|
* new addr variable take effect.
|
2013-05-09 03:10:38 +08:00
|
|
|
*/
|
2020-05-15 16:32:20 +08:00
|
|
|
static void mgag200_set_startadd(struct mga_device *mdev,
|
|
|
|
unsigned long offset)
|
2012-04-17 22:01:25 +08:00
|
|
|
{
|
2020-05-15 16:32:20 +08:00
|
|
|
struct drm_device *dev = mdev->dev;
|
|
|
|
u32 startadd;
|
|
|
|
u8 crtcc, crtcd, crtcext0;
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-15 16:32:20 +08:00
|
|
|
startadd = offset / 8;
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-15 16:32:20 +08:00
|
|
|
/*
|
|
|
|
* Can't store addresses any higher than that, but we also
|
|
|
|
* don't have more than 16 MiB of memory, so it should be fine.
|
|
|
|
*/
|
|
|
|
drm_WARN_ON(dev, startadd > 0x1fffff);
|
|
|
|
|
|
|
|
RREG_ECRT(0x00, crtcext0);
|
|
|
|
|
|
|
|
crtcc = (startadd >> 8) & 0xff;
|
|
|
|
crtcd = startadd & 0xff;
|
|
|
|
crtcext0 &= 0xb0;
|
|
|
|
crtcext0 |= ((startadd >> 14) & BIT(6)) |
|
|
|
|
((startadd >> 16) & 0x0f);
|
|
|
|
|
|
|
|
WREG_CRT(0x0c, crtcc);
|
|
|
|
WREG_CRT(0x0d, crtcd);
|
|
|
|
WREG_ECRT(0x00, crtcext0);
|
2012-04-17 22:01:25 +08:00
|
|
|
}
|
|
|
|
|
2020-05-15 16:32:21 +08:00
|
|
|
static int mga_crtc_do_set_base(struct mga_device *mdev,
|
|
|
|
const struct drm_framebuffer *fb,
|
|
|
|
const struct drm_framebuffer *old_fb)
|
2012-04-17 22:01:25 +08:00
|
|
|
{
|
2019-05-08 16:26:24 +08:00
|
|
|
struct drm_gem_vram_object *gbo;
|
2012-04-17 22:01:25 +08:00
|
|
|
int ret;
|
2019-05-08 16:26:24 +08:00
|
|
|
s64 gpu_addr;
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-15 16:32:21 +08:00
|
|
|
if (old_fb) {
|
|
|
|
gbo = drm_gem_vram_of_gem(old_fb->obj[0]);
|
2019-05-21 19:08:29 +08:00
|
|
|
drm_gem_vram_unpin(gbo);
|
2012-04-17 22:01:25 +08:00
|
|
|
}
|
|
|
|
|
2020-05-15 16:32:21 +08:00
|
|
|
gbo = drm_gem_vram_of_gem(fb->obj[0]);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2019-05-08 16:26:24 +08:00
|
|
|
ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM);
|
|
|
|
if (ret)
|
2019-05-17 00:27:46 +08:00
|
|
|
return ret;
|
2019-05-08 16:26:24 +08:00
|
|
|
gpu_addr = drm_gem_vram_offset(gbo);
|
|
|
|
if (gpu_addr < 0) {
|
|
|
|
ret = (int)gpu_addr;
|
|
|
|
goto err_drm_gem_vram_unpin;
|
2012-04-17 22:01:25 +08:00
|
|
|
}
|
|
|
|
|
2020-05-15 16:32:20 +08:00
|
|
|
mgag200_set_startadd(mdev, (unsigned long)gpu_addr);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
return 0;
|
2019-05-08 16:26:24 +08:00
|
|
|
|
|
|
|
err_drm_gem_vram_unpin:
|
|
|
|
drm_gem_vram_unpin(gbo);
|
|
|
|
return ret;
|
2012-04-17 22:01:25 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
|
|
|
|
struct drm_framebuffer *old_fb)
|
|
|
|
{
|
2020-05-15 16:32:20 +08:00
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
struct mga_device *mdev = dev->dev_private;
|
2020-05-15 16:32:21 +08:00
|
|
|
struct drm_framebuffer *fb = crtc->primary->fb;
|
2020-05-15 16:32:20 +08:00
|
|
|
unsigned int count;
|
|
|
|
|
|
|
|
do { } while (RREG8(0x1fda) & 0x08);
|
|
|
|
do { } while (!(RREG8(0x1fda) & 0x08));
|
|
|
|
|
|
|
|
count = RREG8(MGAREG_VCOUNT) + 2;
|
|
|
|
do { } while (RREG8(MGAREG_VCOUNT) < count);
|
|
|
|
|
2020-05-15 16:32:21 +08:00
|
|
|
return mga_crtc_do_set_base(mdev, fb, old_fb);
|
2012-04-17 22:01:25 +08:00
|
|
|
}
|
|
|
|
|
2020-05-15 16:32:22 +08:00
|
|
|
static void mgag200_set_mode_regs(struct mga_device *mdev,
|
|
|
|
const struct drm_display_mode *mode)
|
|
|
|
{
|
|
|
|
unsigned int hdisplay, hsyncstart, hsyncend, htotal;
|
|
|
|
unsigned int vdisplay, vsyncstart, vsyncend, vtotal;
|
2020-05-15 16:32:23 +08:00
|
|
|
u8 misc, crtcext1, crtcext2, crtcext5;
|
2020-05-15 16:32:22 +08:00
|
|
|
|
|
|
|
hdisplay = mode->hdisplay / 8 - 1;
|
|
|
|
hsyncstart = mode->hsync_start / 8 - 1;
|
|
|
|
hsyncend = mode->hsync_end / 8 - 1;
|
|
|
|
htotal = mode->htotal / 8 - 1;
|
|
|
|
|
|
|
|
/* Work around hardware quirk */
|
|
|
|
if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
|
|
|
|
htotal++;
|
|
|
|
|
|
|
|
vdisplay = mode->vdisplay - 1;
|
|
|
|
vsyncstart = mode->vsync_start - 1;
|
|
|
|
vsyncend = mode->vsync_end - 1;
|
|
|
|
vtotal = mode->vtotal - 2;
|
|
|
|
|
2020-05-15 16:32:23 +08:00
|
|
|
misc = RREG8(MGA_MISC_IN);
|
|
|
|
|
2020-05-15 16:32:22 +08:00
|
|
|
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
|
2020-05-15 16:32:23 +08:00
|
|
|
misc |= MGAREG_MISC_HSYNCPOL;
|
|
|
|
else
|
|
|
|
misc &= ~MGAREG_MISC_HSYNCPOL;
|
|
|
|
|
2020-05-15 16:32:22 +08:00
|
|
|
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
|
2020-05-15 16:32:23 +08:00
|
|
|
misc |= MGAREG_MISC_VSYNCPOL;
|
|
|
|
else
|
|
|
|
misc &= ~MGAREG_MISC_VSYNCPOL;
|
2020-05-15 16:32:22 +08:00
|
|
|
|
|
|
|
crtcext1 = (((htotal - 4) & 0x100) >> 8) |
|
|
|
|
((hdisplay & 0x100) >> 7) |
|
|
|
|
((hsyncstart & 0x100) >> 6) |
|
|
|
|
(htotal & 0x40);
|
|
|
|
if (mdev->type == G200_WB || mdev->type == G200_EW3)
|
|
|
|
crtcext1 |= BIT(7) | /* vrsten */
|
|
|
|
BIT(3); /* hrsten */
|
|
|
|
|
|
|
|
crtcext2 = ((vtotal & 0xc00) >> 10) |
|
|
|
|
((vdisplay & 0x400) >> 8) |
|
|
|
|
((vdisplay & 0xc00) >> 7) |
|
|
|
|
((vsyncstart & 0xc00) >> 5) |
|
|
|
|
((vdisplay & 0x400) >> 3);
|
|
|
|
crtcext5 = 0x00;
|
|
|
|
|
|
|
|
WREG_CRT(0, htotal - 4);
|
|
|
|
WREG_CRT(1, hdisplay);
|
|
|
|
WREG_CRT(2, hdisplay);
|
|
|
|
WREG_CRT(3, (htotal & 0x1F) | 0x80);
|
|
|
|
WREG_CRT(4, hsyncstart);
|
|
|
|
WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
|
|
|
|
WREG_CRT(6, vtotal & 0xFF);
|
|
|
|
WREG_CRT(7, ((vtotal & 0x100) >> 8) |
|
|
|
|
((vdisplay & 0x100) >> 7) |
|
|
|
|
((vsyncstart & 0x100) >> 6) |
|
|
|
|
((vdisplay & 0x100) >> 5) |
|
|
|
|
((vdisplay & 0x100) >> 4) | /* linecomp */
|
|
|
|
((vtotal & 0x200) >> 4) |
|
|
|
|
((vdisplay & 0x200) >> 3) |
|
|
|
|
((vsyncstart & 0x200) >> 2));
|
|
|
|
WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
|
|
|
|
((vdisplay & 0x200) >> 3));
|
|
|
|
WREG_CRT(16, vsyncstart & 0xFF);
|
|
|
|
WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
|
|
|
|
WREG_CRT(18, vdisplay & 0xFF);
|
|
|
|
WREG_CRT(20, 0);
|
|
|
|
WREG_CRT(21, vdisplay & 0xFF);
|
|
|
|
WREG_CRT(22, (vtotal + 1) & 0xFF);
|
|
|
|
WREG_CRT(23, 0xc3);
|
|
|
|
WREG_CRT(24, vdisplay & 0xFF);
|
|
|
|
|
|
|
|
WREG_ECRT(0x01, crtcext1);
|
|
|
|
WREG_ECRT(0x02, crtcext2);
|
|
|
|
WREG_ECRT(0x05, crtcext5);
|
2020-05-15 16:32:23 +08:00
|
|
|
|
|
|
|
WREG8(MGA_MISC_OUT, misc);
|
|
|
|
|
|
|
|
mga_crtc_set_plls(mdev, mode->clock);
|
2020-05-15 16:32:22 +08:00
|
|
|
}
|
|
|
|
|
2020-05-15 16:32:25 +08:00
|
|
|
static u8 mgag200_get_bpp_shift(struct mga_device *mdev,
|
|
|
|
const struct drm_format_info *format)
|
|
|
|
{
|
|
|
|
return mdev->bpp_shifts[format->cpp[0] - 1];
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Calculates the HW offset value from the framebuffer's pitch. The
|
|
|
|
* offset is a multiple of the pixel size and depends on the display
|
|
|
|
* format.
|
|
|
|
*/
|
|
|
|
static u32 mgag200_calculate_offset(struct mga_device *mdev,
|
|
|
|
const struct drm_framebuffer *fb)
|
|
|
|
{
|
|
|
|
u32 offset = fb->pitches[0] / fb->format->cpp[0];
|
|
|
|
u8 bppshift = mgag200_get_bpp_shift(mdev, fb->format);
|
|
|
|
|
|
|
|
if (fb->format->cpp[0] * 8 == 24)
|
|
|
|
offset = (offset * 3) >> (4 - bppshift);
|
|
|
|
else
|
|
|
|
offset = offset >> (4 - bppshift);
|
|
|
|
|
|
|
|
return offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mgag200_set_offset(struct mga_device *mdev,
|
|
|
|
const struct drm_framebuffer *fb)
|
|
|
|
{
|
|
|
|
u8 crtc13, crtcext0;
|
|
|
|
u32 offset = mgag200_calculate_offset(mdev, fb);
|
|
|
|
|
|
|
|
RREG_ECRT(0, crtcext0);
|
|
|
|
|
|
|
|
crtc13 = offset & 0xff;
|
|
|
|
|
|
|
|
crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK;
|
|
|
|
crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK;
|
|
|
|
|
|
|
|
WREG_CRT(0x13, crtc13);
|
|
|
|
WREG_ECRT(0x00, crtcext0);
|
|
|
|
}
|
|
|
|
|
2020-05-15 16:32:26 +08:00
|
|
|
static void mgag200_set_format_regs(struct mga_device *mdev,
|
|
|
|
const struct drm_framebuffer *fb)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = mdev->dev;
|
|
|
|
const struct drm_format_info *format = fb->format;
|
|
|
|
unsigned int bpp, bppshift, scale;
|
|
|
|
u8 crtcext3, xmulctrl;
|
|
|
|
|
|
|
|
bpp = format->cpp[0] * 8;
|
|
|
|
|
|
|
|
bppshift = mgag200_get_bpp_shift(mdev, format);
|
|
|
|
switch (bpp) {
|
|
|
|
case 24:
|
|
|
|
scale = ((1 << bppshift) * 3) - 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
scale = (1 << bppshift) - 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
RREG_ECRT(3, crtcext3);
|
|
|
|
|
|
|
|
switch (bpp) {
|
|
|
|
case 8:
|
|
|
|
xmulctrl = MGA1064_MUL_CTL_8bits;
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
if (format->depth == 15)
|
|
|
|
xmulctrl = MGA1064_MUL_CTL_15bits;
|
|
|
|
else
|
|
|
|
xmulctrl = MGA1064_MUL_CTL_16bits;
|
|
|
|
break;
|
|
|
|
case 24:
|
|
|
|
xmulctrl = MGA1064_MUL_CTL_24bits;
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
xmulctrl = MGA1064_MUL_CTL_32_24bits;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* BUG: We should have caught this problem already. */
|
|
|
|
drm_WARN_ON(dev, "invalid format depth\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
crtcext3 &= ~GENMASK(2, 0);
|
|
|
|
crtcext3 |= scale;
|
|
|
|
|
|
|
|
WREG_DAC(MGA1064_MUL_CTL, xmulctrl);
|
|
|
|
|
|
|
|
WREG_GFX(0, 0x00);
|
|
|
|
WREG_GFX(1, 0x00);
|
|
|
|
WREG_GFX(2, 0x00);
|
|
|
|
WREG_GFX(3, 0x00);
|
|
|
|
WREG_GFX(4, 0x00);
|
|
|
|
WREG_GFX(5, 0x40);
|
|
|
|
WREG_GFX(6, 0x05);
|
|
|
|
WREG_GFX(7, 0x0f);
|
|
|
|
WREG_GFX(8, 0x0f);
|
|
|
|
|
|
|
|
WREG_ECRT(3, crtcext3);
|
|
|
|
}
|
|
|
|
|
2020-05-15 16:32:27 +08:00
|
|
|
static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev)
|
|
|
|
{
|
|
|
|
static uint32_t RESET_FLAG = 0x00200000; /* undocumented magic value */
|
|
|
|
u8 seq1;
|
|
|
|
u32 memctl;
|
|
|
|
|
|
|
|
/* screen off */
|
|
|
|
RREG_SEQ(0x01, seq1);
|
|
|
|
seq1 |= MGAREG_SEQ1_SCROFF;
|
|
|
|
WREG_SEQ(0x01, seq1);
|
|
|
|
|
|
|
|
memctl = RREG32(MGAREG_MEMCTL);
|
|
|
|
|
|
|
|
memctl |= RESET_FLAG;
|
|
|
|
WREG32(MGAREG_MEMCTL, memctl);
|
|
|
|
|
|
|
|
udelay(1000);
|
|
|
|
|
|
|
|
memctl &= ~RESET_FLAG;
|
|
|
|
WREG32(MGAREG_MEMCTL, memctl);
|
|
|
|
|
|
|
|
/* screen on */
|
|
|
|
RREG_SEQ(0x01, seq1);
|
|
|
|
seq1 &= ~MGAREG_SEQ1_SCROFF;
|
|
|
|
WREG_SEQ(0x01, seq1);
|
|
|
|
}
|
|
|
|
|
2020-05-15 16:32:28 +08:00
|
|
|
static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev,
|
|
|
|
const struct drm_display_mode *mode,
|
|
|
|
const struct drm_framebuffer *fb)
|
|
|
|
{
|
|
|
|
unsigned int hiprilvl;
|
|
|
|
u8 crtcext6;
|
|
|
|
|
|
|
|
if (mdev->unique_rev_id >= 0x04) {
|
|
|
|
hiprilvl = 0;
|
|
|
|
} else if (mdev->unique_rev_id >= 0x02) {
|
|
|
|
unsigned int bpp;
|
|
|
|
unsigned long mb;
|
|
|
|
|
|
|
|
if (fb->format->cpp[0] * 8 > 16)
|
|
|
|
bpp = 32;
|
|
|
|
else if (fb->format->cpp[0] * 8 > 8)
|
|
|
|
bpp = 16;
|
|
|
|
else
|
|
|
|
bpp = 8;
|
|
|
|
|
|
|
|
mb = (mode->clock * bpp) / 1000;
|
|
|
|
if (mb > 3100)
|
|
|
|
hiprilvl = 0;
|
|
|
|
else if (mb > 2600)
|
|
|
|
hiprilvl = 1;
|
|
|
|
else if (mb > 1900)
|
|
|
|
hiprilvl = 2;
|
|
|
|
else if (mb > 1160)
|
|
|
|
hiprilvl = 3;
|
|
|
|
else if (mb > 440)
|
|
|
|
hiprilvl = 4;
|
|
|
|
else
|
|
|
|
hiprilvl = 5;
|
|
|
|
|
|
|
|
} else if (mdev->unique_rev_id >= 0x01) {
|
|
|
|
hiprilvl = 3;
|
|
|
|
} else {
|
|
|
|
hiprilvl = 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */
|
|
|
|
|
|
|
|
WREG_ECRT(0x06, crtcext6);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev)
|
|
|
|
{
|
|
|
|
WREG_ECRT(0x06, 0x00);
|
|
|
|
}
|
|
|
|
|
2012-04-17 22:01:25 +08:00
|
|
|
static int mga_crtc_mode_set(struct drm_crtc *crtc,
|
|
|
|
struct drm_display_mode *mode,
|
|
|
|
struct drm_display_mode *adjusted_mode,
|
|
|
|
int x, int y, struct drm_framebuffer *old_fb)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2020-05-07 17:03:10 +08:00
|
|
|
struct mga_device *mdev = to_mga_device(dev);
|
2016-11-19 03:52:40 +08:00
|
|
|
const struct drm_framebuffer *fb = crtc->primary->fb;
|
2012-04-17 22:01:25 +08:00
|
|
|
int option = 0, option2 = 0;
|
|
|
|
int i;
|
|
|
|
unsigned char misc = 0;
|
2020-05-15 16:32:26 +08:00
|
|
|
u8 crtcext3, crtcext4;
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
static unsigned char dacvalue[] = {
|
|
|
|
/* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
|
|
|
|
/* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
|
|
|
|
/* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
|
|
|
|
/* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
|
|
|
|
/* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
/* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
|
|
|
|
/* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
|
|
|
|
/* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
|
|
|
|
/* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
|
|
|
|
/* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
|
|
|
|
};
|
|
|
|
|
|
|
|
switch (mdev->type) {
|
|
|
|
case G200_SE_A:
|
|
|
|
case G200_SE_B:
|
|
|
|
dacvalue[MGA1064_VREF_CTL] = 0x03;
|
|
|
|
dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
|
|
|
|
dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
|
|
|
|
MGA1064_MISC_CTL_VGA8 |
|
|
|
|
MGA1064_MISC_CTL_DAC_RAM_CS;
|
|
|
|
if (mdev->has_sdram)
|
|
|
|
option = 0x40049120;
|
|
|
|
else
|
|
|
|
option = 0x4004d120;
|
|
|
|
option2 = 0x00008000;
|
|
|
|
break;
|
|
|
|
case G200_WB:
|
2015-08-21 21:24:05 +08:00
|
|
|
case G200_EW3:
|
2012-04-17 22:01:25 +08:00
|
|
|
dacvalue[MGA1064_VREF_CTL] = 0x07;
|
|
|
|
option = 0x41049120;
|
|
|
|
option2 = 0x0000b000;
|
|
|
|
break;
|
|
|
|
case G200_EV:
|
|
|
|
dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
|
|
|
|
dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
|
|
|
|
MGA1064_MISC_CTL_DAC_RAM_CS;
|
|
|
|
option = 0x00000120;
|
|
|
|
option2 = 0x0000b000;
|
|
|
|
break;
|
|
|
|
case G200_EH:
|
2016-10-22 00:47:07 +08:00
|
|
|
case G200_EH3:
|
2012-04-17 22:01:25 +08:00
|
|
|
dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
|
|
|
|
MGA1064_MISC_CTL_DAC_RAM_CS;
|
|
|
|
option = 0x00000120;
|
|
|
|
option2 = 0x0000b000;
|
|
|
|
break;
|
|
|
|
case G200_ER:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < sizeof(dacvalue); i++) {
|
2013-04-13 04:42:19 +08:00
|
|
|
if ((i <= 0x17) ||
|
2012-04-17 22:01:25 +08:00
|
|
|
(i == 0x1b) ||
|
|
|
|
(i == 0x1c) ||
|
|
|
|
((i >= 0x1f) && (i <= 0x29)) ||
|
|
|
|
((i >= 0x30) && (i <= 0x37)))
|
|
|
|
continue;
|
|
|
|
if (IS_G200_SE(mdev) &&
|
|
|
|
((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
|
|
|
|
continue;
|
2015-08-21 21:24:05 +08:00
|
|
|
if ((mdev->type == G200_EV ||
|
|
|
|
mdev->type == G200_WB ||
|
|
|
|
mdev->type == G200_EH ||
|
2016-10-22 00:47:07 +08:00
|
|
|
mdev->type == G200_EW3 ||
|
|
|
|
mdev->type == G200_EH3) &&
|
2012-04-17 22:01:25 +08:00
|
|
|
(i >= 0x44) && (i <= 0x4e))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
WREG_DAC(i, dacvalue[i]);
|
|
|
|
}
|
|
|
|
|
2013-04-05 22:51:15 +08:00
|
|
|
if (mdev->type == G200_ER)
|
|
|
|
WREG_DAC(0x90, 0);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
if (option)
|
|
|
|
pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
|
|
|
|
if (option2)
|
|
|
|
pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
|
|
|
|
|
|
|
|
WREG_SEQ(2, 0xf);
|
|
|
|
WREG_SEQ(3, 0);
|
|
|
|
WREG_SEQ(4, 0xe);
|
|
|
|
|
|
|
|
WREG_CRT(10, 0);
|
|
|
|
WREG_CRT(11, 0);
|
|
|
|
WREG_CRT(12, 0);
|
|
|
|
WREG_CRT(13, 0);
|
|
|
|
WREG_CRT(14, 0);
|
|
|
|
WREG_CRT(15, 0);
|
|
|
|
|
2020-05-15 16:32:26 +08:00
|
|
|
RREG_ECRT(0x03, crtcext3);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-15 16:32:26 +08:00
|
|
|
crtcext3 |= BIT(7); /* enable MGA mode */
|
|
|
|
crtcext4 = 0x00;
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-15 16:32:26 +08:00
|
|
|
WREG_ECRT(0x03, crtcext3);
|
|
|
|
WREG_ECRT(0x04, crtcext4);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
if (mdev->type == G200_ER)
|
2013-04-05 22:51:15 +08:00
|
|
|
WREG_ECRT(0x24, 0x5);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2015-08-21 21:24:05 +08:00
|
|
|
if (mdev->type == G200_EW3)
|
|
|
|
WREG_ECRT(0x34, 0x5);
|
|
|
|
|
2020-05-15 16:32:23 +08:00
|
|
|
misc = RREG8(MGA_MISC_IN);
|
|
|
|
misc |= MGAREG_MISC_IOADSEL |
|
|
|
|
MGAREG_MISC_RAMMAPEN |
|
|
|
|
MGAREG_MISC_HIGH_PG_SEL;
|
2012-04-17 22:01:25 +08:00
|
|
|
WREG8(MGA_MISC_OUT, misc);
|
|
|
|
|
2020-05-15 16:32:26 +08:00
|
|
|
mgag200_set_format_regs(mdev, fb);
|
2020-05-15 16:32:21 +08:00
|
|
|
mga_crtc_do_set_base(mdev, fb, old_fb);
|
2020-05-15 16:32:25 +08:00
|
|
|
mgag200_set_offset(mdev, fb);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-15 16:32:24 +08:00
|
|
|
mgag200_set_mode_regs(mdev, mode);
|
|
|
|
|
2020-05-15 16:32:27 +08:00
|
|
|
if (mdev->type == G200_ER)
|
|
|
|
mgag200_g200er_reset_tagfifo(mdev);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-15 16:32:28 +08:00
|
|
|
if (IS_G200_SE(mdev))
|
|
|
|
mgag200_g200se_set_hiprilvl(mdev, mode, fb);
|
|
|
|
else if (mdev->type == G200_EV)
|
|
|
|
mgag200_g200ev_set_hiprilvl(mdev);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
|
|
|
|
static int mga_suspend(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
struct mga_device *mdev = dev->dev_private;
|
|
|
|
struct pci_dev *pdev = dev->pdev;
|
|
|
|
int option;
|
|
|
|
|
|
|
|
if (mdev->suspended)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
WREG_SEQ(1, 0x20);
|
|
|
|
WREG_ECRT(1, 0x30);
|
|
|
|
/* Disable the pixel clock */
|
|
|
|
WREG_DAC(0x1a, 0x05);
|
|
|
|
/* Power down the DAC */
|
|
|
|
WREG_DAC(0x1e, 0x18);
|
|
|
|
/* Power down the pixel PLL */
|
|
|
|
WREG_DAC(0x1a, 0x0d);
|
|
|
|
|
|
|
|
/* Disable PLLs and clocks */
|
|
|
|
pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
|
|
|
|
option &= ~(0x1F8024);
|
|
|
|
pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
|
|
|
|
pci_set_power_state(pdev, PCI_D3hot);
|
|
|
|
pci_disable_device(pdev);
|
|
|
|
|
|
|
|
mdev->suspended = true;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mga_resume(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
struct mga_device *mdev = dev->dev_private;
|
|
|
|
struct pci_dev *pdev = dev->pdev;
|
|
|
|
int option;
|
|
|
|
|
|
|
|
if (!mdev->suspended)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
|
|
pci_enable_device(pdev);
|
|
|
|
|
|
|
|
/* Disable sysclk */
|
|
|
|
pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
|
|
|
|
option &= ~(0x4);
|
|
|
|
pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
|
|
|
|
|
|
|
|
mdev->suspended = false;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2020-05-07 17:03:10 +08:00
|
|
|
struct mga_device *mdev = to_mga_device(dev);
|
2012-04-17 22:01:25 +08:00
|
|
|
u8 seq1 = 0, crtcext1 = 0;
|
|
|
|
|
|
|
|
switch (mode) {
|
|
|
|
case DRM_MODE_DPMS_ON:
|
|
|
|
seq1 = 0;
|
|
|
|
crtcext1 = 0;
|
|
|
|
mga_crtc_load_lut(crtc);
|
|
|
|
break;
|
|
|
|
case DRM_MODE_DPMS_STANDBY:
|
|
|
|
seq1 = 0x20;
|
|
|
|
crtcext1 = 0x10;
|
|
|
|
break;
|
|
|
|
case DRM_MODE_DPMS_SUSPEND:
|
|
|
|
seq1 = 0x20;
|
|
|
|
crtcext1 = 0x20;
|
|
|
|
break;
|
|
|
|
case DRM_MODE_DPMS_OFF:
|
|
|
|
seq1 = 0x20;
|
|
|
|
crtcext1 = 0x30;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
if (mode == DRM_MODE_DPMS_OFF) {
|
|
|
|
mga_suspend(crtc);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
WREG8(MGAREG_SEQ_INDEX, 0x01);
|
|
|
|
seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
|
|
|
|
mga_wait_vsync(mdev);
|
|
|
|
mga_wait_busy(mdev);
|
|
|
|
WREG8(MGAREG_SEQ_DATA, seq1);
|
|
|
|
msleep(20);
|
|
|
|
WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
|
|
|
|
crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
|
|
|
|
WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
|
|
|
|
mga_resume(crtc);
|
|
|
|
drm_helper_resume_force_mode(dev);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This is called before a mode is programmed. A typical use might be to
|
|
|
|
* enable DPMS during the programming to avoid seeing intermediate stages,
|
|
|
|
* but that's not relevant to us
|
|
|
|
*/
|
|
|
|
static void mga_crtc_prepare(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2020-05-07 17:03:10 +08:00
|
|
|
struct mga_device *mdev = to_mga_device(dev);
|
2012-04-17 22:01:25 +08:00
|
|
|
u8 tmp;
|
|
|
|
|
|
|
|
/* mga_resume(crtc);*/
|
|
|
|
|
|
|
|
WREG8(MGAREG_CRTC_INDEX, 0x11);
|
|
|
|
tmp = RREG8(MGAREG_CRTC_DATA);
|
|
|
|
WREG_CRT(0x11, tmp | 0x80);
|
|
|
|
|
|
|
|
if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
|
|
|
|
WREG_SEQ(0, 1);
|
|
|
|
msleep(50);
|
|
|
|
WREG_SEQ(1, 0x20);
|
|
|
|
msleep(20);
|
|
|
|
} else {
|
|
|
|
WREG8(MGAREG_SEQ_INDEX, 0x1);
|
|
|
|
tmp = RREG8(MGAREG_SEQ_DATA);
|
|
|
|
|
|
|
|
/* start sync reset */
|
|
|
|
WREG_SEQ(0, 1);
|
|
|
|
WREG_SEQ(1, tmp | 0x20);
|
|
|
|
}
|
|
|
|
|
2015-08-21 21:24:05 +08:00
|
|
|
if (mdev->type == G200_WB || mdev->type == G200_EW3)
|
2012-04-17 22:01:25 +08:00
|
|
|
mga_g200wb_prepare(crtc);
|
|
|
|
|
|
|
|
WREG_CRT(17, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This is called after a mode is programmed. It should reverse anything done
|
|
|
|
* by the prepare function
|
|
|
|
*/
|
|
|
|
static void mga_crtc_commit(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2020-05-07 17:03:10 +08:00
|
|
|
struct mga_device *mdev = to_mga_device(dev);
|
2015-03-11 17:51:00 +08:00
|
|
|
const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
|
2012-04-17 22:01:25 +08:00
|
|
|
u8 tmp;
|
|
|
|
|
2015-08-21 21:24:05 +08:00
|
|
|
if (mdev->type == G200_WB || mdev->type == G200_EW3)
|
2012-04-17 22:01:25 +08:00
|
|
|
mga_g200wb_commit(crtc);
|
|
|
|
|
|
|
|
if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
|
|
|
|
msleep(50);
|
|
|
|
WREG_SEQ(1, 0x0);
|
|
|
|
msleep(20);
|
|
|
|
WREG_SEQ(0, 0x3);
|
|
|
|
} else {
|
|
|
|
WREG8(MGAREG_SEQ_INDEX, 0x1);
|
|
|
|
tmp = RREG8(MGAREG_SEQ_DATA);
|
|
|
|
|
|
|
|
tmp &= ~0x20;
|
|
|
|
WREG_SEQ(0x1, tmp);
|
|
|
|
WREG_SEQ(0, 3);
|
|
|
|
}
|
|
|
|
crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The core can pass us a set of gamma values to program. We actually only
|
|
|
|
* use this for 8-bit mode so can't perform smooth fades on deeper modes,
|
|
|
|
* but it's a requirement that we provide the function
|
|
|
|
*/
|
2016-06-07 18:49:30 +08:00
|
|
|
static int mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
|
2017-04-03 16:33:01 +08:00
|
|
|
u16 *blue, uint32_t size,
|
|
|
|
struct drm_modeset_acquire_ctx *ctx)
|
2012-04-17 22:01:25 +08:00
|
|
|
{
|
|
|
|
mga_crtc_load_lut(crtc);
|
2016-06-07 18:49:30 +08:00
|
|
|
|
|
|
|
return 0;
|
2012-04-17 22:01:25 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Simple cleanup function */
|
|
|
|
static void mga_crtc_destroy(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
|
|
|
|
|
|
|
|
drm_crtc_cleanup(crtc);
|
|
|
|
kfree(mga_crtc);
|
|
|
|
}
|
|
|
|
|
2013-07-17 21:07:22 +08:00
|
|
|
static void mga_crtc_disable(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
DRM_DEBUG_KMS("\n");
|
|
|
|
mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
|
2014-04-02 06:22:40 +08:00
|
|
|
if (crtc->primary->fb) {
|
2019-06-27 16:09:09 +08:00
|
|
|
struct drm_framebuffer *fb = crtc->primary->fb;
|
|
|
|
struct drm_gem_vram_object *gbo =
|
|
|
|
drm_gem_vram_of_gem(fb->obj[0]);
|
2019-05-21 19:08:29 +08:00
|
|
|
drm_gem_vram_unpin(gbo);
|
2013-07-17 21:07:22 +08:00
|
|
|
}
|
2014-04-02 06:22:40 +08:00
|
|
|
crtc->primary->fb = NULL;
|
2013-07-17 21:07:22 +08:00
|
|
|
}
|
|
|
|
|
2012-04-17 22:01:25 +08:00
|
|
|
/* These provide the minimum set of functions required to handle a CRTC */
|
|
|
|
static const struct drm_crtc_funcs mga_crtc_funcs = {
|
|
|
|
.gamma_set = mga_crtc_gamma_set,
|
|
|
|
.set_config = drm_crtc_helper_set_config,
|
|
|
|
.destroy = mga_crtc_destroy,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_crtc_helper_funcs mga_helper_funcs = {
|
2013-07-17 21:07:22 +08:00
|
|
|
.disable = mga_crtc_disable,
|
2012-04-17 22:01:25 +08:00
|
|
|
.dpms = mga_crtc_dpms,
|
|
|
|
.mode_set = mga_crtc_mode_set,
|
|
|
|
.mode_set_base = mga_crtc_mode_set_base,
|
|
|
|
.prepare = mga_crtc_prepare,
|
|
|
|
.commit = mga_crtc_commit,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* CRTC setup */
|
2013-02-20 22:34:22 +08:00
|
|
|
static void mga_crtc_init(struct mga_device *mdev)
|
2012-04-17 22:01:25 +08:00
|
|
|
{
|
2020-05-07 17:03:11 +08:00
|
|
|
struct drm_device *dev = mdev->dev;
|
2012-04-17 22:01:25 +08:00
|
|
|
struct mga_crtc *mga_crtc;
|
|
|
|
|
|
|
|
mga_crtc = kzalloc(sizeof(struct mga_crtc) +
|
|
|
|
(MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
|
|
|
if (mga_crtc == NULL)
|
|
|
|
return;
|
|
|
|
|
2020-05-07 17:03:11 +08:00
|
|
|
drm_crtc_init(dev, &mga_crtc->base, &mga_crtc_funcs);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
|
|
|
|
|
|
|
|
drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
|
|
|
|
}
|
|
|
|
|
2020-05-07 17:03:15 +08:00
|
|
|
/*
|
|
|
|
* Connector
|
|
|
|
*/
|
|
|
|
|
2012-04-17 22:01:25 +08:00
|
|
|
static int mga_vga_get_modes(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct mga_connector *mga_connector = to_mga_connector(connector);
|
|
|
|
struct edid *edid;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
|
|
|
|
if (edid) {
|
2018-07-09 16:40:06 +08:00
|
|
|
drm_connector_update_edid_property(connector, edid);
|
2012-04-17 22:01:25 +08:00
|
|
|
ret = drm_add_edid_modes(connector, edid);
|
|
|
|
kfree(edid);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-06-28 01:38:59 +08:00
|
|
|
static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
|
|
|
|
int bits_per_pixel)
|
|
|
|
{
|
|
|
|
uint32_t total_area, divisor;
|
2015-11-04 12:09:58 +08:00
|
|
|
uint64_t active_area, pixels_per_second, bandwidth;
|
2013-06-28 01:38:59 +08:00
|
|
|
uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
|
|
|
|
|
|
|
|
divisor = 1024;
|
|
|
|
|
|
|
|
if (!mode->htotal || !mode->vtotal || !mode->clock)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
active_area = mode->hdisplay * mode->vdisplay;
|
|
|
|
total_area = mode->htotal * mode->vtotal;
|
|
|
|
|
|
|
|
pixels_per_second = active_area * mode->clock * 1000;
|
|
|
|
do_div(pixels_per_second, total_area);
|
|
|
|
|
|
|
|
bandwidth = pixels_per_second * bytes_per_pixel * 100;
|
|
|
|
do_div(bandwidth, divisor);
|
|
|
|
|
|
|
|
return (uint32_t)(bandwidth);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MODE_BANDWIDTH MODE_BAD
|
|
|
|
|
2018-04-24 21:15:06 +08:00
|
|
|
static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector,
|
2012-04-17 22:01:25 +08:00
|
|
|
struct drm_display_mode *mode)
|
|
|
|
{
|
2013-02-26 23:55:44 +08:00
|
|
|
struct drm_device *dev = connector->dev;
|
2020-05-07 17:03:10 +08:00
|
|
|
struct mga_device *mdev = to_mga_device(dev);
|
2013-02-26 23:55:44 +08:00
|
|
|
int bpp = 32;
|
|
|
|
|
2013-06-28 01:38:59 +08:00
|
|
|
if (IS_G200_SE(mdev)) {
|
|
|
|
if (mdev->unique_rev_id == 0x01) {
|
|
|
|
if (mode->hdisplay > 1600)
|
|
|
|
return MODE_VIRTUAL_X;
|
|
|
|
if (mode->vdisplay > 1200)
|
|
|
|
return MODE_VIRTUAL_Y;
|
|
|
|
if (mga_vga_calculate_mode_bandwidth(mode, bpp)
|
|
|
|
> (24400 * 1024))
|
|
|
|
return MODE_BANDWIDTH;
|
2015-08-21 21:24:13 +08:00
|
|
|
} else if (mdev->unique_rev_id == 0x02) {
|
2013-06-28 01:38:59 +08:00
|
|
|
if (mode->hdisplay > 1920)
|
|
|
|
return MODE_VIRTUAL_X;
|
|
|
|
if (mode->vdisplay > 1200)
|
|
|
|
return MODE_VIRTUAL_Y;
|
|
|
|
if (mga_vga_calculate_mode_bandwidth(mode, bpp)
|
|
|
|
> (30100 * 1024))
|
|
|
|
return MODE_BANDWIDTH;
|
2017-06-14 22:39:42 +08:00
|
|
|
} else {
|
|
|
|
if (mga_vga_calculate_mode_bandwidth(mode, bpp)
|
|
|
|
> (55000 * 1024))
|
|
|
|
return MODE_BANDWIDTH;
|
2013-06-28 01:38:59 +08:00
|
|
|
}
|
|
|
|
} else if (mdev->type == G200_WB) {
|
|
|
|
if (mode->hdisplay > 1280)
|
|
|
|
return MODE_VIRTUAL_X;
|
|
|
|
if (mode->vdisplay > 1024)
|
|
|
|
return MODE_VIRTUAL_Y;
|
2018-01-25 22:26:55 +08:00
|
|
|
if (mga_vga_calculate_mode_bandwidth(mode, bpp) >
|
|
|
|
(31877 * 1024))
|
2013-06-28 01:38:59 +08:00
|
|
|
return MODE_BANDWIDTH;
|
|
|
|
} else if (mdev->type == G200_EV &&
|
|
|
|
(mga_vga_calculate_mode_bandwidth(mode, bpp)
|
|
|
|
> (32700 * 1024))) {
|
|
|
|
return MODE_BANDWIDTH;
|
2014-02-05 12:13:56 +08:00
|
|
|
} else if (mdev->type == G200_EH &&
|
2013-06-28 01:38:59 +08:00
|
|
|
(mga_vga_calculate_mode_bandwidth(mode, bpp)
|
|
|
|
> (37500 * 1024))) {
|
|
|
|
return MODE_BANDWIDTH;
|
2014-02-05 12:13:56 +08:00
|
|
|
} else if (mdev->type == G200_ER &&
|
2013-06-28 01:38:59 +08:00
|
|
|
(mga_vga_calculate_mode_bandwidth(mode,
|
|
|
|
bpp) > (55000 * 1024))) {
|
|
|
|
return MODE_BANDWIDTH;
|
|
|
|
}
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2015-06-16 04:16:15 +08:00
|
|
|
if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
|
|
|
|
(mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
|
|
|
|
return MODE_H_ILLEGAL;
|
|
|
|
}
|
|
|
|
|
2012-04-17 22:01:25 +08:00
|
|
|
if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
|
|
|
|
mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
|
|
|
|
mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
|
|
|
|
mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
|
|
|
|
return MODE_BAD;
|
|
|
|
}
|
|
|
|
|
2013-02-26 23:55:44 +08:00
|
|
|
/* Validate the mode input by the user */
|
2014-08-06 16:08:32 +08:00
|
|
|
if (connector->cmdline_mode.specified) {
|
|
|
|
if (connector->cmdline_mode.bpp_specified)
|
|
|
|
bpp = connector->cmdline_mode.bpp;
|
2013-02-26 23:55:44 +08:00
|
|
|
}
|
|
|
|
|
2019-09-27 17:13:00 +08:00
|
|
|
if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->vram_fb_available) {
|
2014-08-06 16:08:32 +08:00
|
|
|
if (connector->cmdline_mode.specified)
|
|
|
|
connector->cmdline_mode.specified = false;
|
2013-02-26 23:55:44 +08:00
|
|
|
return MODE_BAD;
|
|
|
|
}
|
|
|
|
|
2012-04-17 22:01:25 +08:00
|
|
|
return MODE_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mga_connector_destroy(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct mga_connector *mga_connector = to_mga_connector(connector);
|
|
|
|
mgag200_i2c_destroy(mga_connector->i2c);
|
|
|
|
drm_connector_cleanup(connector);
|
|
|
|
}
|
|
|
|
|
2015-12-15 19:21:10 +08:00
|
|
|
static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
|
2012-04-17 22:01:25 +08:00
|
|
|
.get_modes = mga_vga_get_modes,
|
|
|
|
.mode_valid = mga_vga_mode_valid,
|
|
|
|
};
|
|
|
|
|
2015-12-15 19:21:10 +08:00
|
|
|
static const struct drm_connector_funcs mga_vga_connector_funcs = {
|
2012-04-17 22:01:25 +08:00
|
|
|
.dpms = drm_helper_connector_dpms,
|
|
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
|
|
|
.destroy = mga_connector_destroy,
|
|
|
|
};
|
|
|
|
|
2020-05-07 17:03:15 +08:00
|
|
|
static int mgag200_vga_connector_init(struct mga_device *mdev)
|
2012-04-17 22:01:25 +08:00
|
|
|
{
|
2020-05-07 17:03:15 +08:00
|
|
|
struct drm_device *dev = mdev->dev;
|
|
|
|
struct mga_connector *mconnector = &mdev->connector;
|
|
|
|
struct drm_connector *connector = &mconnector->base;
|
|
|
|
struct mga_i2c_chan *i2c;
|
|
|
|
int ret;
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-07 17:03:15 +08:00
|
|
|
i2c = mgag200_i2c_create(dev);
|
|
|
|
if (!i2c)
|
|
|
|
drm_warn(dev, "failed to add DDC bus\n");
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-07 17:03:15 +08:00
|
|
|
ret = drm_connector_init_with_ddc(dev, connector,
|
|
|
|
&mga_vga_connector_funcs,
|
|
|
|
DRM_MODE_CONNECTOR_VGA,
|
|
|
|
&i2c->adapter);
|
|
|
|
if (ret)
|
|
|
|
goto err_mgag200_i2c_destroy;
|
2012-04-17 22:01:25 +08:00
|
|
|
drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
|
|
|
|
|
2020-05-07 17:03:15 +08:00
|
|
|
mconnector->i2c = i2c;
|
2013-07-17 21:07:25 +08:00
|
|
|
|
2020-05-07 17:03:15 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_mgag200_i2c_destroy:
|
|
|
|
mgag200_i2c_destroy(i2c);
|
|
|
|
return ret;
|
2012-04-17 22:01:25 +08:00
|
|
|
}
|
|
|
|
|
2020-05-07 17:03:13 +08:00
|
|
|
static const struct drm_mode_config_funcs mgag200_mode_config_funcs = {
|
|
|
|
.fb_create = drm_gem_fb_create
|
|
|
|
};
|
|
|
|
|
|
|
|
static unsigned int mgag200_preferred_depth(struct mga_device *mdev)
|
|
|
|
{
|
|
|
|
if (IS_G200_SE(mdev) && mdev->vram_fb_available < (2048*1024))
|
|
|
|
return 16;
|
|
|
|
else
|
|
|
|
return 32;
|
|
|
|
}
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
int mgag200_modeset_init(struct mga_device *mdev)
|
|
|
|
{
|
2020-05-07 17:03:11 +08:00
|
|
|
struct drm_device *dev = mdev->dev;
|
2020-02-28 16:18:27 +08:00
|
|
|
struct drm_encoder *encoder = &mdev->encoder;
|
2020-05-07 17:03:15 +08:00
|
|
|
struct drm_connector *connector = &mdev->connector.base;
|
2020-02-28 16:18:27 +08:00
|
|
|
int ret;
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-07 17:03:13 +08:00
|
|
|
mdev->bpp_shifts[0] = 0;
|
|
|
|
mdev->bpp_shifts[1] = 1;
|
|
|
|
mdev->bpp_shifts[2] = 0;
|
|
|
|
mdev->bpp_shifts[3] = 2;
|
|
|
|
|
|
|
|
ret = drmm_mode_config_init(dev);
|
|
|
|
if (ret) {
|
|
|
|
drm_err(dev, "drmm_mode_config_init() failed, error %d\n",
|
|
|
|
ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-05-07 17:03:11 +08:00
|
|
|
dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
|
|
|
|
dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-07 17:03:13 +08:00
|
|
|
dev->mode_config.preferred_depth = mgag200_preferred_depth(mdev);
|
|
|
|
dev->mode_config.prefer_shadow = 1;
|
|
|
|
|
2020-05-07 17:03:11 +08:00
|
|
|
dev->mode_config.fb_base = mdev->mc.vram_base;
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-07 17:03:13 +08:00
|
|
|
dev->mode_config.funcs = &mgag200_mode_config_funcs;
|
|
|
|
|
2013-02-20 22:34:22 +08:00
|
|
|
mga_crtc_init(mdev);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-07 17:03:11 +08:00
|
|
|
ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
|
2020-02-28 16:18:27 +08:00
|
|
|
if (ret) {
|
2020-05-07 17:03:11 +08:00
|
|
|
drm_err(dev,
|
2020-02-28 16:18:27 +08:00
|
|
|
"drm_simple_encoder_init() failed, error %d\n",
|
|
|
|
ret);
|
|
|
|
return ret;
|
2012-04-17 22:01:25 +08:00
|
|
|
}
|
2020-02-28 16:18:27 +08:00
|
|
|
encoder->possible_crtcs = 0x1;
|
2012-04-17 22:01:25 +08:00
|
|
|
|
2020-05-07 17:03:15 +08:00
|
|
|
ret = mgag200_vga_connector_init(mdev);
|
|
|
|
if (ret) {
|
|
|
|
drm_err(dev,
|
|
|
|
"mgag200_vga_connector_init() failed, error %d\n",
|
|
|
|
ret);
|
|
|
|
return ret;
|
2012-04-17 22:01:25 +08:00
|
|
|
}
|
|
|
|
|
2018-07-09 16:40:07 +08:00
|
|
|
drm_connector_attach_encoder(connector, encoder);
|
2012-04-17 22:01:25 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|