2023-03-20 19:22:45 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Common definitions for Cirrus Logic CS35L56 smart amp
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*
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* Copyright (C) 2023 Cirrus Logic, Inc. and
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* Cirrus Logic International Semiconductor Ltd.
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*/
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#ifndef __CS35L56_H
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#define __CS35L56_H
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#include <linux/firmware/cirrus/cs_dsp.h>
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#include <linux/regulator/consumer.h>
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#include <linux/regmap.h>
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2024-02-23 23:39:07 +08:00
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#include <sound/cs-amp-lib.h>
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2023-03-20 19:22:45 +08:00
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#define CS35L56_DEVID 0x0000000
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#define CS35L56_REVID 0x0000004
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#define CS35L56_RELID 0x000000C
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#define CS35L56_OTPID 0x0000010
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#define CS35L56_SFT_RESET 0x0000020
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#define CS35L56_GLOBAL_ENABLES 0x0002014
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#define CS35L56_BLOCK_ENABLES 0x0002018
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#define CS35L56_BLOCK_ENABLES2 0x000201C
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#define CS35L56_REFCLK_INPUT 0x0002C04
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#define CS35L56_GLOBAL_SAMPLE_RATE 0x0002C0C
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#define CS35L56_OTP_MEM_53 0x00300D4
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#define CS35L56_OTP_MEM_54 0x00300D8
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#define CS35L56_OTP_MEM_55 0x00300DC
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#define CS35L56_ASP1_ENABLES1 0x0004800
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#define CS35L56_ASP1_CONTROL1 0x0004804
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#define CS35L56_ASP1_CONTROL2 0x0004808
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#define CS35L56_ASP1_CONTROL3 0x000480C
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#define CS35L56_ASP1_FRAME_CONTROL1 0x0004810
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#define CS35L56_ASP1_FRAME_CONTROL5 0x0004820
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#define CS35L56_ASP1_DATA_CONTROL1 0x0004830
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#define CS35L56_ASP1_DATA_CONTROL5 0x0004840
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#define CS35L56_DACPCM1_INPUT 0x0004C00
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#define CS35L56_DACPCM2_INPUT 0x0004C08
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#define CS35L56_ASP1TX1_INPUT 0x0004C20
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#define CS35L56_ASP1TX2_INPUT 0x0004C24
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#define CS35L56_ASP1TX3_INPUT 0x0004C28
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#define CS35L56_ASP1TX4_INPUT 0x0004C2C
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#define CS35L56_DSP1RX1_INPUT 0x0004C40
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#define CS35L56_DSP1RX2_INPUT 0x0004C44
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#define CS35L56_SWIRE_DP3_CH1_INPUT 0x0004C70
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#define CS35L56_SWIRE_DP3_CH2_INPUT 0x0004C74
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#define CS35L56_SWIRE_DP3_CH3_INPUT 0x0004C78
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#define CS35L56_SWIRE_DP3_CH4_INPUT 0x0004C7C
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#define CS35L56_IRQ1_CFG 0x000E000
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#define CS35L56_IRQ1_STATUS 0x000E004
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#define CS35L56_IRQ1_EINT_1 0x000E010
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#define CS35L56_IRQ1_EINT_2 0x000E014
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#define CS35L56_IRQ1_EINT_4 0x000E01C
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#define CS35L56_IRQ1_EINT_8 0x000E02C
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#define CS35L56_IRQ1_EINT_18 0x000E054
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#define CS35L56_IRQ1_EINT_20 0x000E05C
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#define CS35L56_IRQ1_MASK_1 0x000E090
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#define CS35L56_IRQ1_MASK_2 0x000E094
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#define CS35L56_IRQ1_MASK_4 0x000E09C
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#define CS35L56_IRQ1_MASK_8 0x000E0AC
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#define CS35L56_IRQ1_MASK_18 0x000E0D4
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#define CS35L56_IRQ1_MASK_20 0x000E0DC
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#define CS35L56_DSP_VIRTUAL1_MBOX_1 0x0011020
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#define CS35L56_DSP_VIRTUAL1_MBOX_2 0x0011024
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#define CS35L56_DSP_VIRTUAL1_MBOX_3 0x0011028
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#define CS35L56_DSP_VIRTUAL1_MBOX_4 0x001102C
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#define CS35L56_DSP_VIRTUAL1_MBOX_5 0x0011030
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#define CS35L56_DSP_VIRTUAL1_MBOX_6 0x0011034
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#define CS35L56_DSP_VIRTUAL1_MBOX_7 0x0011038
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#define CS35L56_DSP_VIRTUAL1_MBOX_8 0x001103C
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#define CS35L56_DSP_RESTRICT_STS1 0x00190F0
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#define CS35L56_DSP1_XMEM_PACKED_0 0x2000000
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#define CS35L56_DSP1_XMEM_PACKED_6143 0x2005FFC
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#define CS35L56_DSP1_XMEM_UNPACKED32_0 0x2400000
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#define CS35L56_DSP1_XMEM_UNPACKED32_4095 0x2403FFC
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#define CS35L56_DSP1_SYS_INFO_ID 0x25E0000
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#define CS35L56_DSP1_SYS_INFO_END 0x25E004C
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#define CS35L56_DSP1_AHBM_WINDOW_DEBUG_0 0x25E2040
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#define CS35L56_DSP1_AHBM_WINDOW_DEBUG_1 0x25E2044
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#define CS35L56_DSP1_XMEM_UNPACKED24_0 0x2800000
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#define CS35L56_DSP1_FW_VER 0x2800010
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#define CS35L56_DSP1_HALO_STATE_A1 0x2801E58
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#define CS35L56_DSP1_HALO_STATE 0x28021E0
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#define CS35L56_DSP1_PM_CUR_STATE_A1 0x2804000
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#define CS35L56_DSP1_PM_CUR_STATE 0x2804308
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#define CS35L56_DSP1_XMEM_UNPACKED24_8191 0x2807FFC
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#define CS35L56_DSP1_CORE_BASE 0x2B80000
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#define CS35L56_DSP1_SCRATCH1 0x2B805C0
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#define CS35L56_DSP1_SCRATCH2 0x2B805C8
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#define CS35L56_DSP1_SCRATCH3 0x2B805D0
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#define CS35L56_DSP1_SCRATCH4 0x2B805D8
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#define CS35L56_DSP1_YMEM_PACKED_0 0x2C00000
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#define CS35L56_DSP1_YMEM_PACKED_4604 0x2C047F0
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#define CS35L56_DSP1_YMEM_UNPACKED32_0 0x3000000
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#define CS35L56_DSP1_YMEM_UNPACKED32_3070 0x3002FF8
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#define CS35L56_DSP1_YMEM_UNPACKED24_0 0x3400000
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#define CS35L56_MAIN_RENDER_USER_MUTE 0x3400024
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#define CS35L56_MAIN_RENDER_USER_VOLUME 0x340002C
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#define CS35L56_MAIN_POSTURE_NUMBER 0x3400094
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#define CS35L56_PROTECTION_STATUS 0x34000D8
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#define CS35L56_TRANSDUCER_ACTUAL_PS 0x3400150
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#define CS35L56_DSP1_YMEM_UNPACKED24_6141 0x3405FF4
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#define CS35L56_DSP1_PMEM_0 0x3800000
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#define CS35L56_DSP1_PMEM_5114 0x3804FE8
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/* DEVID */
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#define CS35L56_DEVID_MASK 0x00FFFFFF
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/* REVID */
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#define CS35L56_AREVID_MASK 0x000000F0
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#define CS35L56_MTLREVID_MASK 0x0000000F
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#define CS35L56_REVID_B0 0x000000B0
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/* ASP_ENABLES1 */
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#define CS35L56_ASP_RX2_EN_SHIFT 17
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#define CS35L56_ASP_RX1_EN_SHIFT 16
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#define CS35L56_ASP_TX4_EN_SHIFT 3
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#define CS35L56_ASP_TX3_EN_SHIFT 2
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#define CS35L56_ASP_TX2_EN_SHIFT 1
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#define CS35L56_ASP_TX1_EN_SHIFT 0
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/* ASP_CONTROL1 */
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#define CS35L56_ASP_BCLK_FREQ_MASK 0x0000003F
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#define CS35L56_ASP_BCLK_FREQ_SHIFT 0
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/* ASP_CONTROL2 */
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#define CS35L56_ASP_RX_WIDTH_MASK 0xFF000000
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#define CS35L56_ASP_RX_WIDTH_SHIFT 24
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#define CS35L56_ASP_TX_WIDTH_MASK 0x00FF0000
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#define CS35L56_ASP_TX_WIDTH_SHIFT 16
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#define CS35L56_ASP_FMT_MASK 0x00000700
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#define CS35L56_ASP_FMT_SHIFT 8
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#define CS35L56_ASP_BCLK_INV_MASK 0x00000040
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#define CS35L56_ASP_FSYNC_INV_MASK 0x00000004
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/* ASP_CONTROL3 */
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#define CS35L56_ASP1_DOUT_HIZ_CTRL_MASK 0x00000003
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/* ASP_DATA_CONTROL1 */
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#define CS35L56_ASP_TX_WL_MASK 0x0000003F
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/* ASP_DATA_CONTROL5 */
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#define CS35L56_ASP_RX_WL_MASK 0x0000003F
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/* ASPTXn_INPUT */
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#define CS35L56_ASP_TXn_SRC_MASK 0x0000007F
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/* SWIRETX[1..7]_SRC SDWTXn INPUT */
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#define CS35L56_SWIRETXn_SRC_MASK 0x0000007F
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/* IRQ1_STATUS */
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#define CS35L56_IRQ1_STS_MASK 0x00000001
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/* IRQ1_EINT_1 */
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#define CS35L56_AMP_SHORT_ERR_EINT1_MASK 0x80000000
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/* IRQ1_EINT_2 */
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#define CS35L56_DSP_VIRTUAL2_MBOX_WR_EINT1_MASK 0x00200000
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/* IRQ1_EINT_4 */
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#define CS35L56_OTP_BOOT_DONE_MASK 0x00000002
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/* IRQ1_EINT_8 */
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#define CS35L56_TEMP_ERR_EINT1_MASK 0x80000000
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/* Mixer input sources */
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#define CS35L56_INPUT_SRC_NONE 0x00
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#define CS35L56_INPUT_SRC_ASP1RX1 0x08
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#define CS35L56_INPUT_SRC_ASP1RX2 0x09
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#define CS35L56_INPUT_SRC_VMON 0x18
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#define CS35L56_INPUT_SRC_IMON 0x19
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#define CS35L56_INPUT_SRC_ERR_VOL 0x20
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#define CS35L56_INPUT_SRC_CLASSH 0x21
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#define CS35L56_INPUT_SRC_VDDBMON 0x28
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#define CS35L56_INPUT_SRC_VBSTMON 0x29
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#define CS35L56_INPUT_SRC_DSP1TX1 0x32
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#define CS35L56_INPUT_SRC_DSP1TX2 0x33
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#define CS35L56_INPUT_SRC_DSP1TX3 0x34
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#define CS35L56_INPUT_SRC_DSP1TX4 0x35
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#define CS35L56_INPUT_SRC_DSP1TX5 0x36
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#define CS35L56_INPUT_SRC_DSP1TX6 0x37
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#define CS35L56_INPUT_SRC_DSP1TX7 0x38
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#define CS35L56_INPUT_SRC_DSP1TX8 0x39
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#define CS35L56_INPUT_SRC_TEMPMON 0x3A
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#define CS35L56_INPUT_SRC_INTERPOLATOR 0x40
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#define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1 0x44
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#define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2 0x45
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#define CS35L56_INPUT_MASK 0x7F
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#define CS35L56_NUM_INPUT_SRC 21
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/* ASP formats */
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#define CS35L56_ASP_FMT_DSP_A 0
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#define CS35L56_ASP_FMT_I2S 2
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/* ASP HiZ modes */
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#define CS35L56_ASP_UNUSED_HIZ_OFF_HIZ 3
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/* MAIN_RENDER_ACTUAL_PS */
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#define CS35L56_PS0 0
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#define CS35L56_PS3 3
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/* CS35L56_DSP_RESTRICT_STS1 */
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#define CS35L56_RESTRICTED_MASK 0x7
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/* CS35L56_MAIN_RENDER_USER_MUTE */
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#define CS35L56_MAIN_RENDER_USER_MUTE_MASK 1
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/* CS35L56_MAIN_RENDER_USER_VOLUME */
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#define CS35L56_MAIN_RENDER_USER_VOLUME_MIN -400
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#define CS35L56_MAIN_RENDER_USER_VOLUME_MAX 400
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#define CS35L56_MAIN_RENDER_USER_VOLUME_MASK 0x0000FFC0
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#define CS35L56_MAIN_RENDER_USER_VOLUME_SHIFT 6
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#define CS35L56_MAIN_RENDER_USER_VOLUME_SIGNBIT 9
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/* CS35L56_MAIN_POSTURE_NUMBER */
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#define CS35L56_MAIN_POSTURE_MIN 0
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#define CS35L56_MAIN_POSTURE_MAX 255
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#define CS35L56_MAIN_POSTURE_MASK CS35L56_MAIN_POSTURE_MAX
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/* CS35L56_PROTECTION_STATUS */
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#define CS35L56_FIRMWARE_MISSING BIT(0)
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/* Software Values */
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#define CS35L56_HALO_STATE_SHUTDOWN 1
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#define CS35L56_HALO_STATE_BOOT_DONE 2
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#define CS35L56_MBOX_CMD_AUDIO_PLAY 0x0B000001
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#define CS35L56_MBOX_CMD_AUDIO_PAUSE 0x0B000002
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#define CS35L56_MBOX_CMD_AUDIO_REINIT 0x0B000003
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#define CS35L56_MBOX_CMD_HIBERNATE_NOW 0x02000001
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#define CS35L56_MBOX_CMD_WAKEUP 0x02000002
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#define CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE 0x02000003
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#define CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE 0x02000004
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#define CS35L56_MBOX_CMD_SHUTDOWN 0x02000005
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#define CS35L56_MBOX_CMD_SYSTEM_RESET 0x02000007
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#define CS35L56_MBOX_TIMEOUT_US 5000
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#define CS35L56_MBOX_POLL_US 250
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#define CS35L56_PS0_POLL_US 500
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#define CS35L56_PS0_TIMEOUT_US 50000
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#define CS35L56_PS3_POLL_US 500
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#define CS35L56_PS3_TIMEOUT_US 300000
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#define CS35L56_CONTROL_PORT_READY_US 2200
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#define CS35L56_HALO_STATE_POLL_US 1000
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2024-01-30 00:27:33 +08:00
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#define CS35L56_HALO_STATE_TIMEOUT_US 250000
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2023-03-20 19:22:45 +08:00
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#define CS35L56_RESET_PULSE_MIN_US 1100
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2023-10-06 19:10:37 +08:00
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#define CS35L56_WAKE_HOLD_TIME_US 1000
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2023-03-20 19:22:45 +08:00
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#define CS35L56_SDW1_PLAYBACK_PORT 1
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#define CS35L56_SDW1_CAPTURE_PORT 3
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#define CS35L56_NUM_BULK_SUPPLIES 3
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#define CS35L56_NUM_DSP_REGIONS 5
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2023-07-21 21:21:10 +08:00
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struct cs35l56_base {
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struct device *dev;
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struct regmap *regmap;
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int irq;
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struct mutex irq_lock;
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2024-03-08 21:58:58 +08:00
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u8 type;
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2023-07-21 21:21:10 +08:00
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u8 rev;
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bool init_done;
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bool fw_patched;
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bool secured;
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bool can_hibernate;
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2024-04-08 18:18:03 +08:00
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bool fw_owns_asp1;
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2024-02-23 23:39:07 +08:00
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bool cal_data_valid;
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s8 cal_index;
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struct cirrus_amp_cal_data cal_data;
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2023-07-21 21:21:10 +08:00
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struct gpio_desc *reset_gpio;
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};
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2023-03-20 19:22:45 +08:00
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extern struct regmap_config cs35l56_regmap_i2c;
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extern struct regmap_config cs35l56_regmap_spi;
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extern struct regmap_config cs35l56_regmap_sdw;
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2024-02-23 23:39:07 +08:00
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extern const struct cirrus_amp_cal_controls cs35l56_calibration_controls;
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2023-03-20 19:22:45 +08:00
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extern const char * const cs35l56_tx_input_texts[CS35L56_NUM_INPUT_SRC];
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extern const unsigned int cs35l56_tx_input_values[CS35L56_NUM_INPUT_SRC];
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2023-07-21 21:21:10 +08:00
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int cs35l56_set_patch(struct cs35l56_base *cs35l56_base);
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2024-04-08 18:18:03 +08:00
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int cs35l56_init_asp1_regs_for_driver_control(struct cs35l56_base *cs35l56_base);
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2024-01-30 00:27:26 +08:00
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int cs35l56_force_sync_asp1_registers_from_cache(struct cs35l56_base *cs35l56_base);
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2023-07-21 21:21:13 +08:00
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int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command);
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2023-07-21 21:21:18 +08:00
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int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base);
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2023-07-21 21:21:13 +08:00
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int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base);
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2023-07-21 21:21:17 +08:00
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void cs35l56_wait_control_port_ready(void);
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2023-07-21 21:21:13 +08:00
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void cs35l56_wait_min_reset_pulse(void);
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void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire);
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int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq);
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irqreturn_t cs35l56_irq(int irq, void *data);
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int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base);
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2023-07-21 21:21:14 +08:00
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int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base);
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int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire);
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2023-07-21 21:21:15 +08:00
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void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp);
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2024-02-23 23:39:07 +08:00
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int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base);
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2024-01-30 00:27:31 +08:00
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int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base,
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bool *fw_missing, unsigned int *fw_version);
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2023-07-21 21:21:16 +08:00
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int cs35l56_hw_init(struct cs35l56_base *cs35l56_base);
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2024-01-30 00:27:32 +08:00
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int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base);
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2023-03-20 19:22:45 +08:00
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int cs35l56_get_bclk_freq_id(unsigned int freq);
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void cs35l56_fill_supply_names(struct regulator_bulk_data *data);
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#endif /* ifndef __CS35L56_H */
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