2016-05-24 06:44:26 +08:00
|
|
|
/*
|
|
|
|
* GXBB clock tree IDs
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __GXBB_CLKC_H
|
|
|
|
#define __GXBB_CLKC_H
|
|
|
|
|
|
|
|
#define CLKID_CPUCLK 1
|
2016-08-22 20:49:37 +08:00
|
|
|
#define CLKID_HDMI_PLL 2
|
2016-08-03 05:40:11 +08:00
|
|
|
#define CLKID_FCLK_DIV2 4
|
2016-08-22 20:49:37 +08:00
|
|
|
#define CLKID_FCLK_DIV3 5
|
|
|
|
#define CLKID_FCLK_DIV4 6
|
2017-03-22 18:32:26 +08:00
|
|
|
#define CLKID_GP0_PLL 9
|
2016-05-24 06:44:26 +08:00
|
|
|
#define CLKID_CLK81 12
|
2016-09-07 05:38:44 +08:00
|
|
|
#define CLKID_MPLL2 15
|
2016-09-14 18:06:05 +08:00
|
|
|
#define CLKID_I2C 22
|
2017-01-19 22:58:20 +08:00
|
|
|
#define CLKID_SAR_ADC 23
|
2017-02-22 14:55:24 +08:00
|
|
|
#define CLKID_RNG0 25
|
|
|
|
#define CLKID_SPI 34
|
2016-05-24 06:44:26 +08:00
|
|
|
#define CLKID_ETH 36
|
2017-03-09 18:41:54 +08:00
|
|
|
#define CLKID_AIU_GLUE 38
|
|
|
|
#define CLKID_I2S_OUT 40
|
|
|
|
#define CLKID_MIXER_IFACE 44
|
|
|
|
#define CLKID_AIU 47
|
2016-09-05 05:31:46 +08:00
|
|
|
#define CLKID_USB0 50
|
|
|
|
#define CLKID_USB1 51
|
|
|
|
#define CLKID_USB 55
|
2017-01-17 20:08:48 +08:00
|
|
|
#define CLKID_HDMI_PCLK 63
|
2016-09-05 05:31:46 +08:00
|
|
|
#define CLKID_USB1_DDR_BRIDGE 64
|
|
|
|
#define CLKID_USB0_DDR_BRIDGE 65
|
2017-01-19 22:58:20 +08:00
|
|
|
#define CLKID_SANA 69
|
2017-01-17 20:08:48 +08:00
|
|
|
#define CLKID_GCLK_VENCI_INT0 77
|
2017-03-09 18:41:54 +08:00
|
|
|
#define CLKID_AOCLK_GATE 80
|
2016-09-14 18:06:05 +08:00
|
|
|
#define CLKID_AO_I2C 93
|
2016-08-03 05:40:11 +08:00
|
|
|
#define CLKID_SD_EMMC_A 94
|
|
|
|
#define CLKID_SD_EMMC_B 95
|
|
|
|
#define CLKID_SD_EMMC_C 96
|
2017-01-19 22:58:20 +08:00
|
|
|
#define CLKID_SAR_ADC_CLK 97
|
|
|
|
#define CLKID_SAR_ADC_SEL 98
|
2017-03-22 18:18:53 +08:00
|
|
|
#define CLKID_MALI_0_SEL 100
|
|
|
|
#define CLKID_MALI_0 102
|
|
|
|
#define CLKID_MALI_1_SEL 103
|
|
|
|
#define CLKID_MALI_1 105
|
|
|
|
#define CLKID_MALI 106
|
2016-05-24 06:44:26 +08:00
|
|
|
|
|
|
|
#endif /* __GXBB_CLKC_H */
|