2019-05-19 20:07:45 +08:00
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# SPDX-License-Identifier: GPL-2.0-only
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2014-06-06 04:42:39 +08:00
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config CRYPTO_DEV_QAT
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tristate
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select CRYPTO_AEAD
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select CRYPTO_AUTHENC
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2019-10-26 03:41:13 +08:00
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select CRYPTO_SKCIPHER
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2015-07-16 06:28:38 +08:00
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select CRYPTO_AKCIPHER
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2016-07-07 22:27:29 +08:00
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select CRYPTO_DH
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2015-06-17 14:58:24 +08:00
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select CRYPTO_HMAC
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2016-07-04 17:49:28 +08:00
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select CRYPTO_RSA
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2014-06-06 04:42:39 +08:00
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select CRYPTO_SHA1
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select CRYPTO_SHA256
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select CRYPTO_SHA512
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2021-01-04 23:35:15 +08:00
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select CRYPTO_LIB_AES
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2014-06-25 06:19:29 +08:00
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select FW_LOADER
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crypto: qat - introduce support for PFVF block messages
GEN2 devices use a single CSR for PFVF messages, which leaves up to 10 bits
of payload per single message. While such amount is sufficient for the
currently defined messages, the transfer of bigger and more complex data
streams from the PF to the VF requires a new mechanism that extends the
protocol.
This patch adds a new layer on top of the basic PFVF messaging, called
Block Messages, to encapsulate up to 126 bytes of data in a single
logical message across multiple PFVF messages of new types (SMALL,
MEDIUM and LARGE BLOCK), including (sub)types (BLKMSG_TYPE) to carry the
information about the actual Block Message.
Regardless of the size, each Block Message uses a two bytes header,
containing the version and size, to allow for extension while
maintaining compatibility. The size and the types of Block Messages are
defined as follow:
- small block messages: up to 16 BLKMSG types of up to 30 bytes
- medium block messages: up to 8 BLKMSG types of up to 62 bytes
- large block messages: up to 4 BLKMSG types of up to 126 bytes
It effectively works as reading a byte at a time from a block device and
for each of these new Block Messages:
- the requestor (always a VF) can either request a specific byte of the
larger message, in order to retrieve the full message, or request the
value of the CRC calculated for a specific message up to the provided
size (to allow for messages to grow while maintaining forward
compatibility)
- the responder (always the PF) will either return a single data or CRC
byte, along with the indication of response type (or error).
This patch provides the basic infrastructure to perform the above
operations, without defining any new message.
As CRCs are required, this code now depends on the CRC8 module.
Note: as a consequence of the Block Messages design, sending multiple
PFVF messages in bursts, the interrupt rate limiting values on the PF are
increased.
Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-16 17:13:26 +08:00
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select CRC8
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2014-06-06 04:42:39 +08:00
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config CRYPTO_DEV_QAT_DH895xCC
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tristate "Support for Intel(R) DH895xCC"
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2022-06-17 17:59:45 +08:00
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depends on PCI && (!CPU_BIG_ENDIAN || COMPILE_TEST)
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2014-06-06 04:42:39 +08:00
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select CRYPTO_DEV_QAT
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help
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Support for Intel(R) DH895xcc with Intel(R) QuickAssist Technology
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for accelerating crypto and compression workloads.
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To compile this as a module, choose M here: the module
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will be called qat_dh895xcc.
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2015-08-08 02:34:31 +08:00
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2015-12-05 08:56:34 +08:00
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config CRYPTO_DEV_QAT_C3XXX
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tristate "Support for Intel(R) C3XXX"
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2022-06-17 17:59:45 +08:00
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depends on PCI && (!CPU_BIG_ENDIAN || COMPILE_TEST)
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2015-12-05 08:56:34 +08:00
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select CRYPTO_DEV_QAT
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help
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Support for Intel(R) C3xxx with Intel(R) QuickAssist Technology
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for accelerating crypto and compression workloads.
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To compile this as a module, choose M here: the module
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will be called qat_c3xxx.
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2015-12-05 08:56:40 +08:00
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config CRYPTO_DEV_QAT_C62X
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tristate "Support for Intel(R) C62X"
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2022-06-17 17:59:45 +08:00
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depends on PCI && (!CPU_BIG_ENDIAN || COMPILE_TEST)
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2015-12-05 08:56:40 +08:00
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select CRYPTO_DEV_QAT
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help
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Support for Intel(R) C62x with Intel(R) QuickAssist Technology
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for accelerating crypto and compression workloads.
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To compile this as a module, choose M here: the module
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will be called qat_c62x.
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2020-11-14 00:46:43 +08:00
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config CRYPTO_DEV_QAT_4XXX
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tristate "Support for Intel(R) QAT_4XXX"
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2022-06-17 17:59:45 +08:00
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depends on PCI && (!CPU_BIG_ENDIAN || COMPILE_TEST)
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2020-11-14 00:46:43 +08:00
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select CRYPTO_DEV_QAT
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help
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Support for Intel(R) QuickAssist Technology QAT_4xxx
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for accelerating crypto and compression workloads.
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To compile this as a module, choose M here: the module
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will be called qat_4xxx.
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2015-08-08 02:34:31 +08:00
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config CRYPTO_DEV_QAT_DH895xCCVF
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tristate "Support for Intel(R) DH895xCC Virtual Function"
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2022-06-17 17:59:45 +08:00
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depends on PCI && (!CPU_BIG_ENDIAN || COMPILE_TEST)
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2015-08-08 02:34:31 +08:00
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select PCI_IOV
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2015-08-12 02:05:37 +08:00
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select CRYPTO_DEV_QAT
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2015-08-08 02:34:31 +08:00
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help
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Support for Intel(R) DH895xcc with Intel(R) QuickAssist Technology
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Virtual Function for accelerating crypto and compression workloads.
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To compile this as a module, choose M here: the module
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will be called qat_dh895xccvf.
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2015-12-05 08:56:45 +08:00
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config CRYPTO_DEV_QAT_C3XXXVF
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tristate "Support for Intel(R) C3XXX Virtual Function"
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2022-06-17 17:59:45 +08:00
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depends on PCI && (!CPU_BIG_ENDIAN || COMPILE_TEST)
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2015-12-10 03:59:47 +08:00
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select PCI_IOV
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2015-12-05 08:56:45 +08:00
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select CRYPTO_DEV_QAT
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help
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Support for Intel(R) C3xxx with Intel(R) QuickAssist Technology
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Virtual Function for accelerating crypto and compression workloads.
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To compile this as a module, choose M here: the module
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will be called qat_c3xxxvf.
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2015-12-05 08:56:51 +08:00
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config CRYPTO_DEV_QAT_C62XVF
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tristate "Support for Intel(R) C62X Virtual Function"
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2022-06-17 17:59:45 +08:00
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depends on PCI && (!CPU_BIG_ENDIAN || COMPILE_TEST)
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2015-12-10 03:59:47 +08:00
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select PCI_IOV
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2015-12-05 08:56:51 +08:00
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select CRYPTO_DEV_QAT
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help
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Support for Intel(R) C62x with Intel(R) QuickAssist Technology
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Virtual Function for accelerating crypto and compression workloads.
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To compile this as a module, choose M here: the module
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will be called qat_c62xvf.
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